GB2002960A - Charge transfer memory apparatus - Google Patents
Charge transfer memory apparatusInfo
- Publication number
- GB2002960A GB2002960A GB7833698A GB7833698A GB2002960A GB 2002960 A GB2002960 A GB 2002960A GB 7833698 A GB7833698 A GB 7833698A GB 7833698 A GB7833698 A GB 7833698A GB 2002960 A GB2002960 A GB 2002960A
- Authority
- GB
- United Kingdom
- Prior art keywords
- rows
- column
- charge packets
- ctd
- electrodes
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
- H01L27/1057—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components comprising charge coupled devices [CCD] or charge injection devices [CID]
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
- G11C19/287—Organisation of a multiplicity of shift registers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/38—Digital stores in which the information is moved stepwise, e.g. shift registers two-dimensional, e.g. horizontal and vertical shift registers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C27/00—Electric analogue stores, e.g. for storing instantaneous values
- G11C27/04—Shift registers
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Solid State Image Pick-Up Elements (AREA)
- Measurement And Recording Of Electrical Phenomena And Electrical Characteristics Of The Living Body (AREA)
Abstract
In a CTD, M(eg3) rows of charge transfer channels 11-13 each have identical sets of r(eg4) electrodes 31-34. In response to a first set of clocking voltages, N(eg4) charge packets, each of which is a sampled analog signal, are initially entered in parallel from an input shift register 45 vertically into the N successive stages contained in a first one 11 of the M horizontal rows, and concurrently the charge packets just previously stored in the first to (M-1)<th> rows, are transferred vertically for storage in the respectively like-numbered ones of the N stages, of the second to M<th> rows, respectively. This transfer is effected through channels 36c,36d connecting the (r-1)<th> electrode 33 of one row to the first electrode 31 of the next row. The entry and shifting continues in successive steps, until M such sequences, each containing N charge packets, are loaded in the array. Then, in response to a second set of clocking voltages applied to the sets of r electrodes 31-34, transfers are made horizontally in repeated steps, such that in each step the contents of the N<th> column are shifted out of the array and are read, those of the (N-1)<th> column are shifted into the N<th> column, etc. The CTD is suitable for integrated circuit fabrication and is usable for re-sorting the order of analog signal samples, such as in radar, colour television, image display, or medical electronics applications. <IMAGE>
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US05/825,924 US4125786A (en) | 1977-08-19 | 1977-08-19 | Charge transfer memory apparatus |
US05/878,427 US4125785A (en) | 1978-02-16 | 1978-02-16 | Charge transfer memory apparatus |
Publications (2)
Publication Number | Publication Date |
---|---|
GB2002960A true GB2002960A (en) | 1979-02-28 |
GB2002960B GB2002960B (en) | 1982-01-13 |
Family
ID=27124958
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB7833698A Expired GB2002960B (en) | 1977-08-19 | 1978-08-17 | Charge transfer memory apparatus |
Country Status (3)
Country | Link |
---|---|
DE (2) | DE2835950A1 (en) |
GB (1) | GB2002960B (en) |
IL (1) | IL55367A (en) |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3953837A (en) * | 1974-11-27 | 1976-04-27 | Texas Instruments Incorporated | Dual serial-parallel-serial analog memory |
US3958210A (en) * | 1975-02-05 | 1976-05-18 | Rca Corporation | Charge coupled device systems |
US4001878A (en) * | 1975-11-19 | 1977-01-04 | Rca Corporation | Charge transfer color imagers |
-
1978
- 1978-08-16 IL IL55367A patent/IL55367A/en unknown
- 1978-08-17 DE DE19782835950 patent/DE2835950A1/en active Granted
- 1978-08-17 GB GB7833698A patent/GB2002960B/en not_active Expired
- 1978-08-17 DE DE19787824494U patent/DE7824494U1/en not_active Expired
Also Published As
Publication number | Publication date |
---|---|
DE2835950A1 (en) | 1979-07-05 |
IL55367A (en) | 1981-07-31 |
DE7824494U1 (en) | 1979-01-18 |
IL55367A0 (en) | 1978-10-31 |
GB2002960B (en) | 1982-01-13 |
DE2835950C2 (en) | 1989-10-05 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PCNP | Patent ceased through non-payment of renewal fee |