GB1604589A

GB1604589A - Analogue to digital convertor

Info

Publication number: GB1604589A
Application number: GB9413/78A
Authority: GB
Original assignee: Cambridge Consultants Ltd
Current assignee: Cambridge Consultants Ltd
Priority date: 1978-05-31
Filing date: 1978-05-31
Publication date: 1981-12-09

Description

(54) ANALOGUE TO DIGITIAL CONVERTOR (71) We, CAMBRIDGE CONSULTANTS LIMITED, a British Company of Bar Hill, Cambridge do hereby declare the invention, for which we pray that a patent may be granted to us and the method by which it is to be performed, to be particularly described in and by the following statement: This invention relates to analogue to digital convertors and is particularly concerned with such convertors operable at high speed.

A variety of different forms of analogue to digital convertors are known, for example as described in the article entitled "High Speed Analogue to Digital Conversion Techniques" by Dr. Christopher Davies in "Electronic Engineering" May 1976 pages 43 to 45. One type of convertor described in that article is called a "parallel - series" convertor and comprises a sample/hold circuit for repeatedly sampling the analogue signal to be digitized and a series of two or more stages, the first operable to generate the most significant bit or bits of the required number by quantizing the sampled signal, and the next stage operable to generate the next most significant bit or bits by quantizing the difference between the quantized signal of the first stage and the signal in the sample/hold circuit.Similarly, any succeeding stages generate the bit or bits of successively lower significance by quantizing the residue of the signal left over by the preceding stage. The difficulty with such circuits is that if the number of stages is increased to increase the accuracy of the device by increasing the number of bits in the final number, the longer it takes for each binary number to be obtained.

In one aspect, the present invention provides a method of analogue to digital conversion for generating a series of numbers representing successive values of an input analogue signal, comprising: (a) during a first time period quantizing a received analogue signal to generate at least one first bit of a said number; (b) during a second time period quantizing the residue of said signal quantized during the first time period to obtain at least one further bit of said number, more than one said bit of said number being generated during one at least of said first and second time periods; (c) also during said second period quantizing a further received analogue signal to generate a said at least one first bit of a succeeding said number; and (d) repeating said quantization so as to make complete successive said numbers available in successive said periods.

In another aspect, the present invention provides an analogue to digital converter for generating a succession of numbers representing successive values of an analogue input signal, comprising (a) a first quantizing means defining a plurality of quantization levels and operable to generate at least one first bit by determining the quantization level equal to or immediately below the level of an analogue signal received by said first quantizing means; (b) means to provide an output analogue signal representing the difference between said received analogue signal and said determined quantization level; (c) analogue store means for storing said output analogue signal;; (d) a second quantizing means defining a plurality of quantization levels and operable to generate at least one second bit of lower significance than said at least one first bit by determining which of the quantization levels defined by said second quantizing means is equal to or immediately below the level of said stored analogue signal, and (e) control means operable to cause said first quantizing means to generate said at least one first bit of successive said numbers respectively during successive periods in which said second quantizing means generates said at least one second bit of the preceding said number; and wherein one at least of the first and second quantizing means is operable to generate more than one said bit during each successive period.

In a preferred embodiment, the first quantizing means generates the most significant bit or bits, the signal supplied thereto being successive samples of a varying analogue input signal. However, it Is alternatively possible in the scope of the invention for the most significant bit or bits to be obtained by some other means, and the arrangement of the invention would be incorporated in the circuit just to obtain the bit or bits of lower significance.

In the scope of the invention, there may be just the two quantization processes or alternatively more quantization processes may be carried out, to obtain more bits of successively less significance, by including further quantizing means and associated circuitry. There may be included between each pair of quantizing means a said means to generate an output analogue signal representing the difference between the analogue signal received by the preceding quantizing means and the quantization level determined thereby and an analogue store means for storing the said output analogue signal.

The invention is described rurther by way of example with reference to the accompanying drawings, in which: Figure I is a block diagram of a four stage analogue to digital convertor producing an eight bit output, according to an embodiment of the invention; Figure 2 is a diagram illustrating the way in which the analogue signal is quantized in successive stages of the convertor of Figure 1; Figure 3 is a diagram illustrating the timing of the quantization processes carried out by successive stages in the convertor of Figure 1; Figure 4 is a block diagram illustrating in more detail one form which each stage of the convertor of Figure 1 may take; Figure 5 is a diagram similar to Figure 4, but showing an alternative form which each stage may take; and Figure 6 is a block diagram similar to Figure 1 but showing an alternative embodiment of the invention.

With reference to Figures 1 to 4, the analogue to digital convertor comprises a sample/hold circuit 10 having an input terminal 12 to which an analogue signal Vj to be digitized is applied, and four successive stages labelled stage 1 to stage 4 each of which produces two bits of the required digital output, stage 1 producing the two most significant bits, stage 2 the next most significant bits, stage 3 the next most significant bits and stage 4 the least significant bits. Control logic 14 controls the timing of the operations performed by the sample/hold circuit 10 and stages 1 to 4.In order to explain the operation of the convertor, a numerical example will be assumed in which the input signal Vi has a value, when digitized, equal to the binary number: 10001011 During a first time period T1 (Figure 3) defined by the control logic 14, sample/hold circuit 10 samples the value of the input signal Vj and supplies the sampled value, say Vj1, to stage 1. Each stage includes a further sample/hold circuit 16 and this circuit of stage 1 receives the sampled value Vjl or Vj from the circuit 10 and holds this value while it is quantized in stage 1.The quantization process carried out in stage 1 involves determining whether the sampled value of Vj is between voltage levels V0 and V1, or V1 and V2 or V2 and V3 or V3 and V4, where V0 and V4 represent the minimum and maximum values of the signal Vj which can be digitized in the convertor and: V1 = t V4 V2 = i V4 V3 = i V4 To determine which of the above mentioned voltage bands the sampled value of Vj falls within, the output of the sample/hold circuit 16 is applied to three comparators 18, 20 and 22 to which voltages V1, V2 and V3 are also respectively applied. The outputs of the comparators 18, 20 and 22 are applied to a level coding circuit 24 which generates at its outputs 24a and 24b the binary digits 00, 01, 10 or 11 according to whether the comparators indicate that the sampled value of the signal Vj is within the voltage band V0 to V1, V1 to V2, V2 to V3, V3 to V4. In the example under discussion, the sampled value of input signal Vj is shown to be within the band V2 to V3 and therefore the circuit 24 generates the binary digits 10, which constitute the two most significant bits of the required binary number. Since the remaining bits of the required binary number have not yet been generated, the digits output by the circuit 24 are supplied to a bit delay store 26.

The outputs of the comparators 18, 20 and 22 are also supplied to a current digital to analogue convertor 28 which supplies to a summing junction 30 a current representative of the value V0, V1, V2 or V3 according to whether the value of Vi1 falls within the band V0 to Vl, V1 to V2, V2 to V3 or V3 to V4. Thus, in the example under discussion, the current supplied by the convertor 28 to the summing junction 30 is representative of the value V2.

The summing junction 30 also receives, from the output of a voltage to current convertor 32 whose input is connected to the output of sample/hold circuit 16, a current representative of the value Vi1 held in the sample/hold circuit 16. The summing junction 30 is connected to ground through a resistor 34 and to the input of a buffer amplifier 36, and the arrangement is such that the buffer amplifier 36 outputs a signal representative of V11 minus V2, which signal is applied to stage 2 of the convertor. The timing of the operations which take place within stage 1 are controlled by stage timing logic 38 which receives signals from the control logic 14, and applies appropriate control signals to the sample/hold circuit 16, the comparators 18, 20 and 22 and the bit delay store 26.

The function of stage 2 is to determine the next two most significant digits of the required binary output. This is done by quantizing the signal Vi1 minus V2 to determine where, within the band V2 to V3, the sampled value of Vi actually falls. In particular, if Vi1 minus V2 is less than V'l then the next two most significant digits are 00 (as in the example under discussion), if V11 minus V2 is within the band V'l to V'2 the next two digits are 01, if within the band V'2 to V'3 the next two digits are 10 and if within the band V'3 to V'4 the next two digits are 11. This determination is carried out during time interval T2, which immediately follows time interval Tl, and is defined by the control logic 14.Stage 2 is identical to stage 1 in its construction and operation, and thus during time interval T2 the difference V11 minus V2 is stored within the sample/hold circuit 16 of stage 2. Also during time T2, the bits stored in bit delay store 26 of stage 1 are transferred to the corresponding bit delay store of stage 2 which, therefore, has capacity for storing both the two bits generated in stage 2 and the two bits obtained from stage 1.

Also during period T2, the logic 14 causes the sample/hold circuit 10 to take a new example V2 of the value of the input signal Vi, this being transferred to the sample/hold circuit 16 of stage 1 and quantized, as described previously, to obtain the two most significant bits of the binary number representing V12, which bits are stored in the bit delay 26.

During period T3, the difference signal obtained from the buffer amplifier 36 of stage 2 is applied to stage 3 and stored in the sample/hold circuit 16 thereof for quantization to determine the next two most significant bits of the required binary number. Also during period T3, the contents of the bit delay 26 of stage 2 i.e. the four most significant bits of the binary number representing Vi1, are transferred to the bit delay store 26 of stage 3 which of course also receives and stores, during this period T3, the two bits obtained in stage 3, so that the bit delay 26 of stage 3 then contains the six most significant bits of the binary number representing the value of Vjl. In the example under discussion, these six most significant bits are 100010.

Also during period T3, the two most significant bits of the binary number representing Vj2 are transferred from the bit delay store 26 of stage 1 to the bit delay store 26 of stage 2 and stage 2 obtains the next two most significant bits of the binary number representing V12 by quantizing the difference signal obtained from the buffer amplifier 36 of stage 1 obtained during period T2. Further, during period T3, sample/hold circuit 10 takes a third sample Vj3 of the input signal Vi and this is quantized, in the manner previously described, by stage 1, the two most significant bits thus obtained stored in store 26 of stage 1 and a difference signal generated at the buffer amplifier 36 of stage 1 for supply into the sample/hold circuit 16 of stage 2 during period T4.

Also during period T4, the difference signal obtained during period T3 at the output of the buffer amplifier 36 of stage 3 is supplied into the sample/hold circuit 16 of stage 4 and the six most significant bits of the binary number representing Vj1 transferred from the bit delay store 26 of stage 3 into the bit delay store 26 of stage 4 which, upon completion of the quantization of the difference signal obtained from stage 3, will thus contain an eigth bit binary number representing Vj1.

The process proceeds as described above so that during period T5 an eight bit binary number is available in the bit delay store of stage 4 representing the value of signal Vj2, and during period T6 an eight bit number representing the value of signal Vj3 is available in the bit delay store 26 of stage 4.

Accordingly, it will be understood from the above, that when the convertor is in operation, the sample/hold circuit 10 does not need to hold a single sample for the whole period required to generate the eight bit binary number representing the sampled value of the signal, and that the time taken, once the device is in operation, for each successive number to be generated is equal to the time taken for a single stage to quantize its received analogue signal, so that a high conversion rate is obtainable.

In the above description, and in Figure 2, it has been assumed for simplicity that the difference signal output by the buffer amplifier of one stage to the next stage becomes smaller and smaller stage by stage. In practice, this difference signal will be amplified so that in the last stages it does not become unmeasurable. In particular, in the embodiments shown in Figure 2, the arrangement of the voltage to current convertor 32, resistor 34 and buffer amplifier 36 should be such as to amplify the difference signal by a factor of four so that the voltages at which the successive stages are operating will all be the same.

In the embodiment of Figure 5, the same reference numbers are used to indicate parts corresponding to those present in Figure 4. However, a differential sample/hold circuit 16a is used instead of the sample/hold circuit 16 and thus the difference signal required by, say, stage 2 is obtained from stage 1 by applying to the differential sample/hold circuit 16a of stage 2 a signal obtained directly from the output of the differential sample/hold circuit 16a of stage 1 and a voltage of V0, V1, V2 or V3 according to the quantization level measured in stage 1. A voltage switch 40, controlled by the outputs of the comparators 18, 20 and 22 is provided for this purpose.

In the embodiments so far described, the four stages have been identical with each other.

This is convenient if each stage is to be implemented as an integrated circuit even though strictly speaking the sample/hold circuit 16 of the first stage is not required since there is an external sample/hold circuit 10, which must of course be capable of sampling a signal which may be varying rapidly whereas the sample/hold circuits 16 of the succedding stages do not need to be capable of such operation, and even though the bit delay store 26 of each stage except the last stage will consequently contain excess capacity, it being only the bit store of the last stage which has to be capable of storing the full eight bits of the final word: the store of the first stage only stores two bits, the second stage four bits and the third stage six bits.

However, it is possible within the scope of the invention to provide convertors in which all the stages are not identical. In particular, higher speeds of operation can be achieved at the cost of increasing the number of stages by arranging for the stage computing the more significant bits to compute fewer bits than those computing the bits of lower significance.

Figure 6 shows an embodiment of the invention in a sixteen bit analogue to digital convertor in which the stages are not identical with each other. In Figure 6, each of stages 1 to 3 produces only one bit and thus each stage can be highly accurate at high speed. Each of stages 1 to 3 thus may contain one comparator and each of stages 2 and 3 also contains a sample/hold circuit such as 16 or 16a which stores the difference signal from the preceding stage. Thus, stages 1 to 3 compute the three most significant digits at high speed and with great accuracy. Stage 4 computes the next two most significant digits and thus includes three comparators and a sample/hold circuit in the manner of Figure 4 or Figure 5.Stage 5 computes the next three most significant digits and contains a sample/hold circuit such as 16 or 16a for receiving the difference signal from stage 4 and, in order to determine the next three most significant digits, seven comparators thus permitting quantization of the signal to eight levels. Stage 6 contains a sample/hold circuit for receiving the difference signal from stage 5 and produces the eight least significant bits, for example by means of an integrated circuit 50 containing a bank of 255 comparators for quantizing the difference signal obtained from stage 5 to the required number of levels.

In the embodiment of Figure 6, since each of the first three stages contains only a single comparator little amplification is necessary for the difference signal supplied from one stage to the next. Thus, little time is required for the amplified signal to settle down and the quantization process carried out by the first three stages can therefore be effected at high speed and accuracy. Stage 4 also operates at high speed but with lower accuracy and the subsequent stages also at high speed and with even lower accuracy. By way of example, the accuracy needed in each of the stages of the Figure 6 embodiment is summarised as follows: Stage Number Number of Bit Decisions Precision Needed 1 1 1 in 65,520 2 1 1 in 32,768 3 1 1 in 16,384 4 2 1 in 8,192 5 3 1 in 2,048 6 8 1 in 256 Various modifications are possible within the scope of the invention.For example, it will be possible to incorporate so-called "redundancy" comparators in one or more of the stages in order to detect quantization errors in the preceding stages as described in the article "Design of Convertor Circuits" by R. Smith-Saville IEE Seminar on High Speed Analogue to Digital Conversion October 1975 pages 3.1 to 3.19 or in the article "A Method to Increase the Accuracy of Fast Serial Parallel Analogue to Digital Convertors" by T.C.

Verster IEEE Transactions on Electronic Computers, August 1964 pages 471 to 473. The use of such techniques will enable the convertor to operate at even higher speed, since each individual stage does not have to be absolutely accurate in its decisions, so long as the difference signal passed on to the next stage is accurate. Further, the examples given are not limiting on the scope of the invention. Analogue to digital convertors producing outputs with any desired number of bits may be made within the scope of the invention.As a further example, a fourteen bit analogue to digital convertor might comprise three stages, the first determining the two most significant bits, the next stage determining the next four bits and the third stage the final eight bits, with a sample/hold circuit between each successive pair of stages, each for storing the difference signal obtained in the preceding stage.

It will be understood from the foregoing description that although in Figure 2 the range of values of the input analogue signal Vj which can be digitized is from V0 = 0 to V4 there is in fact no means to determine if the value of Vi falls outside this range. Thus, in fact the comparator 18 merely determines whether Vj is less than V1, and not whether it is above V0 = 0, and the comparator 22 merely determines whether Vj is greater than V3, and not whether it is also less than V4. However, if desired, additional comparators could be included so to determine definitely whether Vi is above V0 and less than V4.From this, it will be understood that although, in the illustrated embodiments of Figures 1 to 5, Vj is quantized to the four levels V0 = 0, V1, V2 and V3 only the levels, V1, V2 and V3 are actually defined by comparators, V0 = 0 being "defined" merely by the fact that the current digital to analogue convertor 28 will output 0 volts if Vj is less than V1: mis-operation of the circuit will therefore result if Vj falls outside the range V0 to V4.

References to definition of quantization levels in the following claims should, therefore, be construed as including arrangements such as those shown in Figures 4 and 5 where one or other of the levels is implicit from the operating range of the circuit, even though not being positively defined by means such as a comparator. Thus, for example, in the embodiment of Figure 6 each of the first three stages, each generating only one bit, may be provided with just a single comparator which determines whether the analogue signal received by the stage is above or below the quantization level represented by the voltage defined by that comparator, the other quantization level being for example zero volts and being defined merely by the operable range of the circuit.

It has been assumed in the foregoing description that the analogue signals are of positive sign. It should be clearly understood that the analogue signals may be positive or negative within the scope of the invention, and references to quantization levels "below" the level of the analogue signal, should be construed accordingly in the following claims.

WHAT WE CLAIM IS: 1. An analogue to digital converter for generating a succession of numbers representing successive values of an analogue input signal, comprising: (a) a first quantizing means defining a plurality of quantization levels and operable to generate at least one first bit by determining the quantization level equal to or immediately below the level of an analogue signal received by said first quantizing means; (b) means to provide an output analogue signal representing the difference between said received analogue signal and said determined quantization level;

**WARNING** end of DESC field may overlap start of CLMS **.

Claims

**WARNING** start of CLMS field may overlap end of DESC **. Stage Number Number of Bit Decisions Precision Needed

1 1 1 in 65,520

2 1 1 in 32,768

3 1 1 in 16,384

4 2 1 in 8,192

5 3 1 in 2,048

6 8 1 in 256 Various modifications are possible within the scope of the invention. For example, it will be possible to incorporate so-called "redundancy" comparators in one or more of the stages in order to detect quantization errors in the preceding stages as described in the article "Design of Convertor Circuits" by R. Smith-Saville IEE Seminar on High Speed Analogue to Digital Conversion October 1975 pages 3.1 to 3.19 or in the article "A Method to Increase the Accuracy of Fast Serial Parallel Analogue to Digital Convertors" by T.C.

(c) analogue store means for storing said output analogue signal; (d) a second quantizing means defining a plurality of quantization levels and operable to generate at least one second bit of lower significance than said at least one first bit by determining which of the quantization levels defined by said second quantizing means is equal to or immediately below the level of said stored analogue signal, and (e) control means operable to cause said first quantizing means to generate said at least one first bit of successive said numbers respectively during successive periods in which said second quantizing means generates said at least one second bit of the preceding said number; and wherein one at least of the first and second quantizing means is operable to generate more than one said bit during each successive period.

2. A converter according to claim 1, including sample/hold means controlled by said control means to sample said analogue input signal repeatedly, said analogue signal received by said first quantizing means being the signal held by said sample/hold means so that said first quantizing means thereby generates the most significant bit or bits of each said number.

3. A convertor according to claim 1 or 2, including a further means to provide an analogue output signal representing the difference between the quantization level determined by said second quantizing means and said stored analogue signal; further analogue store means for storing the output analogue signal provided by said further means; and further quantizing means defining a plurality of quantization levels and operable to generate at least one further bit of lower significance than said at least one second bit by determining which of the quantization levels defined by said further quantizing means is equal to or immediately below the level of the analogue signal stored in said further analogue store means, said control means causing said further quantizing means to generate said at least one further bit of one said number during a period in which said second quantizing means and said first quantizing means generate said at least one second bit and said at least one first bit of respective succeeding said numbers.

4. A convertor according to claim 3, including a succession of said further means to provide an output analogue signal, said further analogue store means and said further quantizing means each for generating at least one bit of successively lower significance, said control means causing the last of said succession of quantizing means to generate the least significant bit or bits of one number during a period in which the preceding quantizing means each generate a bit or bits of higher significance of respective successive numbers.

5. A convertor according to any preceding claim, including bit delay store means associated with each quantizing means (except if desired the quantizing means generating the bit or bits of lowest significance) and operable to make all of the bits of the same number available simultaneously.

6. A convertor according to any preceding claim, including means to provide gain to the or at least one of said analogue output signals.

7. A convertor according to claim 6, wherein the gain provided to said output analogue signal is substantially equal to the number of quantization levels defined by the preceding quantizing means.

8. A convertor according to any preceding claim, wherein a said quantizing means generating bits of lower significance generates more said bits than a said quantizing means generating a bit or bits of higher significance.

9. A convertor according to any preceding claim, wherein at least one of the quantizing means includes a current digital to analogue convertor operable to generate a current representative of the quantization level determined thereby and the means to provide an output analogue signal comprises a voltage to current convertor for converting the analogue signal received by said at least one quantizing means to current, and summing means operable to provide current representing the difference between said currents from the digital to analogue convertor and the voltage to current convertor.

10. A convertor according to any preceding claim, wherein the or at least one of said analogue store means comprises a sample/hold circuit.

11. A convertor according to any of claims 1 to 8, wherein said or at least one of said means to provide an output analogue signal and analogue store means are together constituted by a differential sample/hold circuit connected to the preceding quantizng means to receive the analogue signal received thereby and an analogue signal representing the quantization level determined thereby.

12. A converter according to any of claims 1 to 10, comprising a plurality of similar stages, each stage including a said analogue store means, a said quantizing means for quantizing the signals stored in the analogue store means of the same stage, and the said means to provide an output analogue signal representing the difference between the analogue signal received by the same stage and the determined quantization level.

13. A converter according to claim 11, comprising a plurality of similar stages, each stage including a said differential sample/hold circuit and said quantizing means operable to quantize the signal stored in the differential sample and hold circuit of the same stage.

14. A converter according to claim 12 or 13, wherein each stage is implemented as an integrated circuit.

15. A method of analogue to digital conversion for generating a series of numbers representing successive values of an input analogue signal, comprising: (a) during a first time period quantizing a received analogue signal to generate at least one first bit of a said number; (b) during a second time period quantizing the residue of said signal quantized during the first time period to obtain at least one further bit of said number, more than one said bit of said number being generated during one at least of said first and second time periods; (c) also during said second period quantizing a further received analogue signal to generate a said at least one first bit of a succeeding said number; and (d) repeating said quantization so as to make complete successive said numbers available in successive said periods.

16. An analogue to digital convertor, substantially as herein described with reference to and as illustrated in Figures 1 to 3 of the accompanying drawings.

17. An analogue to digital convertor, substantially as herein described with reference to and as illustrated in Figures 1 to 4 of the accompanying drawings.

18. An analogue to digital convertor, substantially as herein described with reference to and as illustrated in Figures 1 to 3 and 5 of the accompanying drawings.

19. An analogue to digital convertor, substantially as herein described with reference to and as illustrated in Figure 6 of the accompanying drawings.

20. A method of analogue to digital conversion substantially as herein described with reference to Figures 1 to 4 of the accompanying drawings.

21. A method of analogue to digital conversion substantially as herein described with reference to Figures 1 to 3 and 5 of the accompanying drawings.

22. A method of analogue to digital conversion substantially as herein described with reference to Figure 6 of the accompanying drawings.