GB1603837A - Remote control systems - Google Patents

Description

(54) REMOTE CONTROL SYSTEMS (71) We, HOLDSWORTH ELEC TRONIC DEVELOPMENTS LIMITED, a company incorporated in the United Kingdom, of Victoria Avenue, Harrogate, North Yorkshire, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement:- This invention relates to remote control systems.

One application of the present invention is to remote control systems for operating machines. For example in mining, certain machines are required to be controlled in remote fashion by an operator in order to remove the operator from the potentially dangerous location of the machine. One such machine is a coal cutter for use at the coal face in a coal mine.

One known remote control system for a mining machine comprises a plurality of input channels at a data transmitter to be used by the operator, and a corresponding plurality of receiver channels at a data receiver mounted on the machine. Channels energised at the transmitter cause energisation of the corresponding channels at the receiver, and thus the appropriate controlled action to take place at the machine. Each associated pair of input and output channels operates on a particular frequency (for example radio frequency) which of course must be different from the frequencies of the other channels to avoid spurious control actions. The result of this is that as many different frequencies pass between the transmitter and receiver as there are input or output channels.

According to the present invention there is provided a remote control system comprising a control data transmitter and a control data receiver, said control data transmitter comprising: time multiplexing means having a plurality of data input lines and a data output line, said time multiplexing means being operable to multiplex in time between said data input lines onto said data output line; and frequency generating means for generating a frequency in response to a predetermined logic level signal on said data output line; said control data receiver comprising: frequency decoding means for converting said frequency generated by said frequency generating means into a logic level signal; and time demultiplexing means having a data input line connected to said frequency decoding means and a plurality of data output lines for providing a plurality of control channels, said demultiplexing means being operable to multiplex in time from said data input line onto said data output lines; the system comprising at least one safety function means operable to shut-down to safety the control data receiver in the event of detection of a faulty operating condition.

The invention enables a large number of input and output transmission channels or lines to be provided, with merely a low number of frequencies passing therebetween. A remote control system according to the invention operating on a low number of frequencies and with narrow band width is less likely to be affected by spurious noise than is a remote control system operating on a high number of frequencies.

Preferably, said frequency generating means is adapted to generate tw.o frequencies in response to logic high and low respectively on said data output line, said frequency decoding means being operable to recognise both said two frequencies. In a preferred embodiment, only one of these frequencies is employed to signify transmitted data bits, lack of this frequency indicating no transmitted bit.

The other frequency is merely used in conjunction with the first frequency and with another frequency to provide a safety feature to guard against loss of signal from the transmitter.

Preferably, the remote control system comprises synchronisation means operable to provide that respective ones of said data output channels always receive data on respective associated ones of said data input channels. In a preferred embodiment, said synchronisation means comprise in said control data transmitter pulse generating means for generating a synchronising pulse in a multiplexing cycle, said pulse generating means being coupled to said frequency generating means which is adapted to generate a characteristic frequency indicative of said synchronising pulse, and in said control data receiver said synchronisation means comprise an adaptation of said frequency decoding means whereby the latter is operable to recognise said characteristic frequency and apply a synchronising pulse to said demultiplexing means.

In order to provide the safety feature mentioned in the last-but-one paragraph, said frequency decoding means is operable to shut-down to safety said control data receiver in the event that none of the three frequencies to which said frequency decoding means is responsive, is received. A refinement of this safety feature is to provide delay means operable to ignore none-receipt of said three frequencies if said non-receipt does not persist longer than a predetermined period.

Preferably, the remote control system comprises parity check means whereby the parity of the data received by said control data receiver in a demultiplexing cycle can be checked against the parity of the data transmitted by said control data transmitter in a multiplexing cycle. The parity check means may comprise in said control data transmitter a parity bit generator to supply to an input line of said multiplexer a parity signal which is a logic high or low signal depending upon the parity of the transmitted data in a preceding multiplexing cycle, and in said control data receiver said parity check means comprises a parity detector operable to check whether or not the logic signal on that one of said data output lines which receives the transmitted parity signal is correct according to a parity check performed by said parity detector on the received data in a preceding demultiplexing cycle. The parity check means may be operable to shut-down to safety said control data receiver if the parity check reveals a parity error. A refinement of the parity check means is to provide delay means operable to ignore said parity error if said parity error does not persist beyond a predetermined period.

In a preferred embodiment said control data transmitter comprises a radio frequency transmitter coupled to said frequency generating means such that frequency generated by the latter is used as a modulating signal, and said control data receiver comprises a radio frequency receiver which is cooperable with said radio frequency transmitter and which is coupled to said frequency decoding means.

In order to avoid spurious noise giving rise to invalid control signals, the radio frequency receiver may comprise an output stage which does not respond to a received signal below a predetermined level.

Another safety feature for the radio frequency receiver is to connect it via a transformer to its receiving aerial, whereby d.c. voltage is applied to the receiver side of the transformer cannot be conducted to the aerial.

A feature leading to longer re-chargeable cell life in the transmitter unit, which is usually a hand-held unit, is for the control data transmitter to comprise an economiser circuit operable periodically to cut-off power to said radio frequency transmitter.

Yet a further safety feature is to provide the frequency decoding means with noisesuppression means which do not allow said frequency decoding means to output a signal below a predetermined level of received signal.

In a preferred embodiment, in said control data transmitter some of said plurality of data input lines are connected to an encoding means operable to put onto said some lines a binary coded word in dependence upon discrete positions of a multi-position switch coupled to said encoding means.

Another safety feature is to provide the control data receiver with inhibiting means to inhibit in said plurality of data output lines transitional effects at the beginning of each demultiplexing step.

For a better understanding of the invention and to show how it may be put into effect reference will now be made, by way of example, to the accompanying drawings, in which: Figure 1 shows symbolically an item of machinery and a remote controller therefor; Figure 2 is a block diagram of a channel encoding system data transmitter; Figure 3 is a block diagram of a receiver cooperable with the transmitter of Figure 2; Figure 4 is a detailed circuit diagram of part of the transmitter of Figure 2; Figure 5 shows further details of Figure 2; Figure 6 is a circuit diagram of a speed selector switch and binary encoder for use with the transmitter of Figure 2; Figure 7 shows further details of Figure 2; Figure 8 is a circuit diagram showing details of the radio receiver of Figure 3; Figure 9 shows details of the logic of Figure 3; and Figure 10 shows details of the demultiplexer of Figure 3.

It is to be noted that Figures 4, 5, 6, 7, 9 and 10 of the accompanying drawings show standard integrated circuits manufactured by RCA. In each case on the drawing the integrated circuit is shown with pin-numbers marked and where appropriate, input or output type designations marked also. The manufacturer's circuit type number is given in the description of the drawings in the following manner: i.e. a series of two letters and a number, such as CD4020. In each case this series is preceded by the letters IC to indicate that what is concerned is an integrated circuit. The manufacturer's designations and pin numbers are current at the time of drafting this description; i.e.

March 1978. These designations and pin numbers can be found in RCA's data books relating to their integrated circuits and dated before March 1978. One such book, which contains most of the integrated circuits contained in the present specification and drawings, is the RCA databook COS/MOS Digital Integrated Circuits dated 1975 and reference number SSD--203C.

Figure 1 shows symbolically a coal face coal-cutting machine 1 and a remote controller 2 therefor. A remote control system as will be described hereinafter is employed to transmit control data from the controller 2 to the machine 1. The latter could, of course, be any other type of machine operable by remote control.

Figure 2 shows in simplified block diagram form a channel encoding system data transmitter powered by rechargeable cells. A conventional crystal controlled oscillator 3 is frequency divided in a divider 4 before feeding into a binary counter 5.

The output from the binary counter 5 is fed in parallel to a 1 of 32 line multiplexer 6. 30 of these lines may be used for data transmission and the logic signals thereon are transmitted to a common data line 8 by multiplexing. Some of the 30 data input lines comprise push buttons 7 for applylng logical high signals to the multiplexer 6. The final two lines of the 32 are used for synchronisation and parity checking, as will be described in more detail hereinafter.

A second conventional crystal controlled oscillator 9 is frequency divided in a divider 10 before feeding into a Modulo N Divider 11. A binary coded number N is parallelly entered into the divider 11 and the resulting output frequency of the divider 11 equals the input frequency divided by N. The data multiplexer 6 previously mentioned is used to select one of three values for N which is entered into this divider 11. The highest value N1 represents a logic low level on the selected one of the 30 data input lines at a moment in time. The next value N2 represents a logic high level on the selected data input line at a moment in time, and the next value N3 represents a synchronisation level which occurs only once during each cycle executed by the multiplexer 6 through the 32 channels (including the parity and synch channels).These values N1, N2 and N3 can be selected at will in order to comply with the band width regulations pertaining to the communication system to reused, e.g. radio link or Post Office Transmission lines.

During operation therefore, with the system live but no data entered, the output from the divider 11 consists of a short burst of synchronisation frequency (actually from the previous multiplexing cycle) followed by 30 periods logic low frequency then one period of logic high for the parity check condition, then returning to the next synchronising signal. If, however, data is present on any of the 30 data input channels, then during the sequential stepping the output from the Modulo N divider 11 will jump up to a logic high level indicating frequency when this particular input is selected by the multiplexer 6. It is possible to transmit on one, some or all of the 30 data input channels simultaneously.

In the described embodiment five data input channels are used to provide binary coded information for eleven forward and eleven reverse speeds of the drive to a machine.

The frequencies from the divider 11 may be transmitted along a single channel directly down telegraph lines or may be applied to a radio link of AM or FM type. In the present system, which was designed for use down coal mines, a radio transmitter 12 employing a carrier frequency of approximately 150 MHz on a single output channel is used. This is frequency modulated by the three data frequencies emanating from the divider 11, which range from 2 to 10 KHz.

This system would not be suitable for use above ground in the United Kingdom due to G.P.O. licencing regulations. It could, however, be easily substituted by a narrow band FM system -U.H.F., or a narrow band A.M. system in the V.H.F. range.

Figure 3 shows in block diagram form a data receiver for use with the data transmitter of Figure 2. Conventional techniques are used in the reeceiver in order to extract the three data frequencies from the F.M. Radio transmission. The output from a crystal controlled oscillator 13 15 frequency divided in a divider 14 to produce a stepping rate at the same speed as that occurring in the transmitter system.

Clock pulses at this frequency are fed into a binary counter 15 and the output from this counter 15 is de-coded in a 1 of 32 line demultiplexer 16 having 30 data output channels. Tone signals received by logic circuitry 17 from a radio frequency receiving unit 18 of the receiver are identified by means of three tuned circuits or phaselocked loops which constitute part of the logic circuitry 17. Each of the tuned circuits gives nse to a logic high level only when identifying the frequency to which it has been set. The synchronisation frequency when de-coded is used to re-set the binary counter 15 so that it will then run exactly in synchronism with the signal generated in the transmitter over the next multiplexing/demultiplexing cycle.The 1 of 32 line demultiplexer 16 is therefore seen to be stepping through 32 channels in synchronism with (though not necessarily exactly simultaneously with) the 32 channel data input multiplexer 6 at the transmitter.

Logic high and low level indicating frequencies from the data transmitter are identified by the tuned circuits and at least one of these is used through more logic gating in order to generate high or low levels which can be applied to output drive stages.

At the end of each demultiplexing cycle a parity check is carried out.

Figure 4 shows in detail part of Figure 2, including the counter 5 and part of the multiplexer 6. It also shows other circuitry details which will become apparent from the following description.

The oscillator 3 (see Figure 2) feeds pulses at 32.768 kHz to the counter 5 (IC CD4020) which, in addition to counting, performs the function of the frequency divider 4 of Figure 2. The counter 5 is a binary counter with fourteen stages. Of the fourteen available binary outputs, only those from the stages Q7 to Q12 are used. In this way both frequency division and counting are achieved. The output from the stage Q7 is connected to the clock input pin 3 of a D-type flip-flop 19 (IC CD4013), and to the clock input pin 3 of a JK flip-flop 20 (IC CD4027) via an inverter 21.

The outputs from the stages QS to QIl of the counter 5 are connected to the control inputs A0 to A3 of a multiplexer 22 (IC CD4067BE) to provide binary coded input control words to select sequentially the sixteen data input channels DO to D15 thereof for feeding through to the data output pin I of the multiplexer 22. Data inputs D9 to D13 are used for speed control, as will be described in more detail hereinafter, and the inputs DO to D8 are spare inputs, held at logic low by 100KQ resistors.

The multiplexer 22 provides part of the multiplexer 6 of Figure 2. The rate of stepping of the multiplexer 22 is 256 Hz, owing to the frequency division carried out by the counter 5.

The output of stage Q12 of the counter 5 is connected to pin 15 of the multiplexer 22 by an inverter 23. As long as pin 15 on multiplexer 20 is logically low (when pin I on counter 5 is high), the multiplexer 22 will be enabled and the four output stages Q8 to Q 1 of the counter 5 will cause the multiplexer 22 to multiplex between its sixteen inputs DO to D15.

In order to double to thirty-two the number of input lines between which multiplexing takes place, a data output pin from another multiplexer (shown in Figure 5) which provides the remainder of multiplexer 6 in Figure 2, is connected together with the data output pin 1 of multiplexer 22 to respective inputs of a NOR gate 24. As long as the multiplexer 22 is enabled by a logical low on its input pin 15, the other multiplexer (not shown in Figure 4) is disabled.

When a logical low appears on output stage Q12 of counter 5, the multiplexer 22 is disabled and the other multiplexer is enabled to be controlled by the output stages Q8 to Ql l of the counter 5. The two multiplexers together provide multiplexing between thirty-two input channels, including 30 data input channels.

It is to be appreciated that in a multiplexing cycle first of all the sixteen input lines of the multiplexer which is not shown in Figure 4 are multiplexed, then the sixteen input lines of the multiplexer 22. The 31st line provides a parity check and the 32nd a synchronisation or synch pulse before the start of the next multiplexing cycle. Parity check and synch pulse generation are described in more detail hereinafter.

The output of the NOR gate 24 is connected to the data input pin 5 of the Dtype flip-flop 19, which is clocked by the output stage Q7 of the counter 5. The logic level appearing at the data input pin 5 is transferred to the Q output of the flip-flop 19 at positive-going transistions of the clock pulses; the inverse appears at Q. The flipflop 19 is clocked at twice the stepping frequency of the multiplexers. Thus the output ot the flip-flop 19 can be ensured to represent only valid data and not any invalid data which may occur whilst switching from one bit to another.

The Q and Q outputs of the flip-flop 19 are connected to the inputs of respective NOR gates 25 and 26. These are enabled whenever an AND gate 27 has a logical low output. In fact the AND gate 27 is so coupled to the output stages Q8 to Q12 of the counter 5, that the AND gate 27 issues a logical high only once in a complete multiplexing cycle, when the outputs Q8 to Q12 of the counter 5 are all at logic high, corresponding to the final channel of the 32 input channels of the multiplexer 6 in Figure 2. In addition to disabling the NOR gates 25 and 26, this logical high is employed as a synchronising pulse and set the flip-flop 19 such that its Q output is initially logic high.

Figure 4 therefore has three output lines.

The output line from the NOR gate 25 is at a logic high when a logic low is present at the selected one of the data inputs to the multiplexers, the output line from the NOR gate 26 is at a logic high when a logic high is present at the selected one of the data inputs to the multiplexers, and the output line from the AND gate 27 is at a logical high only once in a multiplexing cycle.

These three output lines together provide the common data line in Figure 8 to define N.

The foregoing describes how three signals are generated to signify Nl, N2 and N3 as described with respect to Figure 2. In each multiplexing cycle thirty-one data input channels (including the parity check) are scanned sequentially, and the logic level at the data input which is selected at a moment in time is indicated by the NOR gates 25 and 26. Once in every multiplexing cycle, when the signal from all the output stages Q8 to Q12 of the counter 5 is high, as synchronisingpulse is issued by the AND gate 27.

Parity determination is provided by the JK flip-flop 20 which is reset in dependence upon the AND gate 27. The JK flip-flop 20 operates such that if J and K inputs are both high, then operation of the clock input at pin 3 will cause a change of state. The output Q will go high if it was previously low and vice versa. Before the beginning of each multiplexing cycle the flip-flop 20 is reset at pin 4 by the AND gate 27 such that output Q is low. Each time data is transmitted through the flip-flop 19 the clock of the flipflop 20 is operated. If at that time pin 1 of flip-flop 19 is high, then the Q output of flipflop 20 will change state. An even number of logic high levels in the transmitted signal will leave pin 1 of flip-flop 20 low at the end of the multiplexing cycle. This parity signal is multiplexed in the multiplexer 22 as are all the other data signals.If, however, an odd number of logic high levels are transmitted during a cycle, then pin 1 of flip-flop 20 will be high at the end of the multiplexing cycle and a high parity bit will be transmitted from the relevant input line D14 of the multiplexer 22. Overall parity is therefore even, flip-flop 20 providing the necessary bit in order to make up an even number.

Figure 5 shows the other multiplexer 29 (IC CD4067BE) which, in conjunction with the multiplexer 22 in Figure 4, makes up the whole multiplexer block 6 in Figure 2.

Sixteen data input stages are multiplexed to a data output Q connected to the lower input of NOR gate 24 in Figure 4. The control of the multiplexing is carried out on inputs A0 to A3 in dependence upon the counter 5 in Figure 4 when the multiplexer 22 is disabled and the multiplexer 29 enabled via the EN inputs. The sixteen data inputs of multiplexer 29 are normally held at logic low by 100 K resistors.

The sixteen data input lines to the multiplexer 29 are connected to sixteen ush- buttons on a keyboard 29a of a hand-held control unit containing all the data transmitter circuitry. These push-buttons can be employed to provide on/off signals for various electrical drives for example.

Figure 6 shows a speed controller for supplying to data input channels D9 to D13 of the multiplexer 22 in Figure 4 control data in the form of a binary encoded work.

A twenty-three position rotary switch 30 is mounted in the hand-held control unit. The centre position of the switch is used to represent zero speed, and eleven forward and eleven reverse speeds are provided on opposite sides of the zero position. Those fixed terminals of the switch which are not contacted by a wiper 31 are normally held at logic low by resistors of 100 Ks2 each connected to earth. That fixed terminal which is contacted by the wiper 31 is put to logic high, the wiper 31 being connected to a 12v d.c. rechargeable cell supply for the data transmission circuitry.

The inputs of three priority encoders 32, 33 and 34 (ICs CD4532BE) are connected to respective ones of the twenty-three fixed terminals of the switch 30. A binary representation of the highest priority input appears on the three output pins QO, Ql and Q2 of each encoder. These outputs are gated together in three NOR gates 35, 36 and 37 and are used to provide a five-bit binary coded number for the input channels D9 to D13 of the multiplexer 22 in Figure 4.

This binary coded number simply represents the twenty-three rotary switch positions by the numbers one to twentythree. Binary number twelve therefore represents the zero speed setting. By using the priority encoders 32, 33 and 34, it is ensured that if the switch 30 is adjusted during a transmission, it is not possible to select two speeds simultaneously with the wiper 31 half-way between two adjacent contacts, thereby transmitting an invalid code.

Figure 7 shows details of the divider 11 of Figure 2 and the connections thereto and therefrom. The divider 11 is in fact an IC CD40103BE which is an eight-stage presettable synchronised down counter. It is clocked at pin 1 by the conventional crystal controlled oscillator 9 (not shown in Figure 7) oscillating at I MHz. There is no frequency divider 10 in this embodiment.

The values Nl, N2 and N3 which define logic low, high and synch respectively are loaded into the inputs W to P7 of divider 11 in binary coded form. These inputs are connected to a set of terminals 38. Three further sets of terminals 39, 40 and 41 are connected to respective ones of the three output lines of Figure 4. The terminals 39 are connected to the output of the AND gate 27 in Figure 4 and thus go logic high when a synch pulse is transmitted.

Terminals 40 are connected to the output of the NOR gate 26 in Figure 4 and thus go high when a logic high level is transmitted; and terminals 41 are connected to the output of the NOR gate 25 in Figure 4 and thus go high when a logic low level is transmitted. The three sets of terminals 39, 40 and 41 are connected to the terminals 38 by diodes in such a way that each set of terminals 39, 40 and 41, when put to logic high, supplies to the terminals 38 a characteristic binary coded work consisting of logic highs where the terminals are interconnected by diodes, and logic lows where no interconnection exists. The divider 11 thus outputs a frequency which is equal to 1 MHz divided by the particular binary coded number loaded at its input PO to P7, provided by a respective one of the sets of terminals 39, 40 and 41.The divider 11 thus outputs three different frequencies to signify the three different facts of logic high transmission, logic low transmission, and synch pulse transmission. It is to be noted that the control inputs and the carry out of divider 11 are active low. It is therefore necessary that the complement of the binary divisor required be loaded into divider 11.

For the sake of clarity in Figure 7, the particular diode interconnections between the sets of terminals 38 and 39, 40, 41 are not shown. However, they are so selected in this embodiment that the three output frequencies from the divider 11 are approximately twice 4.7 kHz, 7.3 kHz and 9 kHz.

The output signals from the divider 11 are only T psec wide. These are fed to a JK flipflop 42 (IC CD4027) which halves the output frequency of the divider 11 and also provides an equal mark-to-space ratio thereby eliminating risk of even harmonic introduction in the transmitted signal.

The output signal of the flip-flop 42 is fed as modulating frequency to the FM modulated radio frequency transmitter 12 shown in Figure 2. Any suitable conventional transmitter of this type can be employed as the transmitter 12. Since the design of such a transmitter will be apparent to a man skilled in the art, no detailed description of this item is required here. We employ a transmitter generating a 150 Mhz carrier wave, although frequencies from 50 to 800 MHz could be considered.

Figure 7 also shows an economiser circuit comprising a monostable flip-flop 43 (IC CD4098) connected via an inverter 44 and a light emitting diode 45 to control a transistor 46 having its emitter collector path connected directly in an electrical path via which the RF transmitter 12 (see Figure 2) is supplied with electrical power. The flip-flop 43 is adjusted to have a pulse width of just less than 1 second. It controls the transistor 46 to interrupt the supply to the transmitter and is triggered by a synch pulse on the set of terminals 39. A negative going signal at pin 5 of flip-flop 43 causes its pin 7 to go low, enabling the output of the inverter 44 to go high thereby turning-off the transistor 46 for the duration of the output pulse. When the light emitting diode 45 flickers, the operator knows that the circuit is operational as the transistor 46 is turned off and on.

The use of the economiser enables longer rechargeable cell life between charges to be achieved. It is to be realised, however, that the economiser can only be used in systems requiring a relatively long response time, owing to the fact that the RF transmitter is out of operation for the majority of the time, and is operative for only a short proportion of each second. If a short response time to changes in input data is required, the economiser can be omitted.

Figure 8 shows inter alia the interconnection between the aerial of the RF receiver 18 shown in Figure 3, and the receiver itself. The interconnection is via a transformer 47 having a winding connected to the aerial and a further winding connected to the receiver 18. The purpose of this transformer is to allow signals received at the aerial to be transmitted to the receiver 18, but to prevent voltage being applied from the receiver to the aerial in the event of a fault in the receiver causing its supply voltage to be applied to its input terminals. This makes the receiver intrinsically safe.

The circuitry of the receiver itself is conventional except for its output stage which is also shown in Figure 8 and described hereinafter. In our actual embodiment the receiver was, in fact, built around a standard IC CA 3089 F.M. radio receiver chip. The output of this chip is fed to the inverting input of an operational amplifier 48, the non-inverting input of which is coupled to a potential divider 49.

The output of the operational amplifier 48 provides the output signal of the RF receiver 18 in Figure 2.

The comparator action of the operational amplifier 48 in conjunction with the potential divider 49 provides that received RF signals below a predetermined level set by the potential divider 49 result in no output signal from the operational amplifier 48. In this way the receiver is protected against responding to input signals produced merely by random or spurious noise levels.

Figure 9 shows details of the logic circuitry 17 of Figure 3. An audio frequency signal trom the receiver 18 is fed via a capacitor 50 to two Zener diodes 51 which act as amplitude limiters on the incoming signal. The incoming signal is then fed through three resistors 52, 53 and 54 to three tuned LC circuits 55, 56 and 57 respectively, which are tuned to resonate at respective ones of the three frequencies transmitted by the transmitter system. The circuit 55 is tuned to resonate at the frequency of 9kHz, indicative of a synch pulse; the circuit 56 is tuned to resonate at the frequency 7.3 kHz indicative of a logic high being transmitted; and the circuit 57 is tuned to resonate at the frequency 4.7 kHz indicative of a logic low being transmitted.

When any one of the tuned circuits 55, 56 and 57 resonates in response to an incoming frequency, and the amplitude of the resonant frequency is sufficient to cause the relevant one of diodes 58, 59 and 60 to conduct, a rectified voltage is applied to the sequentially connected circuitry.

Capacitors 61, 62 and 63 are decoupling capacitors.

The diode 58, when conductive, applies a unidirectional voltage across a resistor 64 and to the non-inverting input of an operational amplifier 65. This acts as a comparator to compare the undirectional voltage from the diode 58 with reference voltage applied to the inverting input of the amplifier 65 from the potential divider 66.

When the unidirectional voltage from the diode 58 exceeds the reference value, a logic high signal is emitted from the amplifier 65, indicating transmission of a synch pulse. The comparator 65 sets a threshold to prevent noise signals producing a spurious logic high from the amplifier 65.

The diodes 59 and 60 operate in a similar manner. When the tuned circuit 56 resonates and diode 59 conducts, a unidirectional voltage is applied to the inverting input of an operational amplifier 67, which emits a logic low level when the signal at its inverting input exceeds that at its non-inverting input from a potential divider. Thus a logic low level at the output of amplifier 67 signifies a transmitted logic high level.

When the tuned circuit 57 resonates and diode 60 conducts, a unidirectional voltage is applied to the inverting input of an operational amplifier 68, which emits a logic low level when the signal at its inverting input exceeds that at its non-inverting input from a further potential divider. Thus a logic low level at the output of amplifier 68 signifies a transmitted logic low level.

The output of amplifier 65 is coupled to the reset input of binary counter 15 (see Figures 3 and 10) to reset it at each synch pulse, thereby to synchronise the demultiplexing of the demultiplexer 16 (see Figure 3) in the receiver with the multiplexing of the multiplexer 6 (see Figure 2) in the transmitter. The output of amplifier 65 is also connected to the input of a JK flipflop 84 to be described with reference to Figure 10, and also to the input pin 12 of a monostable flip-flop 69 (IC CD4528) which outputs a logic high response to a synch pulse, this logic high persisting for a period dependent upon timing elements coupled to the flip-flop 69 as shown.

The outputs of amplifiers 67 and 68 are connected to the data inputs of two halves 70 and 71 respectively of a dual D-type flipflop (IC CD4013). The clocking inputs of the flip-flop are connected to an output stage of the counter 15 (see Figures 3 and 10) so that on the Q outputs of the flip-flop will appear, when the tlip-flop receives a clock pulse, the inverse of the data signals thereto. Thus, on clocking, the ftip- flop half 70 will output a logic high signal to signify a transmitted logic high, and the flipflop half 71 will output a logic low signal to signify a transmitted logic high, and vice versa.

A NOR gate 72 has inputs connected to the Q outputs of the three flip-flops 69, 70 and 71. The NOR gate 72 emits a logic high only when all its inputs are logic low, i.e when no information at all is received from the transmitter. The monostable 69 is so timed as to disable the NOR gate 72 for a period between the synch pulse from amplifier 65 ending, and the next logic high appearing from flip-flop 70 or 71. The output of the NOR gate 72 is connected to a fault output channel shown in Figure 10.

In addition to being connected to the NOR.

gate 72 the Q output stage of the flip-floP 70 is coupled to the multiplexer 16, as will be described in more detail with respect to Figure 10.

Figure 10 shows details of the counter 15 and demultiplexer 16 of Figure 3.

The oscillator 13 in Figure 3 (not shown in Figure 10) is a conventional crystal controlled oscillator emitting output pulses at the rate of 32.768 KHz. It is identical to the oscillator 3 of Figure 2. The oscillator 13 outputs pulses to a 14-stage binary counter 15 (IC CD4020) which performs the functions not only of the counter 15 of Figure 3, but of the frequency divider 14 also. This is achieved by employing only the six output stages Q7 to Qiof the counter 15. The output stage Q7 is employed to clock the flip-flops 70 and 71 of Figure 9, and the output stages Q8 to Q12 are employed in the demultiplexing process at a rate of 256 Hz as will be described hereinafter. The reset input R of the counter 15 is operated by synch pulses received from the operational amplifier 65 in Figure 9.This ensures that the counter 15 is synchronised with the counter 5 in the transmitter before the beginning of each demultiplexing cycle.

The demutiplexer 16 of Figure 3 comprises inter alia in Figure 10 a B.C.D. to decimal decoder 73 (IC CD4028) and four addressable latches 74 to 77 (IC CD4099).

The thirty data output lines are provided by pins 1,9 to 11, 13 to 15 on latch 74, pins 1 and 9 to 15 on latches 75 and 76, and pins 9 to 15 on latch 77. The parity bit is carried by pin 1 of latch 77. Only the first and thirtieth output lines are shown for the sake of clanty. The data inputs 3 of the latches 74 to 77 are connected in common to the output of the flip-flop 70 in Figure 9.

The binary counter 15 addresses the latches 74 to 77 via its output stages Q8, Q9 and Q10. The most significant bits of the count performed by the counter 15 are supplied via its output stages Qll and Q12 to the B.C.D. to decimal decoder 73. The decimal output lines 0 to 3 of the decoder 73 are used to enable the latches 74 to 77 in turn via NAND gates 78 to 81 respectively, which enable the respective latches by logic low signals.

Demultiplexing between the thirty-one output pins (including the parity pin) of the latches 74 to 77 is carried out by the counter 15 in conjunction with the B.C.D. to decimal decoder 73. The data line from the output of the flip-flop 70 in Figure 8 is coupled to the thirty-one output pins in turn of the latches 74 to 77. When a logic high appears on an addressed one of these thirtyone pins, flip-flop 70 is supplying a logic high signal signifying a logic high on the corresponding input line at the transmitter.

When a logic low appears on an addressed one of these thirty-one pins, flip-flop 70 is supplying a logic low signal signifying a logic low on the corresponding input line at the transmitter.

In the present system, in correspondence with the transmitter arrangement, five of the thirty-one output pins will carry a binary coded word to define a selected one of the twenty-three speed settings of the speed controller 30 in Figure 6, nine of the output pins will be spare to correspond with the nine spare input lines to the multiplexer 22 shown in Figure 4, and sixteen will carry logic high or low signals in dependence upon the state of the sixteen push buttons on the keyboard shown in Figure 5. These sixteen output lines can be employed to supply control pulses (amplified if required) for solenoid valves, small motors etc, depending upon what the controlled device is. The nine spare lines could be employed as desired, depending upon the application.

An interesting feature of Figure 10 is an inverter 81 a connected between the Q7 output stage of the counter 15 and the input of the B.C.D. to decimal decoder 73. This is employed to inhibit all of the latches 74 to 77 during the first half of each bit period thereby to disregard any transitional effects when switching from logic high to logic low or vice versa.

It is to be appreciated that in Figure 10, although the counter 15 is synchronised with the counter 5 of the transmitter by synch pulses from the amplifier 65, the operations of the counter 15 do not occur strictly simultaneously with the operations of the counter 5. This is because the tuned circuit 55 does not respond immediately to an incoming synch frequency. The tuned circuit 55 has to receive some five to ten cycles of the incoming synch frequency before it recognises that it is, in fact, the synch frequency. The counter 15 is therefore not reset until after these cycles have been received. This does not affect the operation of the circuitry of Figure 9, and obviously a similar delay will occur in the tuned circuits 56 and 57.It is to be understood, therefore, that in the present specification and claims the term "synchronism" when used in relation to the mutual timing of operations in the transmitter and receiver systems with respect to one another, does not imply precise simultaneity of these operations. It will be appreciated, of course, that the higher are the three frequencies used between the transmitter and receiver systems, the shorter time it will take for the tuned circuitry to recognise their respective frequencies, and the nearer to simultaneous synchronous operation will be achieved. It must be realised, however, that certain frequencies may not be employable (above ground at least) in view of local laws relating to R.F. broadcasting. The present system, which employs frequencies in the range 2 to 10 kHz, is perfectly suitable for mining applications in the U.K. The frequency levels in this range allow operation without any appreciable delay in operation of the receiver caused by the inherent delay of the tuned circuits 55, 56 and 57.

The circuitry illustrated in Figure 10 comprises a fault output channel 82 which can be employed to signal a fault on the system. If a fault occurs a fault signal is fed from the output channel 82 to an input of a NOR gate 83 which disables all the NAND gates 78 to 81 and resets the latches 74 to 77 via an inverter 83a. Thus in the event of a fault, none of the latches 74 to 77 can be enables and all the output channels are shut down. This is a valuable failure-to-safety feature ensuring that no invalid codes are put out by the latches 74 to 77 in the event of fault.

One of the ways in which a fault can be signalled on the fault output channel 82 is in dependence upon the parity check facility.

The parity of the received data is checked by a JK flip-flop 84 ( IC CD4027) which is reset by the synch pulse from the amplifier 65 (see Figure 9) and which receives at its clock input CK data from the flip-flop 70 (also see Figure 9). As long as its J and K inputs are high, successive operations of the clock input cause the outputs Q and Q to change state. An even number of data bits in a demultiplexing cycle will result in the Q output being high and the Q output being low. An odd number of bits in the cycle will cause the reverse situation. The J and K inputs of the flip-flop 84 will normally be kept high in dependence upon an inverter 85 supplied by a NOR gate 86.The latter normally receives logic low signals from the NOR gate 81 (when latch 77 receiving the parity bit is enabled) and from an inverter 87 controlled by a further NOR gate 88 which receives via inverters 89, 90 and 91 inverted clocking signals from the output stages Q8, Q9 and Q10 of the counter 15.

The circuitry comprising components 87 to 91 disables the'NOR gates 86 and 96 just before the parity bit. The J and K inputs of the flipflop 84 go low, and so the parity bit does not affect the state of the flip-flop 84.

If an odd number of data bits are transmitted for example, parity is made up by inclusion in the data of a bit generated by the JK flip-flop 20 in Figure 4. In Figure 10, therefore, pin 1 of latch 77 carries a logic high. The upper input of a NOR gate 92 thus carries a logic high signal, and the upper input of a NOR gate 93 carries a logic low signal via an inverter 94. The lower input of the NOR gate 92 then carries a logic low signal from the Q output of flip-flop 84, and the lower input of NOR gate 93 carries a logic high signal from the Q output of flipflop 84. Therefore the outputs of both NOR gates 92 and 93 carry logic low signals.

rhis is the case when the parity bit carried by pin 1 of latch 77, indicating an odd number of transmitted bits, agrees with the state of the flip-flop 84. A NOR gate 95 receives logic low signals from the NOR gates 92 and 93 and disables a further NOR gate 96.

When an even number of bits is transmitted and there is no parity fault, a logic low is present on pin 1 of latch 77 and logic low and high are present on outputs Q and Q respectively of flip-flop 84. The logic levels on the inputs of NOR gates 92 and 93 are reversed, and they again carry logic lows on their outputs. NOR gate 95 again supplies logic high which again disables the further NOR gate 96.

If a parity fault occurs and the flip-flop 84 responds, say, to an even number of bits transmitted at the same time that pin 1 of latch 77 carries a signal to signify an odd number of transmitted its, NOR gate 92 will carry high logic levels on its two inputs and NOR gate 93 will carry low levels. NOR gate 93 will thus output logic high to disable NOR gate 95 and enable NOR gate 96. On the other hand, if a fault occurs such that the flip-flop 84 responds to an odd number of bits transmitted at the same time that pin 1 of latch 77 carries a logic low to signify an even number of transmitted bits, NOR gate 93 will carry logic high levels on its two inputs and NOR gate 92 will carry logic low levels. NOR gate 92 will thus output logic high to disable NOR gate 95 and enable NOR gate 96.

In both these cases, NOR gate 96 will output a logic high level because it already normally receives logic low signals at its upper two inputs. The upper input receives a logic low signal from NAND gate 81 which is simultaneously enabling latch 77, and the middle input receives a logic low from the inverter 87. At this point in time, therefore, the NOR gate 96 emits a logic high to the upper two inputs of a NOR gate 97, the lower input of which normally receives a logic low from NOR gate 72 Figure 8). This triggers a delay circuit 9 , which is a monostable flipflop (IC CD4528) and is so set as not to respond to the parity error for one demultiplexing cycle. If, however, the parity error persists in the succeeding demultiplexing cycle, the flip-flop 98 enables a NOR gate 99 to send a clock pulse to a JK flip-flop 100.The flip-flop 100 thus emits a logic high on its Q output to signal a fault and to disable the latches 74 to 77 via the NOR gate 83.

Normal operation of the latches and cancellation of the fault signalling can only be restored by grounding a reset line 101, which operates the reset input of the JK flip-flop 100 via an inverter 102.

In our embodiment one output channel pin 13 of latch 74 of the thirty data output channels is employed as a main motor control stage. This output channel pin 13 of latch 74 is connected with the fault channel 82 to two inputs of a NOR gate 103. In this way the fault output signal is employed to stop the main motor in the same way that the motor stop signal, when transmitted, would operate.

Another way to operate the fault output channel 82 is if the NOR gate 72 (see Figure 9) applies logic high to the lower input of NOR gate 97. This signifies that no signal is received from any of flip-flops 69, 70 and 71.

This could mean, for example, that the distance between the transmitter and receiver units is too great for the system to operate properly. In this case the delay circuit flip-flop 98 is again brought into operation, which causes the fault output channel to operate if the fault is not corrected within the next demultiplexing cycle. It must be ensured that the delay circuit flip-flop 98 is so timed that it does not respond spuriously to the effect of the economiser circuit in Figure 4.

It will be appreciated that the illustrated and described remote control system comprises many features providing safety in operation. This is particularly important in operating heavy machinery, such as in the mining industry.

Some salient features of the system are as follows: the system combines tonal and digital techniques in order to achieve a high degree of security and reliability; a narrow band F.M. radio transmission system is used which comprises several features providing a high degree of rejection against spurious noise.

The parity check circuitry and the delayed fault output on the receiver provide that one-time interference pulses, even if occurring at the appropriate frequency, are ignored. On the other hand, if interfering tones at the correct frequency are received for more than one scan, then the parity check circuitry will trip the system out to safety.

One of the data channels can be used to transmit a permanent "transmitter alive" signal. If the received signal does not contain this particular piece of data due to loss of signal, batteries failing or fading, then again the whole receiver circuit trips out to safety.

The delay in the operation of the fault output channel can be increased to provide a stay-as-you-were facility enabling the receiver to continue operating in the event of brief losses of signal due, for example, to the physical position of the operator changing or due to momentary fading. This stay-as-you-were facility could be applied to individual channels at the discretion of the user and enables, for example, main motors to continue running during loss of signal whilst haulage systems are caused to stop until the signals are restored. If the signal is lost for more than say two seconds, then the main motor would automatically stop also.

A further feature which could be added to increase the security of the system would be for some of the spare channels to be used to transmit between the transmitter and the receiver a characteristic binary coded word.

The receiver would be set-up to identify this code. Therefore a transmitter on a similar frequency, but not transmitting the characteristic word, would be unable to interfere with the receiver s function.

The illustrated and described system can easily be modified for use over closed wire links or for leaky inductance links.

In general it can be stated that the system has been designed specifically to overcome some of the problems encountered when transmitting data over radio links or down long lines in communication systems for the control of large machines. Great emphasis has been placed on the security of the communicating link i.e. it cannot easily be simulated by spurious noises and Test Engineer's transmissions. In addition to this great care has been taken to ensure that failure to safety occurs in the event of any mal-function between the transmitter and the receiver.

The prototype system caters for data transmission over thirty channels, however, it is easily expanded up to 100 channels.

WHAT WE CLAIM IS: 1. A remote control system comprising a control data transmitter and a control data receiver, said control data transmitter comprising: time multiplexing means having a plurality of data input lines and data output line, said time multiplexing means being operable to multiplex in time between said data input lines onto said data output line; and frequency generating means for generating a frequency in response to a predetermined logic level signal on said data output line; said control data receiver comprising: frequency decoding means for converting said frequency generated by said frequency generating means into a logic level signal; and time demultiplexing means having a data input line connected to said frequency decoding means, and a plurality of data output lines for providing a plurality of control channels, said demultiplexing means being operable to multiplex in time from said data input line onto said data output lines; the system comprising at least one safety function means operable to shut-down to safety the control data receiver in the event of detection of a faulty operating condition.

2. A remote control system according to claim 1, wherein said frequency generating means is adapted to generate two frequencies in response to logic high and low respectively on said data output line, said frequency decoding means being

**WARNING** end of DESC field may overlap start of CLMS **.

Claims (23)

**WARNING** start of CLMS field may overlap end of DESC **. channel 82 is if the NOR gate 72 (see Figure 9) applies logic high to the lower input of NOR gate 97. This signifies that no signal is received from any of flip-flops 69, 70 and 71. This could mean, for example, that the distance between the transmitter and receiver units is too great for the system to operate properly. In this case the delay circuit flip-flop 98 is again brought into operation, which causes the fault output channel to operate if the fault is not corrected within the next demultiplexing cycle. It must be ensured that the delay circuit flip-flop 98 is so timed that it does not respond spuriously to the effect of the economiser circuit in Figure 4. It will be appreciated that the illustrated and described remote control system comprises many features providing safety in operation. This is particularly important in operating heavy machinery, such as in the mining industry. Some salient features of the system are as follows: the system combines tonal and digital techniques in order to achieve a high degree of security and reliability; a narrow band F.M. radio transmission system is used which comprises several features providing a high degree of rejection against spurious noise. The parity check circuitry and the delayed fault output on the receiver provide that one-time interference pulses, even if occurring at the appropriate frequency, are ignored. On the other hand, if interfering tones at the correct frequency are received for more than one scan, then the parity check circuitry will trip the system out to safety. One of the data channels can be used to transmit a permanent "transmitter alive" signal. If the received signal does not contain this particular piece of data due to loss of signal, batteries failing or fading, then again the whole receiver circuit trips out to safety. The delay in the operation of the fault output channel can be increased to provide a stay-as-you-were facility enabling the receiver to continue operating in the event of brief losses of signal due, for example, to the physical position of the operator changing or due to momentary fading. This stay-as-you-were facility could be applied to individual channels at the discretion of the user and enables, for example, main motors to continue running during loss of signal whilst haulage systems are caused to stop until the signals are restored. If the signal is lost for more than say two seconds, then the main motor would automatically stop also. A further feature which could be added to increase the security of the system would be for some of the spare channels to be used to transmit between the transmitter and the receiver a characteristic binary coded word. The receiver would be set-up to identify this code. Therefore a transmitter on a similar frequency, but not transmitting the characteristic word, would be unable to interfere with the receiver s function. The illustrated and described system can easily be modified for use over closed wire links or for leaky inductance links. In general it can be stated that the system has been designed specifically to overcome some of the problems encountered when transmitting data over radio links or down long lines in communication systems for the control of large machines. Great emphasis has been placed on the security of the communicating link i.e. it cannot easily be simulated by spurious noises and Test Engineer's transmissions. In addition to this great care has been taken to ensure that failure to safety occurs in the event of any mal-function between the transmitter and the receiver. The prototype system caters for data transmission over thirty channels, however, it is easily expanded up to 100 channels. WHAT WE CLAIM IS:

1. A remote control system comprising a control data transmitter and a control data receiver, said control data transmitter comprising: time multiplexing means having a plurality of data input lines and data output line, said time multiplexing means being operable to multiplex in time between said data input lines onto said data output line; and frequency generating means for generating a frequency in response to a predetermined logic level signal on said data output line; said control data receiver comprising: frequency decoding means for converting said frequency generated by said frequency generating means into a logic level signal; and time demultiplexing means having a data input line connected to said frequency decoding means, and a plurality of data output lines for providing a plurality of control channels, said demultiplexing means being operable to multiplex in time from said data input line onto said data output lines; the system comprising at least one safety function means operable to shut-down to safety the control data receiver in the event of detection of a faulty operating condition.

2. A remote control system according to claim 1, wherein said frequency generating means is adapted to generate two frequencies in response to logic high and low respectively on said data output line, said frequency decoding means being

operable to recognise both said two frequencies.

3. A remote control system according to claim 1 or 2, and comprising synchronisation means operable to provide that respective ones of said data output channels always receive data on respective associated ones of said data input channels.

4. A remote control system according to claim 3, wherein said synchronisation means comprise in said control data transmitter pulse generating means for generating a synchronising pulse in a multiplexing cycle, said pulse generating means being coupled to said frequency generating means which is adapted to generate a characteristic frequency indicative of said synchronising pulse, and in said control data receiver said synchronisation means comprise an adaptation of said frequency decoding means whereby the latter is operable to recognise said characteristic frequency and apply a synchronising pulse to said demultiplexer.

5. A remote control system according to claims 2, 3 and 4 combined, wherein said frequency decoding means is operable to shut-down to safety said control data receiver in the event that none of the three frequencies, to which said frequency decoding means is responsive, is received.

6. A remote control system according to claim 5, and comprising delay means operable to ignore none-receipt of said three frequencies if said none-receipt does not persist longer than a predetermined period.

7. A remote control system according to any one of the preceding claims, and comprising parity check means whereby the parity of the data received by said control data receiver in a demultiplexing cycle can be checked against the parity of the data transmitted by said control data transmitter in a multiplexing cycle.

8. A remote control system according to claim 7, wherein said parity check means comprises in said control data transmitter a parity bit generator to supply to an input line of said multiplexer a parity signal which is a logic high or low signal depending upon the parity of the transmitted data in a preceding multiplexing cycle, and in said control data receiver said parity check means comprises a parity detector operable to check whether or not the logic signal on that one of said data output lines which receives the transmitted parity signal is correct according to a parity check performed by said parity detector on the received data in a preceding demultiplexing cycle.

9. A remote control system according to claim 7 or 8, wherein said parity check means is operable to shut-down to safety said control data receiver if the parity check reveals a parity error.

10. A remote control system according to claim 9, wherein said control data receiver comprises delay means operable to ignore said parity error if said parity error does not persist beyond a predetermined period.

11. A remote control system according to any one of the preceding claims, wherein said control data transmitter comprises a radio frequency transmitter coupled to said frequency generating means such that frequency generated by the latter is used as a modulating signal, and said control data receiver comprises a radio frequency receiver which is cooperable with said radio frequency transmitter and which is coupled to said frequency decoding means.

12. A remote control system according to claim 11, wherein said radio frequency receiver comprises an output stage which does not respond to a received signal below a predetermined level.

13. A remote control system according to claim 11 or 12, wherein said radio frequency receiver is connected via a transformer to its receiving aerial, whereby d.c. voltage applied to the receiver side of the transformer cannot be conducted to the aerial.

14. A remote control system according to any one of claims 11 to 13, wherein said control data transmitter comprises an economiser circuit operable eriodically to cut-off power to said radio frequency transmitter.

15. A remote control system according to any one of the preceding claims, wherein said frequency decoding means comprise noise-suppression means which do not allow said frequency decoding means to output a signal below a predetermined level of received signal.

16. A remote control system according to any one of the preceding claims, wherein in said control data transmitter some of said plurality of data input lines are connected to an encoding means operable to put into said some lines a binary coded word in dependence upon discrete positions of a multi-position switch coupled to said encoding means.

17. A remote control system -according to any one of the preceding claims, wherein said control data receiver comprises inhibiting means to inhibit in said plurality of data output lines transitional effects at the beginning of each demultiplexing step.

18. A remote control system according to any one of the preceding claims, wherein one data channel is adapted to transmit and receive a permanent "transmitter alive" signal when the system is in use, the receiver being operable to shut-down to safety if this signal is absent.

19. A remote control system according to any one of the preceding claims, wherein a plurality of data channels are adapted to transmit and receive a characteristic binary coded word, whereby an outside transmitter not transmitting this word would be unable to interfere with the receiver's function.

20. A remote control system substantially as hereinbefore described with reference to Figures 2 to 10 of the accompanying drawings.

21. A remote control system according to any one of the preceding claims, when said control data receiver is installed in a machine to be remotely controlled.

22. A remote control system according to claim 20, the machine being an item of mining machinery.

23. A remote control system according to claim 21 the machine being a coal-cutting machine.