GB1602984A

GB1602984A - Integrated semiconductor circuit

Info

Publication number: GB1602984A
Application number: GB1934678A
Authority: GB
Original assignee: Zaidan Hojin Handotai Kenkyu Shinkokai
Current assignee: Zaidan Hojin Handotai Kenkyu Shinkokai
Priority date: 1977-05-15
Filing date: 1978-05-12
Publication date: 1981-11-18
Also published as: NL188061B; NL7805149A; FR2391563A1; NL188061C; FR2391563B1; DE2820913C2; DE2820913A1

Description

(54) INTEGRATED SEMI CONDUCTOR CIRCUIT (71) We, ZAIDAN HOJIN HANDO TAI KENKYU SHINKOKAl, of Kawauchi, Sendai-shi, Miyagi-ken, Japan, a body corporate organized according to the laws of Japan, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement: The present invention relates to an integrated semiconductor circuit, and more particularly to a Static Induction Transistor Logic (SITL) device including a pair of static induction transistors. A static induction transistor (SIT) is a relatively new type of field effect transistor first invented by Professor J. Nishizawa and disclosed in British Patent Specification Nos. 1,393,792 and 1,396,198.

Reference should also be made to our copending Application No. 32,256/77 (Serial No.

1,599,177) for a more detailed explanation of the basic characteristics and advantages of the SIT are given. It is sufficient to mention that the region between the source and drain has a low impurity concentration, especially the length of the channel defined by the gates.

The impurity concentration and channel width are so selected that the height of the potential barrier which is produced in the channel can be controlled by the drain voltage. A potential barrier can thus be formed and controlled by the gate potential.

A static Induction Transistor Logic device (SITL device), which is a unique modification of the conventional IIL device employing bipolar transistors to serve as the injector and the driver, respectively, has been proposed in British Patent Application No. 50,823/76 (Serial No. 1,572,190) and in British Patent Application No. 32,256/77 (Serial No.

1,599,177). The basic arrangement of such an SITL device is shown in an equivalent circuit in Fig. - 1 of the accompanying drawings. As shown, the SITL device has a bi polar transistor Q, serving as the injector and a static induction transistor Q2 serving as the driver. The collector electrode of the injector transistor Q1 is coupled to the gate electrode of the driver transistor Q2, and the base electrode of the injector transistor Q1 and the source electrode of the driver transistor Q2 are mutually coupled together. For normal operation of this SITL device, the emitter electrode of the injector Q, is applied with a constant potential VEE, and the source elec- trode of the driver Q, is earthed. This SITL device will operate in a manner similar to that of the conventional IIL device employing bipolar transistors to serve as an injector and a driver, but is far superior to the conven tional IIL device in many respects, as will be described below.

Firstly, the static induction transistor serv ing as the driver Q2, is basically a majority carrier control device, and therefore it is subjected, only to an extremely reduced extent, to the so-called minority carrier storage effect which contributes to limiting the switching speed of the driver transistor in the conventional IIL device. Consequently, the SITL device can provide a much higher speed in switching operation as compared with that of the conventional IlL device.

Secondly, the static induction transistor, is basically a voltage-controlled device, so that only a small amount of power is required in the driving of the driver transistor and that the driver transistor can be easily coupled to the output of the preceding stage circuit.

Also, the power loss in the driver transistor itself is small. Accordingly, the SITL device will allow a high density integration.

Thirdly, the static induction transistor as the driver has a large transconductance and can provide an increased number of fan-outs.

As a result, the SITL device can perform any required logical operation with a simple circuit arrangement.

Fourth, the SITL device has the advantage that it is simple in construction and that it can be easily formed into a high integration density by a simple manufacturing process, as will be explained below with reference to Figs. 2 and 3 of the accompanying drawings.

An example of the basic structure of an integrated SITL device as mentioned above is illustrated in a top plan view in Fig. 2 anu is also shown in Figs. 3 in a vertical section taken along the line III--III of Fig. 2. The SITL device includes a semiconductor wafer 10 consisting of a heavily doped n type substrate 13 and a lightly doped n- type layer 14. In the semiconductor layer 14 are provided a heavily doped p+ type region 11, and a heavily doped p type region 12 of a mesh- like shape. In upper portions of the layer 14, in those portions surrounded by the region 12, there are provided heavily doped n type regions 15 and 16. The regions 11 and 12 and a portion of the layer 14 which is sandwiched between the regions 11 and 12 jointly constitute a lateral bipolar transistor serving as the injector transistor Q1 as shown in Fig. 1.

In further detail, the region 11 functions as an emitter; the region 12 functions as a collector; and the sandwiched portion of the layer 14 functions as a base. On the other hand, the layers 12, 13, 14, 15 and 16 form, jointly therewith, a static induction transistor serving as a driver transistor Q, as shown in Fig. 1. More particularly, the substrate 13 functions as a source; the region 12 functions as a gate; and the regions 15 and 16 function as respective drains. The current channels of the static induction transistor are defined to be those portions of the layer 14 which are surrounded by the region 12. There are pro vided, on the corresponding locations, drain electrodes D1 and D2, a gate/collector electrode G/C, an emitter electrode E, and a source/base electrode S/B. A passive film layer 17, such as a silicon dioxide film, or a silicon nitride film layer, is formed on the exposed upper surface of the semiconductor wafer 10.

As will be understood from Figs. 2 and 3, the SITL device can be manufactured by relying on a simple processing technique wherein the impurity diffusion step is conducted only two times and not more than four masks are required.

With such a simple structure as well as such a simple process, there has been obtained an integrated SITL device whose power delay product for low current operation is decreased to as low as 0.002 pJ or less.

Furthermore, a specimen of such SITL device exhibiting a minimized delay time of 13.8 nanoseconds or less in an operation with a power dissipation of 230 micro-watts has been produced according to the structure of Figs. 2 and 3. In this specimen, the semiconductor layer 14 has an impurity concentration of about 1014 atoms/cm3 and a thickness of about 6 ,um, the gate region 12 has an impurity concentration of about 10" atoms/cm3 or more and a thickness of about 2 ,am, and the gate mask distance is set to be about 6 micro-meters. The above-mentioned delay time of the SITL device contains several factors such as a delay for charging up the gate capacitance of the driver transistor, a delay for carrier transit across the source and the drain of the driver transistor, a carrier storage effect due to unnecessary minority carriers injected from the gate into a high resistivity region around the gate other than the current channel of the driver transistor, and a carrier storage effect due to excessive minority carriers injected from the gate into the current channel. The former three delay factors may be reduced drastically, by minimizing the thickness of the high resistivity layer 14 (see Fig. 3) to thereby bring the gate 12 into a substantial contact with the low resistivity layer 13 and thereby to reduce the effective distance between the source and the drains 15 and 16, and by minimizing the effective area of the gate 12. The provision of an insulator region at the outer boundary of the driver gate may be effective for preventing the occurrence of an unnecessary carrier injection at the boundary. The last factor may also be reduced by a decrease in the gate area.

In this manner, there has been obtained, in fact, a specimen of the SITL device whose delay time is as small as 4 nano-seconds or less.

The abovementioned excellent operating characteristics of the SITL device can never be attained by the conventional IIL device, particularly by the use of the conventional IIL device designed to provide many fan-outs.

A known modified IIL device comprised of only bipolar transistors, such as the known VIL (Vertical Injection Logic) device and SSL (Self-Aligned Super Injection Logic) device, might be seen as being somewhat comparable to the SITL device only in the delay time (characteristic minimum delay time is 8 nano-seconds), but their power delay product is roughly thirty times or more as large as that of the SITL device. Moreover, these known modified IIL devices are structurely extremely complicated and difficult to manufacture as compared with the SITL device.

The SITL device has many excellent features as mentioned above, but still it leaves room for improvement. One problem is represented by the minority carrier storage effect which is developed in the static induction transistor serving as the driver transistor of the SITL device, which is caused by the excessive minority carriers injected into the current channel from the gate when the driver transistor is in the conductive state. The current which is supplied by the injector transistor, after having charged the gate capacitance of the driver transistor up to a required potential, will continue to flow to charge the gate capacitance up to an excessively high potential, because the injector current is usually kept substantially constant. As a result, the gate junction of the driver transistor is deeply forward-biased, so that an excessively large amount of carriers are injected, thus bringing about the above-described carrier storage effect. Since a static induction transistor, basically, is a majority carrier control device, the degree of the minority carrier storage effect developing at the current channel of the static induction transistor serving as the driver is very low as compared with that in a bipolar transistor. However, the carrier storage effect must be a great obstruction in obtaining a further increase in the operating speed of the SITL device.

Such minority carrier storage effect at the current channel in the driver static induction transistor might be eliminated by replacing the injector bipolar transistor in the SITL device by a static induction transistor, as proposed in Japanese Patent Laid-open Publication No. 89,687/78 and in Japanese Patent Laid-open Publication No. 100,783/78.

Suppose that a device to be employed as the injector transistor has such ideal drain-source voltage Vd, versus drain current 1d character istic as shown by the solid line in Fig. 4 of the accompanying drawings, in which after the gate potential of the driver transistor has exceeded a certain potential Vgo necessary to render the driver transistor conductive, the drain current Id will be suppressed to a desirable minimum value. In the case where an injector transistor has such a characteristic as stated just above, the unrequired excessive minority carrier injection in the driver transistor can be suppressed, and thus the carrier storage effect is greatly reduced. In addition, if the injector transistor is able to supply a sufficiently large amount of drain current Id to quickly charge the gate capacitance of the driver transistor up to said potential Vro, a sufficiently high speed turning-on operation could be performed by the driver transistor.

It should be noted, however, that an actual static induction transistor has such a drainsource voltage versus drain current characteristic shown by the dash-and-dot line in Fig. 4.

As the gate capacitance of the driver transistor is being charged up with the injector drain current and as, thus, the gate potential of the driver transistor together with the drain potential of the injector transistor is being pulled up, the drain current of the injector transistor will tend to gradually decrease because of its decreasing drain-source voltage. For this reason, it is impossible to accomplish at the same time both the elimination of the excessive minority carrier injection and quick charging-up of the gate capacitance of the driver transistor, in accordance with such arrangement of the SITL device wherein the injector is replaced by a static induction transistor.

It is an object of the present invention to overcome partially or wholly the abovementioned disadvantages by providing an improved integrated semiconductor device which is capable of making switching operations at an increased speed.

According to the present invention there is provided an integrated semiconductor circuit having an input terminal, an output terminal and a reference voltage terminal, first and second junction-gate static induction transis tors each comprising a source semiconductor region of a first conductivity type, a channel semiconductor region of said first conductivity type, a drain semiconductor region of said first conductivity type, and a gate semiconductor region of a second conductivity type opposite to said first conductivity type, said drain semiconductor region of said first junction-gate static induction transistor being connected to said output terminal, said gate semiconductor region of this first transistor being connected to said input terminal, and said source semiconductor region of this first transistor being connected to said reference voltage terminal, the gate semiconductor region and the drain semiconductor region of said second junctiongate static induction transistor being electrically connected to each other and also to said input terminal, and the source semiconductor region of this second transistor being connected to said reference voltage terminal, whereby, when the voltage of the gate semiconductor region of said first junction-gate static induction transistor exceeds a predetermined voltage level, said second junction-gate static induction transistor is turned "on" to effect bypassing between the gate semiconductor region of the first transistor and said reference voltage terminal.

The present invention will now be described in greater detail by way of example with reference to the remaining figures of the accompanying drawings, wherein: Fig. 5 is a vertical sectional view of an example of the SITL device according to the present invention; Fig. 6 is a circuit diagram showing an equivalent circuit of the SITL device shown in Fig. 5; Figs. 7 and 8 are vertical sectional views of two further different examples of the SITL device according to the present invention; Fig. 9 is a circuit diagram showing an equivalent circuit of an example of the wired logic circuit constructed with several SITL devices embodying the present invention; and Figs. 10A and 10B are graphs illustrating an example of the drain voltage-drain current characteristics of the driver static induction transistor and the bypass static induction transistor in a STIL device according to the present invention, respectively.

An example of the improved SITL device according to the present invention is shown in vertical section in Fig. 5. The SITL device includes a semiconductor wafer 110 comprised of a heavily doped n+ type substrate 113 and a lightly doped n- type layer 114.

The semiconductor layer 114 may be formed by relaying on the conventional epitaxial growth technique or diffusion technique.

Alternatively, the layer 113 may be formed to be a buried region in a p+ type substrate.

In the semiconductor layer 114, which is made of silicon, for instance, there are provided individual highly doped p+ type regions 121, 122, 123, 124 and 125. The regions 122 to 125 need to be held at a same potential, so that they are electrically connected together.

In general, all of the regions 122 to 125 may be formed in a continuous form such as a grid, mesh shape or stripe shape. At those locations in the semiconductor layer 114 which are surrounded by the respective regions 122 to 125, there are provided separate heavily doped n+ type regions 115, 116 and 117.

Ohmic electrodes 133, 134, 135 and 136 are deposited on the regions 121 to 116, respectively. Also, an ohmic electrode 137 is deposited to make ohmic connection between the two regions 124 and 125. A passivation film 118 of an insulating material, such as silicon dioxide, covers the exposed portions of the upper surface of the semiconductor layer 114.

In the embodiment shown in Fig. 5, the n+ type layer 113 and the n+ type regions 115 to 117 have an impurity concentration of 10"-10" atoms/cm3. The n- type layer 114 has an impurity concentration of 101121016 atoms/cm3. Each of the p type regions 121 to 125 has an impurity concentration of 102'21021 atoms/cm3.

The equivalent circuit of the SITL device shown in Fig. 5 is illustrated in Fig. 6. In this Figure, reference symbol Qi represents a pnp type bipolar transistor serving as the injector transistor of the SITL device, and reference symbol Qd represents an n-channel static induction transistor employed to serve as the driver transistor. The driver transistor Qd has two separate drains D, and D,, a gate Gd, and a source Sd. The injector transistor Qi has an emitter E, a collector C connected to rhe gate Gd of the driver transistor, and a base B connected to the source of the driver transistor. An additional n-channel static in ducdon transistor Qb for providing a current path across the gate and source of the driver transistor Qd is introduced into the circuit as shown. This additional transistor Qb, which is hereinafter to be called a bypass transistor, has - a gate Gb connected to the gate Gd of the driver transistor Qd, a drain Db connected to the gate Gb, and a source Sb connected to the source 5d of the driver transistor.

Description will now be. made on the co relationship between Fig. 5 and Fig. 6. The driver transistor Qd comprises layers 113 and 114, and regions 115, 116, 122, 123 and 124. The layer 113 serves as the source Sd; the regions 122 to 124 serve as the gate G,; the regions 115 and 116 serve as the drains D1 and D2; and those portions of the layer 114 which are surrounded by the respective regions 122 to 124 serve as separated current channels. Similarly, the bypass transistor Qb is constituted by the layer 113 serving as the source Sb, the region 117 serving as the drain Di, the regions 124 and 125 working as the gate Gb, and that portion of the layer 113 which serves as the current channel and which is surrounded by the regions 124 and 125.

On the other hand, the regions 121 and 122 constitute the emitter E and the collector C of the injector transistor Qi. Also, a portion of the layer 114 located between the emitter and the collector serves as the base B of the injector transistor Qi. As will be apparent, the collector of the injector transistor Qi and the gate of the bypass transistor Qb are merged into the gate of the driver transistor Qd, respectively, thereby being held at the same potential with that of the driver gate.

Similarly, the source of the bypass transistor Qb and the base of the injector transistor Qi are held at the same potential with the source potential of the driver transistor Qd.

The operation of the above described embodiment will now be explained in greater detail.

Suppose that a predetermined voltage VEE is constantly applied to the emitter E of the injector transistor Qi to cause this transistor to be rendered conductive, and that an external device (not shown) is connected across the gate Gd and the source Sd of the driver transistor Qd.

In the case where the external device in the preceding stage is turned "on" and the current supplied from the conductive injector transistor is all taken by the external device, the gate of the driver transistor is held at the low level voltage such as 0.120.2V, for instance. Under this condition, both the driver transistor and the bypass transistor are rendered to the "off" state, because the current channels of these transistors are pinched-off by the gate-channel depletion layers, and because there are thus developed high potential barriers in the current channels. In other words, the static induction transistors Qd and Qb are designed so that the gate-channel diffusion potential difference may cause the gatechannel depletion layers extending from the gate to spread all over the current channel.

The higher the impurity concentration of either the gate or the current channel is, and also the more abrupt the impurity concentration change at the boundary between the gate and the current channel is, the larger will become the gate-channel diffusion potential difference. As the gate-channel diffusion potential difference increases, the static induction transistor logic will be able to have a wider logic voltage swing.

It should be noted here that the bypass transistor has the gate coupled to the drain, and that accordingly this bypass transistor exhibits a voltage-current characteristic wherein the drain current will non-linearly increase with an increase in the drain-source voltage.

This voltage-current characteristic is dependent mainly upon the ratio of the distance between the drain and the intrinsic gate, which intrinsic gate being the extreme point of the potential barrier induced in the current channel, to the distance between said intrinsic gate and the source. In general, when the value of the above ratio is large, the bypass transistor will exhibit a more gentle incrementation in the drain current for an increase in the drain-source voltage. The above discussion, supposes that the bypass transistor has a voltage-current characteristic similar to that of a constant-voltage diode. In particular let us suppose that the bypass transistor will remain substantially non-conductive for a drain voltage lower than the certain gate voltage Vjgo of the driver transistor, but that for a drain voltage not lower than said certain gate voltage Vgo, the bypass transistor will become conductive thus keeping the drain-source voltage thereof almost constant. The above voltage VgO is about 0.520.8 volt in the case where the SITL device is formed with silicon.

Next, the operation of the above described embodiment will be described when the external device in the preceding stage is turned off. Upon turning the external device off, the current, which is an almost constant current and is supplied from the injector transistor, then turns to flow towards the gate of the driver and bypass transistors. At the onset, almost all of the current supplied will flow into the gate capacitance of the driver transistor, because the potential at the driver transistor gate still remains to be very low. Accordingly, the gate capacitance is rapidly charged up, with the result that the gate potential is quickly raised up to said certain gate potential Vg,. As a result, the driver transistor is turned "on" immediately after the turning-off of the preceding stage external device. At substantially the sane time with the turning-on of the driver transistor, on the other hand, the bypass transistor will change to become conductive because its drain has been applied with a required voltage not less than Veg0. Therefore, a large part of the current supplied from the injector transistor is bypassed through the bypass transistor and thus a further increase in the driver gate potential is allowed only to be a small value.

As described above, once the driver transistor has been turned "on", the driver gate potential is substantially prevented from mak ing a further increase, due to the action of the bypass transistor. Thus, an unnecessary excessive minority carrier injection into the current channel of the driver transistor will not occur. Furthermore, an unrequired injection of minority carriers into any high resistivity region located adjacent to the gate other than the current channel region of the driver transistor will not occur. As a result, the minority carrier storage effect which would take place at the driver transistor is minimized while securing an increased speed of the turning-on action of the driver transistor. It should be noted here than an adequate amount of minority carriers is constantly injected from the gate into the current channels of the driver transistor to hold this driver transistor in the conducting state. Therefore, the voltagecurrent characteristic of the bypass transistor must meet the above requirement for the driver transistor. Namely, the internal resistance of the bypass ratnsistor in the conductive state needs to be held relatively higher than that of the driver transistor in the conducting state. This condition may be accomplished by setting the width of the current channel of the bypass transistor to be slightly smaller than that of each of the current channels of the driver transistor. Alternatively, for the same purpose, the impurity concentration of the bypass transistor channel needs to be determined so as to be slightly lower than that of the current channels of the driver transistor. In short, the bypass transistor should be designed so that there may be induced in its current channel a slightly higher potential barrier than those induced in the current channels of the driver transistor.

When the preceding stage external device is turned "on" again, the driver transistor will immediately turn "off" because of the minimized minority carrier storage effect in the driver transistor.

A modification of the SITL device of Fig.

5 is shown in vertical section in Fig. 7. In this example, the impurity concentration of those portions 200, 201, 202 and 203 which serve actually as the base of the injector transistor and the current channels of the driver and the bypass transistors, is set to be lower than that of the remaining portions in the layer 114 excepting the gates 122 to 125 and the emitter 121. For instance, the former impurity concentration is set to be about 1011p,101j atoms/cm3 and the latter impurity concentration is determined to be about 1013 atoms/cm3 or more. With this arrangement, the minority carriers are allowed to be injected mainly into real current channel regions 201 to 203 from the gate regions 122 to 125, and also effectively into the base region 200 from the emitter region 121. Because the diffusion potential difference is large, the injection of holes from the p type gate regions 122 to 125 into the n type regions 201' to 203' which are located between the n- type regions 201 to 203 and the n+ type regions 115 to 117, respectively, is not very intensive.

In other words, this arrangement is attributed to a reduction in the unnecessary injection of minority carriers into those high resistivity regions other than the real current channels and the base and to a further reduction in the minority carrier storage effect in the SITL device.

Since the gate regions of the driver transistor are reduced in size, the gate capacitance as well as the minority carrier storage effect of the driver transistor become even smaller.

Therefore, in the embodiments of Figs. 5 and 7, the known ion-implantation technique preferably is applied for forming the gate regions of reduced size.

A further modification of the SITL device of Fig. 5 is illustrated in vertical section in Fig. 8, in which the gates of both the driver transistor and the bypass transistor are formed into minute p type regions 122B, 123A, 123 B, 124A, 124B and 125A, and in which the collector of the injector transistor is formed as a p+ type region 122A separated from the gate region 122B. All of the respective gate (or collector) regions 122A, 122B, ......

125A are electrically and mutually connected to conducting layers 210, 211 and 212 of a conducting material such as aluminium, sistor may be replaced by a junction-type or MOS-type field effect transistor having a saturated drain voltage versus drain current characteristic like a bipolar transistor. Furthermore, the number of the drains or the current channels of the driver transistor may be changed as required.

An example of the logic circuit constructed by wiring several SITL devices is illustrated in Fig 9. This circuit includes three circuit units 300, 301 and 302 each of which consists of an SITL device such as those shown in Figs. 5, 7 and 8, but the driver transistor Qd of the SITL device 302 has only one drain.

The respective SITL devices 300, 301 and 302 may be formed in a discrete fashion, or they may be formed integrally in a single common semiconductor wafer. The emitters of the injectors Qi in the respective SITL devices 300, 301 and 302 are connected to a line applied with a constant positive voltage VEE. The sources of the driver transistors Qd in the respective SITL devices are earthed.

The drains of the driver transistor Qd in the SITL devices 300 and 301 are mutually wired. Two input signals A and B are respectively applied to the gates of the driver transistors Qd in the SITL devices 300 and 301.

When both input signals assume the logic "0" level (e.g. a low level voltage), the driver transistors Qd of the SITL devices 300 and 301 are rendered non-conductive i.e. turned to the "off" state, and then the driver transistor Qd in the SITL device 302 is rendered conductive i.e. turned to the "on" state. If both input signals A and B are at the logic "1" level, (a high level voltage) the driver transistors of the SITL devices 300 and 301 will be caused to turn "on", so that the driver transistor of the SITL device 302 is turned "off". In the case where the input signal B is at the logic "1" level and the input signal A is at the logic "0" level, the driver tran sistor of the SITL device 301 is turned on while the driver transistor of the SITL device 300 is turned off. Accordingly, in this con dition, the driver transistor of the SITL de vice 302 is in the "off" state. In short, at the drain of the driver transistor in the SITL device 302 is delivered the logical sum (OR) of the two inputs A and B. On the other hand, the inverted logical sum (NOR) of these two inputs A and B is obtained at the respective drains of the driver transistors in the SITL devices 300 and 301.

Further reference will now be made to the voltage-current characteristic of the bypass transistor in the SITL device.

In the previous discussion, the bypass tran sistor is assumed to have such a voltage-current characteristic that the drain-source voltage is kept substantially constant when the bypass transistor is in the conductive state. This assumption means that the possible highest level assigned for the gate potential of the driver transistor of the SITL device is determined to be a certain fixed value associated with the drain-source voltage of the conducting by-pass transistor.

In contrast thereto, it is often desired in many applications of the SITL device that the possible highest level assigned for the gate potential of the driver transistor; i.e. the input potential of the SITL device, is variable.

Furthermore, there is often the case wherein a plurality of similar SITL devices are used in cascade connection to form a particular logic circuit as in the case of Fig. 9. In this case, the gate of the driver transistor in a certain stage SITL device is connected to the drain of the driver transistor in the preceding stage SITL device, whilst the drain of the former driver transistor is coupled to the gate of the driver transistor in a subsequent stage SITL device. Accordingly, the abovementioned assumption will necessarily lead to the fact that the possible highest level allowed for both the input and the output of the whole stage SITL devices is limited to a same value which is associated with the voltage-current characteristic of the bypass transistor but which is fixed irrespective to the value of the potential applied at the emitter of the injector transistor.

However, there is sometimes the case wherein the input and/or output highest level for some stage SITL device need to be set so as to be different from that of the other stage SITL devices.

In order to attain the variability of the input and/or output highest level, the bypass transistor preferably may be given such a voltage-current characteristic that the drainsource voltage of the bypass transistor will increase with a certain gradient in accordance with an increase in the drain current thereof.

The certain gradient should be properly determined depending upon the voltage-current characteristic of the driver transistor, as will be explained below.

In the case where the driver transistor has such a drain voltage Vd - drain current Id characteristic as shown in a semi-log scale in Fig. 10A, an example of the possible drain voltage Vd - drain current Id characteristic of the bypass transistor may be as illustrated in a semi-log scale in Fig. 10B. In Fig. 10A, Vg represents a gate voltage of the driver transistor. This characteristic of Fig. 10B is determined so as to satisfy, for a wide range of variation of the potential VEE applied at the injector transistor emitter, the conditions of Vff - VL > 0, and also to satisfy the condition that when the gate potential of the driver transistor, i.e. the input potential of the SITL device, is at a certain VH level, some of the injection current supplied by the injector transistor is allowed to flow through the bypass transistor. In the Figure, Vx and VL represent the high level and the low level of the input and output of the SITL device, respectively.

Let us suppose here a logic circuit comprised of two SITL devices connected in cascade manner, in each of which the driver transistor and the bypass transistor have the voltage-current characteristics of Figs. 10A and lOB, respectively. When the potential VEE is set at a relatively low potential, the output potential of the first stage SITL device is variable between 0.1 volt (the low output level) and 0.2 volt (the high output level). In this condition, the input potential of the second stage SITL device is varied between 0.1 volt (the low input level) and 0.2 volt (the high input level). Alternatively, when the potential VEE is determined so as to be a relatively high potential, the output potential of the first stage SITL device will be variable between 0.1 volt (the low output level) and 0.6 volt (the high output level). At the same time, the input potential of the second stage SITL device is variable between 0.1 volt (the low input level) and 0.6 volt (the high input level).

As will be apparent from the above explanation, the high level which is assigned for either the input or the output may be freely varied in accordance with the potential VEx.

WHAT WE CLAIM IS:- 1. An integrated semiconductor circuit having an input terminal, an output terminal and a reference voltage terminal, first and second junction-gate static induction transistors each comprising a source semiconductor region of a first conductivity type, a channel semiconductor region of said first conductivity type, a drain semiconductor region of said first conductivity type, and a gate semiconductor region of a second conductivity type opposite to said first conductivity type, said drain semiconductor region of said first junction-gate static induction transistor being connected to said output terminal, said gate semiconductor region of this first transistor being connected to said input terminal, and said source semiconductor region of this first transistor being connected to said reference voltage terminal, the gate semiconductor region and the drain semiconductor region of said second junction gate static induction transistor being electrically connected to each other and also to said input terminal, and the source semiconductor region of this second transistor being connected to said reference voltage terminal, whereby, when the voltage of the gate semiconductor region of said first junction-gate static induction transistor exceeds a predetermined voltage level, said second junction-gate static induction transistor is turned "on" to effect bypassing between the gate semiconductor region of the first transistor and said reference voltage terminal.

2. An integrated semiconductor circuit according to Claim 1, wherein said first and second static induction transistors are formed in a single common semiconductor body, said first transistor including: a first semiconductor layer; a source having a first con ductivity type and provided in said first semiconductor layer; a drain having said first conductivity type and provided in said first semiconductor layer; a current channel having said first conductivity type and provided in said first semiconductor layer between said drain and said source; and a gate having a second conductivity type opposite to said first conductivity type and provided adjacent to said current channel to define a boundary of said current channel, said second transistor including: a second semiconductor layer; a source having said first conductivity type and provided in said second semiconductor layer; a drain having said first conductivity type and provided in said second semiconductor layer; a current channel having said first conductivity type and provided in said second semiconductor layer between this drain and this source; and a gate having said second conductivity type and located adjacent to this current channel to define a boundary of this current channel, said gate of said second transistor being electrically connected to both said drain of said second transistor and said gate of said first transistor, said sources of said both transistors being electrically connected to each other.

3. An integrated semiconductor circuit according to Claim 2, in which both said first and second semiconductor layers are merged into a single common semiconductor layer.

4. An integrated semiconductor circuit according to Claim 3, in which said source of both said first and second transistors are merged into a single common semiconductor region having said first conductivity type.

5. An integrated semiconductor circuit according to Claim 3, in which said gate of said second transistor is formed continuous to said gate of said first transistor.

6. An integrated semiconductor circuit according to Claim 2, in which: said current channel of said first transistor comprises a first semiconductor region contacting a particular portion of said gate of said first transistor, and a second semiconductor region contacting a portion of said gate of said first transistor excluding said particular portion, and in which: said first semiconductor layer has said first conductivity type, said first semiconductor region having an impurity concentration lower than those of said second semiconductor region and of said first semiconductor layer.

7. An integrated semiconductor circuit according to Claim 6, in which: the current

**WARNING** end of DESC field may overlap start of CLMS **.

Claims

**WARNING** start of CLMS field may overlap end of DESC **. of the input and output of the SITL device, respectively. Let us suppose here a logic circuit comprised of two SITL devices connected in cascade manner, in each of which the driver transistor and the bypass transistor have the voltage-current characteristics of Figs. 10A and lOB, respectively. When the potential VEE is set at a relatively low potential, the output potential of the first stage SITL device is variable between 0.1 volt (the low output level) and 0.2 volt (the high output level). In this condition, the input potential of the second stage SITL device is varied between 0.1 volt (the low input level) and 0.2 volt (the high input level). Alternatively, when the potential VEE is determined so as to be a relatively high potential, the output potential of the first stage SITL device will be variable between 0.1 volt (the low output level) and 0.6 volt (the high output level). At the same time, the input potential of the second stage SITL device is variable between 0.1 volt (the low input level) and 0.6 volt (the high input level). As will be apparent from the above explanation, the high level which is assigned for either the input or the output may be freely varied in accordance with the potential VEx. WHAT WE CLAIM IS:-

1. An integrated semiconductor circuit having an input terminal, an output terminal and a reference voltage terminal, first and second junction-gate static induction transistors each comprising a source semiconductor region of a first conductivity type, a channel semiconductor region of said first conductivity type, a drain semiconductor region of said first conductivity type, and a gate semiconductor region of a second conductivity type opposite to said first conductivity type, said drain semiconductor region of said first junction-gate static induction transistor being connected to said output terminal, said gate semiconductor region of this first transistor being connected to said input terminal, and said source semiconductor region of this first transistor being connected to said reference voltage terminal, the gate semiconductor region and the drain semiconductor region of said second junction gate static induction transistor being electrically connected to each other and also to said input terminal, and the source semiconductor region of this second transistor being connected to said reference voltage terminal, whereby, when the voltage of the gate semiconductor region of said first junction-gate static induction transistor exceeds a predetermined voltage level, said second junction-gate static induction transistor is turned "on" to effect bypassing between the gate semiconductor region of the first transistor and said reference voltage terminal.

channel of said second transistor comprises a third semiconductor region contacting a certain portion of said gate of said second transistor, and a fourth semiconductor region contacting a portion of said gate of said second transistor excepting said certain portion, and in which: said second semiconductor layer has said first conductivity type, said third semiconductor region having an impurity concentration lower than those of said fourth semiconductor region and of said second semiconductor layer.

8. An integrated semiconductor circuit according to Claim 2, in which: those portions of said gate of said first transistor other than a particular portion thereof are covered with insulator layers, said gate of said first transistor contacting, only at said particular portion thereof, said current channel of said first transistor.

9. An integrated semiconductor circuit according to Claim 8, in which: those portions of said gate of said second transistor other than a particular portion thereof are covered with insulator layers, said gate of said second transistor contacting, only at said particular portion thereof, said current channel of said second transistor.

10. An integrated semiconductor circuit according to Claim 2, in which: said first semiconductor layer has a recess provided in this layer and opening outwardly at a surface of the layer, said gate of said first transistor extending from a particular portion of the inner surface of said recess into said first semiconductor layer.

11. An integrated semiconductor circuit according to Claim 10, in which: said second semiconductor layer has a recess provided in this layer and opening outwardly at a surface of the layer, said gate of the second transistor extending from a particular portion of the inner surface of the recess into the second semiconductor layer.

12. An integrated semiconductor circuit according to Claim 11, in which: both said recesses in said first and second semiconductor layers are formed into a common recess, and said gate of said first transistor is connected to said gate of said second transistor by a conducting layer provided in said common recess.

13. An integrated semiconductor circuit according to Claim 1, further comprising: a power supply terminal, and a third transistor connected between the power supply terminal and said input terminal in order to serve as a current supply source.

14. An integrated semiconductor circuit according to Claim 1, further comprising a third bipolar transistor, said third bipolar transistor including: a third semiconductor layer; an emitter having said second conductivity type and provided in said third semiconductor layer; a collector having said second conductivity type and pro vided in said third semiconductor layer, said collector being electrically connected to said gate of said first transistor; and a base having said first conductivity type and provided in said third semiconductor layer between said collector and said emitter, the base being electrically connected to said source of said first transistor.

15. An integrated semiconductor circuit according to Claim 14, in which: all of said first, second and third semiconductor layers are merged into a single common semicon ductor layer having said first conductivity type.

16. An integrated semiconductor circuit according to Claim 15, in which: said gates of said first and second transistors and the base of said third transistor are a common region of said single common semiconductor layer, respectively, which region having an impurity concentration lower than those of said sources of said first and second transistors.

17. An integrated semiconductor circuit according to Claim 16, in which: all of said gates of said first and second transistors and the collector of said third transistor are formed continuous to each other.

18. An integrated semiconductor circuit according to Claim 15, in which: said sources of said first and second transistors are merged into a single common semiconductor region having said first conductivity type.

19. An integrated semiconductor circuit according to Claim 15, in which: each of said current channels of said first and second transistors comprises a first semiconductor region contacting a particular portion of the gate, and a second semiconductor region contacting a portion of the gate excluding said particular portion, said first semiconductor region having an impurity concentration lower than those of the second semiconductor region and of said single common semiconductor layer.

20. An integrated semiconductor device according to Claim 14, in which: those portions of each of said gates of said first and second transistors other than a particular portion of the gate are covered with insulator layers; the gate contacting, only at said particular portion thereof, the current channel.

21. An integrated semiconductor circuit according to Claim 15, in which: said single common semiconductor layer has at least one recess provided in the layer and opening outwardly at a surface of the layer, each of said gates of said first and second transistors extending into the layer from a particular portion of the inner surface of the recess.

22. An integrated semiconductor circuit according to Claim 21, in which: said emitter of said third transistor is formed to extend into said single common semiconductor layer from another particular portion of the inner surface of said recess.

23. An integrated semiconductor circuit according to Claim 21, in which: said gate of said first transistor is connected to said gate of said second transistor by a conducting layer provided in said recess.

24. An integrated semiconductor circuit according to Claim 22, in which: all of said gates of said first and second transistors and said emitter of said third transistor are mutually connected by a conducting layer provided in said recess.

25. An integrated semiconductor circuit according to Claim 1, further comprising: a third transistor having a control electrode held at a reference potential, a first electrode, and a second electrode applied with a potential to thereby cause a current to flow through said first electrode; said second transistor having such a voltage-current characteristic that when its drain is applied with a certain potential, it becomes conductive to thereby allow a part of said current supplied from said first electrode of said third transistor to flow through the second transistor, said certain potential, when applied at said gate of said first transistor, allowing said first transistor to become conductive.

26. An integrated semiconductor circuit according to Claim 25, in which: said part of said current is the major part of said current.

27. An integrated semiconductor circuit according to Claim 25 or 26, in which: said third transistor is a bipolar transistor, and in which: said control, first and second electrode of said third transistor are a base, collector and emitter of the third transistor, respectively.

28. An integrated semiconductor circuit according to Claim 25 or 26, in which: said third transistor is a field effect transistor, and in which: said control, first and second electrodes are a gate, drain and source of the third transistor.

29. An integrated semiconductor circuit constructed substantially as herein described with reference to and as illustrated in Fig. 5, or Fig. 7 or Fig. 8 of the accompanying drawings.

30. A static induction transistor logic circuit constructed and arranged to operate substantially as herein described with reference to and as illustrated in Fig. 9 of the accompanying drawings.