GB1599083A

GB1599083A - Dc thyristor pulse-width controlled converter digital control apparatus

Info

Publication number: GB1599083A
Application number: GB924978A
Authority: GB
Original assignee: VNII VAGONOSTROENIA
Current assignee: VNII VAGONOSTROENIA
Priority date: 1978-03-08
Filing date: 1978-03-08
Publication date: 1981-09-30

Description

(54) D.C. THYRISTOR PULSE-WIDTH CONTROLLED CONVERTER DIGITAL CONTROL APPARATUS (71) We, VSESOJUZNY NAUCHNO ISSLEDOVATELKSY INSTITUT VAGONOSTROENIA., of Pushkinskaya ulitsa, 11, Moscow, USSR., do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement: The present invention relates to control means for static converters and more particularly, to a thyristor pulse width controlled d.c. converter digital control device. The device of the present invention can be used to control the speed of rotation of d.c.

machines employed in industry and in railroad transport; it can also be used to control the voltage across an inductive load.

According to the present invention there is provided a d.c. thyristor pulse-width controlled converter digital control apparatus, comprising a decoder having a first set of information inputs connected to respective information outputs of a clock pulse counter driven by the output of a master oscillator and having individual individual outputs at which there appear oppositely phased control pulses of constant repetition rate, a second set of informtion inputs of the decoder being connected to respective information outputs of a reversible counter, two outputs of the decoder at which there appear pulses capable of being time displaced being electrically coupled via a control pulse switching unit to control electrodes of controlled thyristors of the converter, control pulse outputs of the decoder being connected to inputs of a setting unit for adjusting the states of the control pulse switching unit and of the reversible counter to correspond with the state of a control unit, other inputs of the setting unit being connected respectively to 'increase voltage' and to 'decrease voltage' outputs of the control unit and to an initial state reset output of the control unit, which is also connected to initial state reset inputs of the reversible counter and of the master oscillator, first respective outputs of the setting unit being connected to add and subtract inputs of the reversible counter, further outputs of the setting unit being connected to inputs of the control pulse switching unit, the setting unit including four AND gates and a bistable trigger, whereas the control pulse switching unit includes six AND gates and two divider flip-flops with counting inputs, an output of a first AND gate of the control pulse switching unit being connected to a control electrode of a first thyristor, which is also connected to a first output of the clock pulse counter, which is also connected to the input of a first said divider flip-flop, an output of a second AND gate being connected to a control electrode of a second thyristor, which is also connected to a second output of the clock pulse counter, which is also connected to the input of the second said divider flip-flop, an output of the third AND gate being connected to a control electrode of a third thyristor, a first input of the third AND gate being connected to an output of the second divider flip-flop, and output of a fourth AND gate being connected to a control electrode of a fourth thyristor, a first input of the fourth thyristor, a first input of the fourth AND gate being connected to an output of the first divider flip-flop, signals from the output of the fifth AND gate being arranged to be applied to the control electrodes of the first and third thyristors, a first input of the fifth AND gate being connected to a first control pulse output of the decoder, which is also connected to a first input of the second AND gate, signals from the output of the sixth AND gate being arranged to be applied to the control electrodes of the second and fourth thyristors, a first input of the sixth AND gate being connected to the second control pulse output of the decoder, which is also connected to a first input of the first AND gate, while in the setting unit, first inputs of a first and of a second AND gate are connected to the 'increase voltage' output of the control unit, first inputs of a third and a fourth AND gate of the setting unit being connected to the 'decrease voltage' output of the control unit, the outputs of the second and fourth AND gates of the setting unit being connected to the add input of the reversible counter, the subtract input of which is connected to outputs of the first and third AND gates of the setting unit, a reset input of the reversible counter being connected to a third control pulse output of the decoder, which is also connected to a first input of the bistable trigger, the second input of the bistable trigger being connected to a fourth control pulse output of the decoder and to the reset output of the control unit, the first output of the bistable trigger being connected to second inputs of the second and third AND gates of the setting unit and of the first, second, third and fourth AND gates of the control pulse switching unit, and the second output of the bistable trigger being connected to second inputs of the first and fourth AND gates of the setting unit and of the fifth and sixth AND gates of the control pulse switching unit.

A better understanding of the present invention will be had from a consideration of the following detailed description of a preferred embodiment thereof, taken in conjunction with the accompanying drawings, wherein: Figure 1 is a block diagram of a d.c.

thyristor pulse-width controlled converter digital control device in accordance with the invention and a controlled converter; Figures 2a, 2b and 2c are graphs showing the voltages across different elements of the controlled converter versus time during a first stage of control; Figures 3a, 3b and 3c are graphs similar to those of Figure 2 but showing voltages across elements of the controlled converter versus time during a second stage of control.

Referring to the attached drawings, Figure 1 shows a d.c. thyristor pulse-width controlled converter digital control apparatus comprising a decoder 1, a clock pulse counter 2 having information outputs connected to a first set 3 of information inputs of the decoder 1, a reversible counter 4 having information outputs connected to a second set 4 of information inputs of the decoder 1, and a master oscillator 6 having its output connected to an input of the clock pulse counter 2.

The apparatus shown in Figure 1 further includes a control pulse switching unit 7. a control unit 8 and a setting unit 9 for adjusting the states of the control pulse switching unit 7 and of the reversible counter 4 to correspond with that of the control unit 8.

The control pulse switching unit 7 comprises six, two input AND gates 10, 11, 12, 13, 14 and 15, and first and second divider flip-flops 16 and 17 with counting inputs.

In the ensuing description the term "directional junction" is used to denote an arrangement in which signals cannot leave a junction by way of a lead bearing an arrow directed towards the junction. Diodes are usually employed to provide this action.

The output of the AND gate 10 is connected by way of a directional junction 61 to the control electrode of a first controlled thyristor 18 of a converter arranged to be controlled by the apparatus of the invention. This electrode is also connected by way of another directional junction 62 to receive signal from a first individual output 19 of the clock pulse counter 2, which signals are also applied to an input of the first dividider flip-flop 16.

The output of the AND gate 11 is connected by way of a directional junction 63 to the control electrode of a second controlled thyristor 20 of the converter. This electrode is connected by way of a further directional junction 64 to receive signals from a second individual output 21 of the clock pulse counter 2, from which signals are also applied to the input of the second divider flip-flop 17.

The output of the AND gate 12 is connected by way of a directional junction 65 to the control electrode of a third controlled thyristor 22 of the converter; a first input of the AND gate 12 is connected to an output of the second divider flip-flop 17.

The output of the AND gate 13 is connected by way of a directional junction 66 to the control electrode of a fourth controlled thyristor 23 of the converter; a first input of the AND gate 13 is connected to the output of the first flip-flop 16.

The output of the AND gate 14 is connected by way of directional junctions 62 and 61 to the control electrodes of the first thyristor 18 and by way of a directional junction 65 to the third thyristor 22 of the converter; a first input of the AND gate 14 is connected to a first control pulse output 24 of the decoder 1, which is also connected to a first input of the AND gate 11.

The output of the AND gate 15 is connected by way of directional junctions 64 and 63 to the control electrode of the second thyristor 20 and by way of a directional junction 66 to that of the fourth thyristor 23 of the converter; a first input of the AND gate 15 is connected to a second control pulse output 25 of the decoder 1, which is also connected to a first input of the AND gate 10.

The setting unit 9 for adjusting the states of the control pulse switching unit 7 and of the reversible counter to correspond with that of the control unit 8 comprises a bistable trigger 26 and four, two-input AND gates 27, 28, 29 and 30.

First inputs of the AND gates 27 and 28 are connected to an 'increase voltage' output 31 of the control unit 8. First inputs of the AND gates 29 and 30 are connected to a 'reduce voltage' output 32 of the control unit 8.

The outputs of the AND gates 28 and 30 are connected to an add input 33 of the reversible counter 4 of which a subtact input 34 is connected to the output of each of the AND gates 27 and 29. A reset input 35 of the reversible counter 4 is connected to a first control pulse output 36 of the decoder 1, which is also connected to a first input 37 of the bistable trigger.

The second input 38 of the bistable trigger 26 is connected by way of a directional junction to a second control pulse output 39 of the decoder 1 and to a reset output 40 of the control unit 8.

The reset output 40 of the control unit 8 is also connected to a reset input 41 of the reversible counter 4 and to a reset input of the master oscillator 6.

A first output 42 of the bistable trigger is connected to the second inputs of the AND gates 10, 11, 12, 13, 28 and 29 and the second output 43 of the bistable trigger 26 is connected to the second input of each of the AND gates 14, 15, 27 and 30.

In addition to the controlled thyristors 18, 20, 22 and 23, the converter includes a commutating capacitor 44 connected in the diagonal of the bridge formed by the aforesaid controlled thyristors 18, 2(), 22 and 23.

The thyristors 18 and 20 are shunted by respective switching circuits comprising the series combination of a diode 45, 46 and a reactor 47, 48.

In series with the thyristor 22 is a load composed of an armature 49 and an exciting winding 50, which are connected in series and are shunted by a diode 51.

In series with the thyristor 23 is a load composed of an armature 52 and an exciting winding 53, which are connected in series and are shunted by a diode 54.

Figure 2a shows voltage pulses 55. 56, 57 and 58 applied in a first stage of control to the control electrodes of the thyristors 18, 20, 22 and 23 plotted against time t; Figure 2b shows the voltage U appearing across the switching capacitor 44, plotted against time t; Figure 2c shows the voltage U appearing across the load plotted against time t.

Figure 3 shows corresponding parameters in a second stage of control: Figure 3a shows voltage pulses 59. 6(1, 61 and 62 applied to the control electrodes of the thyristors 18, 20, 22 and 23 plotted against time t; Figure 3b shows the voltage U appearing across the switching capacitor 44 plotted against time t; Figure 3c shows the voltage U appearing across the load plotted against time t.

The above-described d.c. thyristor pulsewidth controlled converter digital control apparatus operates as follows.

At the commencement of operation there is applied from the output 40 (Figure 1) of the control unit 8 to the input 41 of the reversible counter 4 and to the input of the master oscillator 6 a reset signal which sets the reversible counter 4 and the master oscillator 6 to their respective initial states.

This reset signal is also applied to the input 38 of the bistable trigger 26, whereby the latter is brought to a steady state in which a signal appears at its output 43.

From the output of the master oscillator 6 there are now continuously applied to the input of the clock pulse counter 2 clock pulses which arrive at a frequency selected in accordance with the operating frequency of the thyristors 18, 20. 22 and 23 of the controlled converter, and also in accordance with the capacity of the counters 2 and 4.

These clock pulses change the state of the stages of the clock pulse counter 2 so that there are applied from its respective outputs 19 and 21 to the control electrodes of the thyristors 18 and 2() pulses of constant repetition rate whose frequency is equal to the operating frequency of the thyristors.

During the first half-period of these control pulses a pulse appears at the output 19 of the counter 2; during the second halfperiod a pulse appears at the output 21 of the counter 2.

Thus at the moment of time t (Figure 2a) there is applied to the control electrode of the first controlled thyristor 18 a pulse 55 which drives the thyristor 18 into conduction. As this takes place, the commutating capacitor 44 is recharged in the opposite polarity, by way of a circuit including the capacitor 44, the switching diode 46, the switching reactor 48, and the thyristor 18.

At this time the thyristor 22 of the converter bridge is not conductive, so no voltage is applied to the series combination of armature 4t? and exciting winding 50.

After the capacitor 44 is recharged in the opposite polarity, the voltage across it is less than the initial voltage Ue, (Figure 2b), by an amount A U, which is due to resistance losses in the recharging circuit.

During the first stage of control, a minimum voltage is applied to the load within the first half period; the time interval between the switching on of the thyristor 18 and the subsequent switching on of both of the thyristors 18 and 22 simultaneously is at its maximum, which is due to a maximum time shift between the pulses arriving from the output 19 of the clock pulse counter 2, which turns on thyristor 18, and those from the output 24 of the decoder 1, which turn on both of thyristors 18 and 22.

During the second half period, the aforesaid minimum voltage is applied to the load with a maximum interval between the switching on of the thyristor 20 and the subsequent switching on of both of the thyristors 20 and 23, which is due to a maximum time shift between the pulses arriving from the separate output 21 of the clock pulse counter 2 and those from the output 25 of the decoder 1.

As a signal is applied from the 'increase voltage' output 31 of the control unit 8 to the input of the AND gate 27, to the second input of which there is applied a signal from the output 43 of the bistable trigger 26, the AND gate 27 is driven into conduction so that there is applied to the 'subtract input' 34 of the reversible counter 4 a signal which changes the counting state of the reversible counter 4.

If the states of the counters 2 and 4 coincide, pulses appear at the outputs 24 and 25 of the decoder 1. These pulses are mutually phase-displaced by 1800 and are shifted in time with respect to the pulses coming from the outputs 19 and 21 of the clock pulse counter 2 by an amount which is inversely proportional to the product of the duration of one of the quantization steps into which the switching period of the thyristors 18, 20. 22 and 23 is divided, multiplied by the number of pulses applied to the subtract input 34 of the reversible counter 4.

From the output 24 of the decoder 1, a pulse is applied to the input of the AND gate 14, to the other input of which a signal is applied from the output 43 of the bistable trigger 26. The AND gate 14 is driven into conduction and at the moment of time t2 (Figure 2a) it applies a pulse 56 to the control electrodes of both of the thyristors 18 and 22.

As the thyristors 18 and 22 are thus simultaneously driven into conduction. the commutating capacitor 44 is charged to reach the initial voltage level, which is done through a circuit composed of the armature 49, the exciting winding 50 and a power source represented by terminals + and -.

At this instant, the voltage applied to the load is equal to A U (Figure 2b).

At the end of the first half period of the pulses of constant repetition rate, at the moment of time t3 (Figure 2a) the pulse 57 is applied from the output 21 of the clock pulse counter 2 to the control electrode of the thyristor 20 and; drives the thyristor 20 into conduction.

As this takes place, the capacitor 44 is recharged in the opposite polarity through the circuit composed of the capacitor 44, the switching diode 45, the switching reactor 47 and the thyristor 20. After the capacitor 44 is thus charged in the opposite polarity. the voltage across it is lower than the initial voltage UO (Figure 2b) by an amount A U, which corresponds to the resistance losses of the recharging circuit.

After the first half of the repetition period of the time-displaced control pulses, the next pulse produced at the output 25 of the decoder 1 is applied to the input of the AND gate 15, to the other input of which there is applied a signal from the output 43 of the bistable trigger 26.

At the instant t4 (Figure 2a) the AND gate 15 is driven into conduction so that the pulse 58 is simultaneously passed to the control electrodes of the thyristors 20 and 23.

As this takes place, the switching capacitor 44 is recharged to the initial voltage level, by way of the circuit composed of the armature 52, the exciting winding 53 and the power source.

During the interval between the pulses, the current through the load is maintained with the aid of the inverse diodes 51 and 54.

As pulse signals continue to be applied from the output 31 of the control unit 8 to the subtract input 34 of the reversible counter 4, the counting state of the counter is reduced. When the states of the clock pulse counter 2 and of the reversible counter 4 coincide, there is a reduction in the time difference between the pulses arriving from the outputs 19 and 21 of the counter 2 and the pulses arriving from the outputs 24 and 25 of the decoder 1. The reduction in this interval corresponds to an increase in the voltage applied to the load.

With a minimum interval equal to the quantization step of the switching period of the thyristor 18. 20, 22 and 23, which is dependent upon the digit capacity of the counters 2 and 4, a signal is produced at the output 36 of the decoder 1.

This signal is applied to the input 37 of the bistable trigger 26. whereby the latter is brought to its alternative steady state determined by the presence of a signal at the output 42 and the absence of a signal at the output 43.

Simultaneously, a signal is applied from the output 36 of the decoder 1 to the reset input 35 of the reversible counter 4, whereby the latter is brought back to its initial state ready for the second stage of control.

Control signals continue to arrive in the setting unit 9 from the output 31 of the control unit 8 and are applied via the AND gate 28, to the second input of which there is applied a signal from the output 42 of the bistable trigger 26, to the add input 33 of the reversible counter 4, which starts adding.

From the output 42 of the bistable trigger 26, the signal is also applied to the inputs of the AND gates 10, 11, 12 and 13.

During the second stage of control, a pulse from the output 19 of the clock pulse counter 2 is applied to the input of the flip-flop 16; the first pulse arriving at the input of the flip-flop 16 makes the latter ready to produce a signal; the next pulse arriving at the input of the flip-flop 16 produces an output signal of the latter; the next input pulse brings the flip-flop 16 to a state at which there is no signal at its output and so on.

Thus every alternate pulse applied to the input of the flip-flop 16 actuates the latter.

The flip-flop 17 operates in the same maner as the flip-flop 16 in response to signals from output 21 of counter 2.

The signals produced at the output of the flip-flop 16 are applied to the control electrode of the thyristor 23 via the AND gate 13, to the other input of which there is applied a signal from the output 42 of the bistable trigger 26, and the directional junction 66.

At the moment of time t5 (Figure 3a), the pulse 59 is simultaneously applied to the control electrodes of the thyristors 18 and 23.

The thyristors 18 and 23 are driven into conduction, and the voltage of the power source (Figure 3c) is applied to the load circuit composed of the winding 53 and the armature 52. At this moment (Figure 3b), the capacitor 44 starts recharging.

During the second stage of control, the first half period is marked by an increase in the time shift between the pulses applied to the thyristors 18 and 23 and the pulses applied to the thyristor 20. During the second half period of the second stage of control, there is an increase in the time difference between the pulses applied to the thyristors 20 and 22 and the pulses applied to the thyristor 18.

When the state of the clock pulse counter 2 and that of the reversible counter 4 coincide, there is produced at time t6 from the output 24 of the decoder a pulse 60 (Figure 3b) which is applied via the AND gate 11 to the control electrode of the thyristor 20; to the second input of the AND gate 11 there is applied a signal from the output 42 of the bistable trigger 26.

The same pulse is simultaneously applied from the output of the AND gate 11 to the input of the divider flip-flop 17, whereby the second divider flip-flop 17 is brought to a state at which there is no signal at its output; this means that the flip-flop 17 is ready to produce a signal at its output upon the arrival of a further pulse at its input.

Thus at the moment of time t6 (Figure 3b), the pulse 60 drives the thyristor 20 into conduction, and there is applied to the thyristor 18 the inverse voltage of the capacitor 44 whose recharging is complete; the sum of the voltage of the power source and that on the capacitor 44 is applied to the load composed of the exciting winding 53 and the armature 52.

When the recharging of the capacitor 44 through the diode 45 and the reactor 47 is complete (Figure 3b), voltage is no longer applied to the load (this takes place at the moment of time t7).

Upon the end of the first half period of the constant repetition rate control pulses, another pulse is produced at the output 21 of the clock pulse counter 2, which pulse is simultaneously applied to the control electrode of the thyristor 20 and to the counting input of the divider flip-flop 17, which is ready to produce a signal at its output.

Upon the arrival of the pulse at the input of the divider flip-flop 17, the signal is applied from the output of the flip flop to the control electrode of the thyristor 22, which is done via the AND gate 12 to the other input of which there is applied a signal from the output 42 of the bistable trigger 26.

Thus at the moment of time t8 (Figure 3a), the pulse 61 simultaneously drives the thyristors 20 and 22 into conduction; as this takes place, the voltage of the power source is applied to the load composed of the winding 50 and the armature 49 (Figure 3c) and the capacitor 44 starts recharging (Figure 3b) to the opposite polarity through the diode 45 and the reactor 47.

At the end of the second half period of repetition of the time displaced control pulses and in case of coincidence between the state of the clock pulse counter 2 and that of the reversible counter 4, at time t9 the next pulse 62 is produced at the output 25 of the decoder 1 (Figure 3b).

This pulse is applied to the control electrode of the thyristor 18 via the AND gate 10 to whose other input there is applied a signal from the output 42 of the bistable trigger 26.

This pulse is simultaneously applied to the counting input of the divider flip-flop 16, whereby the latter is brought to a state at which there is no signal at its output; this means that the flip-flop 16 is prepared to produce a signal at its output upon the arrival of the next pulse at its input.

Thus at time t9 (Figure 3a), the pulse 62 drives the thyristor 18 into conduction; to the thyristor 20 there is applied the inverse voltage of the capacitor 44 whose recharging is complete (Figure 3b); the sum of the voltage of the power source and that on the capacitor 44 is appplied to the load composed of the winding 53 and the armature 52.

As signals continue to be applied from the output 31 of the control unit 8 to the add input 33 of the reversible counter 4, the counter state is progressively changed; coincidence of the state of the clock pulse counter 2 with that of the reversible counter 4 increases the time shift between the pulses arriving from the outputs 19 and 21 of the counter 2 and the pulses arriving from the outputs 24 and 25 of the decoder 1. During this second stage of control the increase in this interval corresponds to an increase in the voltage applied to the load.

When the last stage of control setting is reached, a holding condition occurs.

In order to effect a return towards the initial condition a return condition signal is applied from the 'reduce voltage' output 32 of the control unit 8 to the input of the AND gate 29 to the other input of which a signal is applied from the output 42 of the bistable trigger 26. From the output of the AND gate 29, a signal is applied to the subtract input 34 of the reversible counter 4, whereby the counter stages are brought to a respective state. If the state of the counter 4 coincides with that of the clock pulse counter 2, there is a reduction in the time shift between the pulses arriving from the output 19 of the counter 2 and the pulses applied to the control electrode of the thyristor 22, as well as a decrease in the interval between the pulses applied to the control electrode of the thyristor 20 and the pulses applied to the control electrode of the thyristor 23.

Each alternate signal arriving from the output 32 of the control unit 8 decreases the duration of the output voltage pulse by one quantization step.

At the end of the second control stage, during which voltage across the load is reduced by reducing the difference in the time at which the respective thyristors of the converter are driven into conduction, there is produced at the output 39 of the decoder 1 a signal for a return to the first stage of control. This signal is applied to the input 38 of the bistable trigger 26, whereby the latter is brought to its initial steady state. As this takes place, there is no longer a signal at the output 42.

The converter output voltage is further reduced during the first stage of control by increasing the interval between the time at which the thyristor 18 is driven into conduction and the time at which the thyristors 18 and 22 are simultaneously driven into conduction, and also increasing the interval between the time at which the thyristor 20 is driven into conduction and the time at which the thyristors 20 and 23 are simultaneously driven into conduction.

During the first stage of control, the signal from the output 32 of the control unit 8 is applied to the input of the AND gate 30 to the other input of which there is applied a signal from the output 43 of the bistable trigger 26. The output signal of gate 30 is thus applied to the add input 33 of the reversible counter 4, which therefore adds and so increases the interval between the time of arrival of pulses at the control electrode of the thyristor 18 and the time of arrival of pulses at the control electrode of the thyristor 22, as well as the time difference between the arrival of pulses at the control electrode of the thyristor 20 and of the pulses at the control electrode of the thyristor 23. The order in which pulses are applied to the electrodes of the thyristors 18, 20, 22 and 23 is as described above for the case of voltage increase, only the sequence of events is reversed, as compared with the latter case.

Apparatus in accordance with the present invention ensures the aforesaid sequence of connecting the outputs 24 and 25 of the decoder 1 and the outputs 19 and 21 of the clock pulse counter 2 to the control electrodes of the thyristors 18, 20, 22 and 23 of the converter and provides for digital control of the thyristor-pulse converter with a common commutation unit and with precharging of the switching capacitor 44 without the main thyristors.

When used to control the speed of rotation of d.c. machines, the de

Claims

**WARNING** start of CLMS field may overlap end of DESC **. voltage of the power source and that on the capacitor 44 is appplied to the load composed of the winding 53 and the armature 52. As signals continue to be applied from the output 31 of the control unit 8 to the add input 33 of the reversible counter 4, the counter state is progressively changed; coincidence of the state of the clock pulse counter 2 with that of the reversible counter 4 increases the time shift between the pulses arriving from the outputs 19 and 21 of the counter 2 and the pulses arriving from the outputs 24 and 25 of the decoder 1. During this second stage of control the increase in this interval corresponds to an increase in the voltage applied to the load. When the last stage of control setting is reached, a holding condition occurs. In order to effect a return towards the initial condition a return condition signal is applied from the 'reduce voltage' output 32 of the control unit 8 to the input of the AND gate 29 to the other input of which a signal is applied from the output 42 of the bistable trigger 26. From the output of the AND gate 29, a signal is applied to the subtract input 34 of the reversible counter 4, whereby the counter stages are brought to a respective state. If the state of the counter 4 coincides with that of the clock pulse counter 2, there is a reduction in the time shift between the pulses arriving from the output 19 of the counter 2 and the pulses applied to the control electrode of the thyristor 22, as well as a decrease in the interval between the pulses applied to the control electrode of the thyristor 20 and the pulses applied to the control electrode of the thyristor 23. Each alternate signal arriving from the output 32 of the control unit 8 decreases the duration of the output voltage pulse by one quantization step. At the end of the second control stage, during which voltage across the load is reduced by reducing the difference in the time at which the respective thyristors of the converter are driven into conduction, there is produced at the output 39 of the decoder 1 a signal for a return to the first stage of control. This signal is applied to the input 38 of the bistable trigger 26, whereby the latter is brought to its initial steady state. As this takes place, there is no longer a signal at the output 42. The converter output voltage is further reduced during the first stage of control by increasing the interval between the time at which the thyristor 18 is driven into conduction and the time at which the thyristors 18 and 22 are simultaneously driven into conduction, and also increasing the interval between the time at which the thyristor 20 is driven into conduction and the time at which the thyristors 20 and 23 are simultaneously driven into conduction. During the first stage of control, the signal from the output 32 of the control unit 8 is applied to the input of the AND gate 30 to the other input of which there is applied a signal from the output 43 of the bistable trigger 26. The output signal of gate 30 is thus applied to the add input 33 of the reversible counter 4, which therefore adds and so increases the interval between the time of arrival of pulses at the control electrode of the thyristor 18 and the time of arrival of pulses at the control electrode of the thyristor 22, as well as the time difference between the arrival of pulses at the control electrode of the thyristor 20 and of the pulses at the control electrode of the thyristor 23. The order in which pulses are applied to the electrodes of the thyristors 18, 20, 22 and 23 is as described above for the case of voltage increase, only the sequence of events is reversed, as compared with the latter case. Apparatus in accordance with the present invention ensures the aforesaid sequence of connecting the outputs 24 and 25 of the decoder 1 and the outputs 19 and 21 of the clock pulse counter 2 to the control electrodes of the thyristors 18, 20, 22 and 23 of the converter and provides for digital control of the thyristor-pulse converter with a common commutation unit and with precharging of the switching capacitor 44 without the main thyristors. When used to control the speed of rotation of d.c. machines, the device of this invention makes it possible to improve the effectiveness of d.c. machines employed in industry and railroad transport. WHAT WE CLAIM IS:

1. A d.c. thyristor pulse-width controlled converter digital control apparatus, comprising a decoder having a first set of information inputs connected to respective information outputs of a clock pulse counter driven by the output of a master oscillator and having individual outputs at which there appear oppositely phased control pulses of constant repetition rate, a second set of information inputs of the decoder being connected to respective information outputs of a reversible counter, two outputs of the decoder at which there appear pulses capable of being time displaced being electrically coupled via a control pulse switching unit to control electrodes of controlled thyristors of the converter, control pulse outputs of the decoder being connected to inputs of a setting unit for adjusting the states of the control pulse switching unit and of the reversible counter to correspond with the state of a control unit, other inputs of the setting unit being connected respectively to 'increase voltage' and decrease voltage' outputs of the control unit and to an initial

state reset output of the control unit, which is also connected to initial state reset inputs of the reversible counter and of the master oscillator, first respective outputs of the setting unit being connected to add and subtract inputs of the reversible counter, further outputs of the setting unit being connected to inputs of the control pulse switching unit, the setting unit including four AND gates and a bistable trigger, whereas the control pulse switching unit includes six AND gates and two divider flip-flops with counting inputs, an output of a first AND gate of the control pulse switching unit being connected to a control electrode of a first thyristor which is also connected to a first output of the clock pulse counter. which is also connected to the input of a first said divider flip-flop, an output of a second AND gate being connected to a control electrode of a second thyristor, which is also connected to a second output of the clock pulse counter, which is also connected to the input of the second said divider flip-flop, an output of the third AND gate being connected to a control electrode of a third thyristor, a first input of the third AND gate being connected to an output of the second divider flip-flop, an output of a fourth AND gate being connected to a control electrode of a fourth thyristor, a first input of the fourth AND gate being connected to an output of the first divider flip-flop, signals from the output of the fifth AND gate being arranged to be applied to the control electrodes of the first and third thyristors, a first input of the fifth AND gate being connected to a first control pulse output of the decoder, which is also connected to a first input of the second AND gate, signals from the output of the sixth AND gate being arranged to be applied to the control electrodes of the second and fourth thyristors, a first input of the sixth AND gate being connected to the second control pulse output of the decoder, which is also connected to a first input of the first AND gate. while in the the setting unit, first inputs of a first and of a second AND gate are connected to the 'voltage increase' output of the control unit, first inputs of a third and a fourth AND gate of the setting unit being connected to the decrease voltage output of the control unit, the outputs of the second and fourth AND gates of the setting unit being connected to the add input of the reversible counter the subtract input of which is connected to outputs of the first and third AND gates of the setting unit, a reset input of the reversible counter being connected to a third control pulse output of the decoder, which is also connected to a first input of the bistable trigger, the second input of the bistable trigger being connected to a fourth control pulse output of the decoder and to the reset output of the control unit, the first output of the bistable trigger being connected to second inputs of the second and third AND gates of the setting unit and of the first, second, third and fourth AND gates of the control pulse switching unit, and the second output of the bistable trigger being connected to second inputs of the first and fourth AND gates of the setting unit and of the fifth and sixth AND gates of the control pulse switching unit.

2. A d.c. thyristor pulse-width controlled converter digital control apparatus substantially as herein described with reference to Figure 1 of the accompanying drawings.

3. A d.c. thyristor pulse-width controlled converter control apparatus constructed and operating. substantially as herein described with reference to the accompanying drawings.