GB1598075A - Digital computer and a method of testing a digital computer - Google Patents

Description

(54) A DIGITAL COMPUTER AND A METHOD OF TESTING A DIGITAL COMPUTER (71) We, the POST OFFICE, a British body corporate established by Statute, of 23 Howland Street, London, W1P 6HQ, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement: This invention relates to a digital computer and to a method of testing a digital computer.

The invention also includes an automatic telegraph exchange which incorporates such a digital computer.

It has been proposed to use digital computers to control telephone and telegraph exchanges and for such usage it is clearly important that the computer should be very reliable.

It is an object of the invention to provide more or less continuous monitoring of the operation of a digital computer.

According to one aspect of the present invention there is provided a method of testing a digital computer in which instructions forming a program of the computer are divided into groups each followed by a stop instruction, so that during the normal running of the program a group of instructions is started at the beginning of a time period allocated to that group and the stop instruction will have been reached before the end of that time period, and therefore the program is stopped for a brief interval at the end of each such time period, and, for each group of instructions, at the end of the time period allocated to the particular group of instruc tions, a test is made to ascertain whether the program has been stopped.

According to a second aspect of the present invention there is provided a digital computer including means for storing a program including a plurality of instructions, means for selecting the instructions sequentially, means for decoding the selected instructions, means for executing the decoded instructions, timing means for controlling the selection and execution of the instructions and means for detecting a stop instruction when selected by the selecting means, wherein the instructions are divided into groups each of which is started at the beginning of a respective allocated time period and is terminated by a stop instruction, and testing means is provided responsive to the timing means for ascertaining for each group of instructions whether the stop instruction has been reached before the end of the time period allocated to the performance of the particular group of instructions.

If a stop instruction is not reached before the end of the time period allocated to the performance of the group of instructions, the program may be restarred from a datum position such as the beginning. The same time period may be allocated to a plurality of groups of instructions.

The digital computer may be operated "on line", for example as a real time event controller. In one example of the invention the digital computer is used to control an automatic telegraph exchange.

A public telegraph network exists for connecting teleprinters at different locations and this network is commonly known as the telex network. In a manner similar to that provided for telephones, teleprinters are able to be connected to other teleprinters and transfer written messages from one place to another.

Unlike the telephone system, however, the rate of transmission of data from a teleprinter is relatively slow, and typically a character is allocated a time interval of 150 ms, each character being represented by a combination of five digits each occupying an interval of 20 ms and preceded by a start element of 20 ms duration and followed by a stop element of 30 ms duration. Interconnection between the teleprinters has been provided using mechanical switches of the uniselector or Strowger type, in which an electrical path dedicated to the transmission of the digits is provided from one teleprinter to the other.

It has been found that such an arrangement is particularly expensive, bearing in mind the low rate of data transmission, and a digital computer according to the invention can be used to produce a less expensive exchange for telegraph signals.

According to another aspect of the present invention there is provided an automatic telegraph exchange having a plurality of ports for connection to respective lines leading to other telegraph apparatus, at least one access unit connected to the ports and a digital computer according to the second aspect of the invention connected to the or each access unit, the digital computer including means for receiving and storing instructions obtained from telegraph data and means for sending control signals to the or each access unit to regulate the transfer of telegraph data between the access unit and the digital computer, wherein the digital computer is arranged to form independent virtual interconnection paths between the ports defined by instructions stored by the storing means and which are serviced in sequence a plurality of times within the duration of each digit of the telegraph data.

The high speed of operation of the digital computer makes it appear to the telegraph data that the interconnection paths exist simultaneously.

The digital computer may be arranged to sample each digit of telegraph data for a short period of time, for example 62.5 fits, compared with the duration of the digit, e.g.

20 ms, the short period of time being located at the middle of the digit, thereby to lessen the effects of the degradation of the digits during transmission. The timing of the sampling period relative to the telegraph data may be selected by examining the data at a succession of adjacent sampling periods and identifying in which periods the digit is positive and in which it is negative so that the beginnings and ends of the digits can be located and thence the central sampling periods determined.

Such an exchange is particularly but not exclusively suited to use as a private branch exchange with one of the ports connected to an exchange of the public service telex network and the others connected to different teleprinter installations.

The digital computer would include data storage means, probably of a random access nature, a read-only memory for program information, and a data processing unit, and would be arranged to perform the usual logical functions required and may also include facilities for enabling special functions which would be required frequently in the operation of the exchange to be performed in response to single program instructions; such facilities would not only reduce considerably the amount of storage needed for the program information.

but would also enable the processing to be performed in less time.

A broadcasting facility may be provided in the exchange by the digital computer, the function of which facility would be to identify the individual lines of a group specified by a caller and cause the computer to transmit the incoming message to the lines or teleprinter installations belonging to the group.

The broadcasting facility would therefore contain a store for the identities of the lines constituting the different groups to which broadcasting would be required. A message store could be provided for storing the message for subsequent transmission to any lines or teleprinters which were engaged at the time the message was received.

The or each access unit, which is controlled by the digital computer to receive data from different lines and pass it to the computer and to transmit data from the computer to the lines thereby to form the required interconnection paths between the lines, may in dude a status store which records which lines are free and which are busy, the store being updated when a change in status of any line occurs. A problem could arise if, owing to a spurious pulse due to noise or a brief power failure, for example, the status of a line became recorded as busy when it was in fact free, because the line would be lost to the exchange. Moreover this difficulty would be cumulative so that after a period of time all lines might become lost and the exchange would then be unable to call any line. In order to prevent this happening the busy status of any line is checked periodically by applying to the status for that line every time it is accessed by the computer a digit derived from the logic state of a long period (about 30 seconds, say) square wave, and checking the corresponding digit stored in the status store for all lines against the current logic state of the long period square wave. Any difference between the two values would indicate that the line concerned had not been accessed for several seconds at least, and was incorrectly being treated as busy by the central processing means. The status of the particular line could then be corrected.

An access unit may also be provided with a store for storing for each line connected to the exchange through the unit the class of service allocated to the particular line and the class of traffic which the line provides thereby indicating the form of telegraph equipment to which the line is connected.

In order that the invention may be fully understood and readily carried into effect it will now be described with reference to the accompanying drawings, of which: Figure 1 is a timing diagram which will be referred to in explaining the operation of an example of a telegraph exchange employing a digital computer according to the invention; Figure 2 is a block diagram of the exchange; Figure 3 is a block diagram of the digital computer used in the exchange shown in Figure 2; and Figure 4 is a block diagram of an access unit of the exchange shown in Figure 2.

A digital computer according to an example of the invention will be described with reference to a telegraph exchange employing the computer.

The telegraph exchange described herein makes use of the higher operation speed of semiconductor switches and other components relative to the digit rate of telegraph signals to operate serially on a plurality of calls at such a rate that the calls have virtually continuous interconnection paths which exist simultaneously. As the digital computer, or the central processing unit as it is referred to in the following description, works on only one call or call attempt at a time, it is necessary to store the facts relating to the other calls in a memory, and in the example to be described random access memories are used for this purpose.

In Figure 2, a central processing unit is indicated by a reference 11 and a random access memory by a reference 12. Also connected to the CPU 11 are a read-only memory 13 and a broadcast unit 14, the functions of which will be described later.

Access units 15, 16, 17 and 18 are connected to the CPU 11 and each access unit is shown as having connected to it two line units having the references 15A, 1sub; 16A, 16B; . . . 18B.

In one practical example of the exchange, each access unit is constructed to handle the inputs from and outputs to six line units, so that the four access units shown in Figure 2 has connections for 24 lines, and in practice would normally have more than the 8 line units shown in Figure 2 connected to it. Each line unit is intended to be connected to some kind of telegraph equipment which may, for example, be a telex unit, another telegraph exchange or a line to a public service exchange to which the exchange is connected.

When the CPU 11 is instructed to interrogate a particular line it makes a request on a data highway which is common to the access units 15, 16, 17 and 18. One of the access units will recognise the identity of the line to be interrogated and will effect the connection of the appropriate line unit to the CPU. At the same time the access unit will make available to the CPU information giving the class of service, class of traffic and status of the particular line which the CPU will then use appropriately. The class of service is preset information relating to the particular line and indicates if priority is to be given to signals from the line and/or whether telex access from the line is allowed. The class of traffic indicates whether the telegraph equipment connected to the line operates as a normal telex station, a station forming part of an auxiliary hunting group, a dial selection trunk line for connection to the telex or a keyboard selection trunk line to another private branch exchange. The status of a line shows whether the equipment connected to the line is free, busy, busy on a priority call or busy receiving a broadcast. Other categories of status may be provided for such installations.

The line units 15A, 15B, etc., are simple signal converters which serve to convert the signals within the exchange to the 80 volt signals normally applied to teleprinters and vice versa. The line circuits may take a different form when they are provided for connection to other private exchange or to public service exchanges. The line units will not be considered in detail because the form of these equipments is outside the scope of this invention and would depend very much on the form of external signal required.

Before considering the operation of the exchange in detail it would be appropriate to consider this form of signals with which the exchange is concerned and the way in which these signals are treated within the exchange.

Referring now to Figure 1, each coded character is allocated a period of 150 ms which is divided between five code elements each occupying 20 ms, a "start" element of 20 ms and a "stop" element of 30 ms duration.

Within the exchange each period of 20 ms allocated to a code element is subdivided into sixteen equal parts each of 1.25 ms. Each of these 1.25 ms parts is treated in the same way and the purpose of this sub-division is to enable the exchange to select a part of an incoming pulse nearest the middle period of time allocated to that pulse, so that the degradation of the pulse resulting from, for example, long distance line transmission can be avoided. In each of the 1.25 ms parts the exchange provides fifteen 62.5 ,us periods allocated respectively to the fifteen different calls which the exchange can handle at the same time, together with a 312.5 zs period allocated to the broadcast facility. The CPU 11 operates on the fifteen possible calls in turn within the respective 62.5 1S time slots or on the broadcast facility in the remaining 312.5 ,us time slot. These time slots cycle continuously 800 times a second and the CPU is arranged to perform the operations necessary to receive a code element from one line unit, regenerate it and apply it to an access unit for transmission to another line unit, thereby acting to provide virtually independent connecting circuits between different line units as required. Time slots which are not allocated to a particular connection between line units are arranged to scan continuously the unoccupied line units to look for a calling condition.

When the CPU finds a calling condition the status of the calling line unit is changed to busy and the attempt to establish a connection proceeds. Should the incoming call be requesting a broadcast then the CPU interrogates a status store allocated to the broadcast time slot, and if this store is marked free it is changed to busy and the number of the calling line is transferred into the random access memory for association with the broadcast time slot. If a line is allocated to the broadcast time slot the original time slot in which the calling condition was found is released to search for other calling conditions and the call continues under the control of the broadcast time slot. When all of the fifteen normal time slots are busy, any further call attempts by any line are ignored.

The random access memory 12 which in one example of the invention consists of two identical units, each able to store 128 words each of 8 bits. The memory 12 stores all of the facts required for the sixteen calls which the exchange can handle at one time, the sixteen calls consisting of the fifteen normal line to line calls and one broadcast call.

The read only memory 13 records the programs which instruct the CPU 11 on its work. The instructions of the program are stored as 8 bit words, and in one example of the invention 3072 such words can be stored. The programs for the CPU are divided into three groups. In the first group the programs enable the CPU to look for incoming calls, to reply to the calling signals and receive the selection information and to generate service signals and control the call clearing procedure of the exchange. The second group controls part of the hunting for a calling line and testing for the status of the line being called, seizes the called line and completes the connection of the call. The third group of programs controls part of the hunting for a calling condition and the testing of the status of the called line, and also controls the broadcast facility and provides programs for the maintenance of the exchange. In addition to the programs the ROM 13 stores the signals and messages used during the setting up of a call.

The broadcast unit 14 provides the special facilities required for broadcast calls, and this will be described in detail subsequently.

Each of the access units 15, 16, 17 and 18 is of the same form and will be described in detail later with reference to Figure 4.

The operation of the exchange will now be considered in further detail with reference to Figure 3 which shows in block diagrammatic form one example of the construction of the central processing unit 11 of Figure 2. The functions to be performed by the central processing unit have been described above in outline, and the manner in which they are implemented will now be considered in greater detail. The CPU performs the programs required of it in a repetitive cycle of three steps as follows: 1. interrogate the ROM 13 and read the next instruction 2. decode the instruction and set up the various control signals required by it 3. complete the instruction.

As the instructions consist of 8 bit words, a total of 256 different instructions is possible.

The instructions will require reception of data from an access unit, transmission of data to an access unit, transfer of data from one register to another within the CPU itself, the performance of certain logical operations on the stored data including certain specific operations such as receiving and sending data which would be required frequently, the transfer of information to and the reading of information from addresses of the random access memory 12 and the provision of control pulses for operations in other units of the exchange.

The CPU divides its time into slots, each of which is independent of the other slots and has associated with its own group or page of addresses in the random access memory 12.

As mentioned above, there are fifteen time slots of 62.5 ps duration and a broadcast time slot of 312.5 ps duration so that the RAM has 16 addresses for each time slot. The CPU is arranged to treat the data associated with each time slot independently of the data of the other time slots, so that it could be said that each time slot is unaware of the existence of the other time slots. There must, however, be some inter-slot communication, for example, where a particular line is being called and the CPU must act to indicate to the calling line that the called line is not available.

This operation would be performed using the status store which is included in each access unit.

The programs used by the CPU are so constructed that they can be divided into parts which can be executed within a time slot, and this cannot be achieved exactly in each case so that each part of a program is followed by a stop instruction which is used as described later on to monitor the correct functioning of the CPU. At the end of each time slot the clock causes an interrupt sequence to be started so that the change from one time slot to the next can be performed.

Other features of the CPU which will become evident as the description proceeds are that the programs are stored in incorruptible read only memories, the random access memory for the storage of data is completely separate from the program read only memory, the time of the processor is rigidly divided into time slots to each of which is allocated its own group of registers of the random access memory, the unit is designed to recover automatically from transient faults, a register is allocated to each line and is included within the access unit for that line, and special instructions are provided to enable the CPU to handle telegraph signals directly in serial form.

Referring now to Figure 3, the example of the CPU shown includes eleven registers each of 8 bits; the registers are as follows: PC is the program counter which is used to address the particular instructions on a page of program A.

PP is a program page store which is used to address the program page.

A and B are two general purpose registers.

C is used to store an address in the random access memory 12. The upper four bits of the address identify the page of the RAM and are therefore allocated to a particular time slot while the lower four bits provide part of the identification of an address on the particular page.

D is the decode latch which is used to hold an instruction whilst it is being decoded.

IP is an input port latch.

IQ is a second input port latch.

OP is an output register.

OQ is another output register.

MPC is a mini program counter, which is used for addressing a mini program memory.

As shown in Figure 3, the registers PC, PP, A, B, C, IP, IQ, OIP, OQ and the lower four bits of D are connected to send data on to a main parallel highway 100. The registers PC, PP, A, B, C, OP and OQ can receive data from the highway 100. The random access memory 12 is also connected to send data to and receive data from the highway 100.

There are nine fundamental types of instructions which the central processing unit can perform; these are: data transfers, logical operations, arithmetic add, increment, shift, detect call clear algorithm, send character algorithm, receive character algorithm and jumps.

Of these instruction types, some are provided for in units 101 to 106 which are connected to receive data directly from and transmit data directly to the main highway 100. Unit 101 provides the receive character algorithm and unit 102 the send character algorithm. The detect call clear algorithm is provided by unit 103 and the arithmetic add algorithm by unit 104. Units 105 and 106 comprise four bit exclusive-NOR gates and four bit NAND gates respectively and provide for the logical operations.

The data transfer instructions are achieved directly from register to register or between the registers and the RAM in 8 bit parallel form via the highway 100.

The registers PC, A and C, already mentioned, are constructed so as to be able to increment or count in response to pulses applied to the registers. The register PC increments as an 8 bit number automatically at the end of each instruction so as to address the next instruction. The register A is arranged so that it can be incremented as an 8 bit number or as a 4 bit number occupying the lower four digit places. Register C acts as two separate 4 bit registers which can be incremented separately. The mini program counter MPC can also have the lower four bits of a number stored in it incremented so as to address the instructions of the mini program in sequence.

The register B is able to shift downwards so that bit 8 moves to digit place 7, bit 7 to digit place 6, and so on. The input to digit place 8 of the register B is from bit l of the highway 100. Thus by transferring data to register B it is possible to rotate an 8 bit number one bit at a time. Since all data transfers involve the highway 100 and the highway 100 is arranged to be able to perform the interchange of upper and lower four bits of a number, it is clear that any data transfer can be arranged to include a 4 bit shift.

Jump instructions are used to control and change the sequence in which the program is followed. The jump instructions are executed by the use of the register PC which, as explained above, operates as the program counter. When a number is transferred into register PC the program jumps to the instruction indicated by the number introduced into the register PC. Instruction numbers for jumps are entered via unit 117 and control logic 108.

The receive character algorithm provided by the unit 101 uses registers A and B with two input registers to convert a serial telegraph character into parallel form stored in the register B. The algorithm can also be used to regenerate elements of a character.

During the execution of the receive character algorithm, which is repeated for each time slot once in every frame, the lower four stages of the register A are operated as a four-bit counter overflowing into the fifth and sixth stages the outputs of which together form a flag in response to which logical operations are performed. The seventh stage of the register A records the received line condition, and its eighth stage stores the digit value represented by the line condition in regenerated form and this bit is applied sequentially at the bit rate of the telegraph character to the output register OP. The overflows from the lower four stages of the register A are also used to cause shifts of the register B into which the start element is entered once it has been verified as a valid start element. The bits of the incoming telegraph signal are derived from the line condition and applied after the start element via the register IP to bit 8 of the register B.

Following the start element the five bits of the telegraph character are shifted into the register B and when the start element has reached the fourth stage of the register B the last code element will be detected. The bits as they reach the fourth stage of the register B are transferred to the eighth stage of the register A to form the regenerated output. The algorithm which performs this function is repeated once in each time slot for the signals allocated to that time slot, so that each element of an incoming telegraph code is available to be sampled 16 times but is sampled only once substantially at the middle of the element when a carry is produced from the counter formed by the lower four stages of the register A. The algorithm also includes a test for a valid stop element which identifies the code group as a character and not some spurious signal on the line.

The intermediate states attained after each execution of the algorithm are stored in the RAM 12 until the same time slot in the next frame.

The send character algorithm performed by unit 102 uses registers A and B in conjunction with a particular clock signal to send a word stored in the register B into a serial telegraph character complete with start and stop elements. This algorithm and that for receiving a character can be arranged to work with five or eight code elements as required.

The operation of the algorithm is such that the stop element is sent initially and is followed by the start element and rhe code elements for the character. It will be appreciated that the stop element really belongs to the character preceding the particular character in question.

The serial telegraph character is transferred to the access units via register OP or OQ.

During the send character algorithm the lower four stages of the register A are operated as a counter and carries from this counter are used to shift data stored in the register B. The five bits representing a telegraph character are stored in the register B, and as they are shifted out under the control of the counter they are firstly stored in the eighth stage of the register A and transferred from there to the output register OP. The rate of output of the bits corresponds to the serial rate of the elements of a telegraph character. The outgoing character starts with a stop element and is followed by the start and the code elements. It will be appreciated that a stop element will always precede a start element in any sequence of characters, so sending a stop element first will not cause any difficulty. The algorithm is repeated for each time slot once in every frame and the states attained by the registers A and B are transferred into the RAM 12 at the end of each time slot to be read out ready for the next repetition of the algorithm fifteen time slots later.

The aetect clear call algorithm which is executed by the unit 103 is an instruction which is used to detect the standard signals which are used to indicate that a telegraph or telex call should be cleared down. The standard signal is derived from the bits 7 and 8 of the register IP.

The detect call clear algorithm uses only the upper four stages of the register A and operates the stages as two separate tw instructions and mini programs.

Normal instructions are performed by the CPU in a single clock cycle which occupies 500 ns, so that each program part (time slot) could contain about 120 such instructions, which would be followed by a STOP instruction. Most instructions fall into this category.

Assume that the previous instruction has been performed and that the decode latch D contains the new instruction while the program counter PC is now addressing the next instruction.

The contents of D will be decoded by the gates and read-only memories in the decoder which will in turn set the highway H and two enablers.

The selected data propagates along the H highway to its destination.

Meanwhile the output of PC will have propagated to the program memory (ROM 13), and the addressed instruction will have propagated back via instruction data highway ID to the inputs of D. At this time, about 400 ns from the previous clock pulse, all the conditions in the CPU are stable. Thus when the next clock pulse occurs three events take place simultaneously: (1) The data will be loaded into its destination, hence completing the instruction.

(2) The decode latch D will be loaded with the next instruction.

(3) The program counter will increment so as to address a further instruction.

Thus the cycle is complete.

Two-cycle instructions are instructions which include extracting the next word from the program memory but do not treat it as an instruction but transfer it to a selected destination, for example, one of the registers or the random access memory 12. These instructions occupy 1 sus.

Assume that D contains the two-cycle instruction and that the PC is addressing the next word in the program memory. This word will propagate from the program memory, via ID highway, past the decode latch, onto highway H and so on to the selected destination.

The gates in the two-cycle control, enabled by the decoded instruction, act to inhibit the clock input of D and to prepare the twocycle control latch 111 to set. Thus when the clock pulse occurs: the data from the program memory is loaded into the selected destination thus performing the instruction; the two-cycle control latch 111 sets; the program counter PC increments to address the next instruction; the decode latch D does not load as the data at its input was not to be used as an instruction.

The fact that the two-cycle control latch has set causes the following to occur: two 16 output decoders are disabled, thus preventing the instruction from being repeated; the two cycle control latch 111 is prepared to reset; and the inhibit on the dock input of D is removed.

Thus at the next clock pulse: the twocycle control latch is reset; D is loaded with the new instruction; and the program counter increments.

Thus the two cycles are complete.

Mini programs are instructions which take between three and eighteen clock cycles (1.5 to 9 "us) to perform. The first and last cycles perform no useful operations other than starting and ending a mini program. The intermediate cycles perform instructions under an address control from the mini program counter MPC, the instructions themselves being stored in the mini program ROM 110, which are transferred via the switch Z into the decode latch D for execution in the normal way.

A two-cycle control latch 111 and a mini program control latch 112 are provided to operate the various gates required by the different mode of operation of these special instructions from that of a normal single cycle instruction.

Timing within the central processing unit is controlled in response to nine different clock pulse signals termed CP 1 to CP9 derived by dividing down the output of an 8 MHz crystal oscillator 113. The clock signal dividers are included in a unit 114 and the clock signals are distributed by a distributor 115.

An interrupt control 116 receives certain of the clock pulses as specified below and is connected to the instruction decoder 107.

The nine clock pulses are as follows: CP1 is a pulse of 125 ns duration which occurs every 500 ns. This pulse is used as the main clock signal of the CPU and is buffered and distributed for use throughout the unit.

CP2 is a pulse of 500 ns duration synchronised with the trailing edge of CP1 as are all other clock pulses. This pulse occurs every 62.5 s in the example of the invention being considered, but could in other examples be arranged to occur at different intervals up to, for example, 128 Fs. CP2 is used to synchronise the time slots used in the exchange and referred to above.

CP3 and CP4 are both pulses of 500 ns duration and both occur at intervals of 62.5 s and are used by the interrupt control 116.

CP4 immediately precedes CP3, which in turn immediately precedes CP2.

CPS is a pulse having a duration of one cycle of CP2, that is to say 62.5 slS in the present example, and occurs every preset number of CP2 cycles, in the present example 20, and so occurs every 1.25 ms. In other examples GP5 can be arranged to occur at every even number of CP2 cycles up to 32.

The pulse is synchronised by the trailing edge of CP2 and it will be appreciated that the period of CP5 is 1/16th of the element time of the telegraph character, 20 ms.

CP6 is a pulse which has a duration of one cycle of CP5 and occurs every eight cycles of CP5. It is synchronised by the trailing edge of CP5 and is used by the send character algorithm.

CP7 is a pulse that occurs every preset number of cycles of CP6, in the present example 20 but it can be strapped to 40 or 80. The duration of the pulse is one cycle of CPS and is in phase with CP6. It is used in the detect call clear algorithm and as a general prdgram timing signal.

CP8 is a pulse that occurs every preset number of cycles of CP7, typically 300, but it can also be strapped to 150 or 30 cycles.

The duration of the pulse is one cycle of GPS and it is in phase with CP6. CP8 is used in the detect call clear algorithm.

CP9 is a square wave with a period of 3000 cycles of CP6, that is to say 30 seconds.

It is used in the automatic recovery from transient fault mechanism of the CPU which includes the recovery of lost ports.

The functions of CP1, CP2 and CP5 will be evident from their timing, bearing in mind the structure of a telegraph character and the way in which it is handled as illustrated in Figure 1. The uses of the other clock pulses will be evident where they are required in explaining the operation of various parts of the exchange.

As shown in Figure 2, the CPU 11 is connected to access units 15 to 18 to provide a number of ports to the exchange and as outlined above it is possible for the stored status recorded in an access unit to indicate that a port is busy, although in fact it is not allocated to any time slot. If this process were unchecked the port would be irretrievably lost to the exchange because the CPU would be inhibited from receiving signals from the port or applying signals to it. Moreover, over a period of time the effect would be cumulative so that in the end the exchange would have no usable ports at all. In order to prevent this happening the l or 0 state of the clock pulse CP9 is stored as one digit of the status of a port each time the CPU interrogates the port or applies signals to the port. Clearly, if a port is not being interrogated regularly by the CPU the state of CP9 will not be updated.

The digit representing the stored state of CP9 is compared with the current state of this clock pulse, and if they are found to differ this indicates that the port is not being interrogated by the CPU at regular intervals. This check cannot be used during the transition times of the clock pulse CP9 and gates are provided to avoid problems which would occur at these transition times.

As described above the CPU performs operations in groups during time slots of 62.5 ss. Each operation during the time slots occupies one or more units of 500 ns duration, this being the cycle time of CP1. At the end of each time slot an interrupt sequence is started in response to C1)4 in order to check that the program is operated correctly and to reset it if it is not. The programs are written so that the CPU reaches a stop instruction before the end of each time slot so that if an invalid program sequence is followed, then a stop instruction will not be found when CP4 occurs. If this happens the values in the PP and PC registers are replaced by zero so that the time slot concerned is forced to restart the program. The normal interrupt sequence arranges for the values in the registers PP and PC to be recorded in the appropriate part of the RAM 12 and causes the transfer to the registers PP and PC of the values from the RAM 12 relating to the next time slot to be operated on. When the changeover has been effected the operation is begun again so that the new time slot data can be processed. The operations for effecting this changeover are recorded as mini program number zero, which is brought into use in response to the detection of the stop instruction by CP4.

The broadcast unit 14 consists mainly of a read-only memory in which is stored the numbers of - the lines which belong to particular groups for receiving broadcasts. For example, if group 1 consists of all of the lines of the system, then the use of this read-only memory will enable a caller to specify a broadcast to group 1 rather than having to indicate the numbers of all of the line units. Other groups would of course include fewer line numbers.

The broadcast unit also checks to ensure that the class of service allocated to the calling line includes the broadcast facility; otherwise it will not respond to an instruction requesting a broadcast. If all of the line numbers belonging to a requested group for a broadcast are not free at the time, then the broadcast unit will cause the central processor to emit a busy signal until all of the lines of the particular group are free. As an alternative, it would be possible for the broadcast unit to be provided with storage means for a brief message which could be relayed to lines which are not free indicating that a broadcast message from a particular line is available for them. Another alternative would be to provide a store for the entire message, although this would be relatively expensive.

Figure 4 shows in block diagrammatic form one example of an access unit such as is indicated by reference 15, 16, 17 and 18 in Figure 2. For convenience of illustration the access unit shown in Figure 4 has facilities for connection to four line units, whereas only two line units are shown connected to each access unit in Figure 2 and, as mentioned above, one practical embodiment of the invention uses access units with facilities for connection to six line units. All of the access units are connected by a common highway to the central processing unit and these connections will become evident from the description of Figure 4, being all connections other than those connected to the line units.

Referring now to Figure 4, the access unit shown includes four bit stores, each allocated to a respective line unit. The stores have the references 201 to 204 and are connected respectively to line units L1, L2, L3 and L4.

Data input conductors 199 and 200 are connected to each store. An address decode logic unit 205 has a group of input conductors 206 via which address information is received from the CPU 11. The unit 205 has six output conductors which are connected to the stores 201 to 204, of which conductors 207 and 208 are connected to all of the stores 201 to 204, a conductor 209 is connected to the store 201, a conductor 210 to the store 20, a conductor 211 to the store 203 and a conductor 212 to the store 204. The unit 205 has three other output conductors 213, 214 and 215 which are connected to other units in the access unit. The access unit in cludes a 64 bit random access memory 216 which serves as a status store able to store sixteen 4 - bit words, each word representing the status of a respective one of the line units L1 to L4. The address information for the status store 216 is obtained via the conductors 213, 214 and 215. Two selectors 217 and 218 are provided, which also receive their address information via the conductors 213, 214 and 215. Each of the selectors 217 and 218 has twelve input conductors divided into two groups of six of which four from each group are used. Of the selector 217 inputs Al to A4 and B1 to B4 are connected respectively to two output conductors of the line units L1 to L4. Similarly, inputs C1 to C4 and D1 to D4 of the selector 218 are connected respectively to two outputs of the line units L1 to L4. The manner of the con nection is that the output connections of the line unit L1 are connected to the conductors Al, B1, C1 and D1 of the selectors 217 and 218. The selector 217 has a single output conductor 219 and the selector 218 has a single conductor 220. The conductors 219 and 220 are connected to the CPU 11. Two further selectors 221 and 222 of similar construction to the selectors 217 and 218 are provided, these selectors also being addressed by signals applied over the conductors 213, 214 and 215. The selectors 221 and 222 provide over conductors 223 and 224 respectively the class of service and class of traffic codes for the line units L1 to L4. This coded information is derived from switched inputs applied to the various input connections of the selectors 221 and 222.

In the operation of the access units shown in Figure 4, the CPU 11 applies over the conductors 206 address signals identifying a line unit. These address signals cause the status store 216 to produce a 4 bit output signal representing the status of the address line unit which, as mentioned above, would indicate whether the line unit is busy or free and will include the state of CP9 indicating whether the line unit has been used recently by the CPU 11. Assuming that the CPU 11 wishes to transmit data to, for example, the line unit L1 and that this line unit is free to receive signals, then the CPU 11 updates the status store 216 changing the status of the line unit L1 to busy. The data from the CPU 11 is applied to the store 201 which is selected by an address signal over the conductor 209 via the conductors 199 and 200. The data signals from the CPU 11 take the form of two bits on each of the conductors 199 and 200 in serial from and these are routed to the four output conductors of the store 201 under the control of signals on conductors 207 and 208, a signal on the conductor 207 occurring during the first bits on conductors 199 and 200 and a signal on the conductors 208 occurring during the second such bits.

If, however, the CPU 11 is to receive signals from the line unit L1, these would be received via conductors Al, B2, C1 and D1 as inputs to the selectors 217 and 218 and will be transmitted to the CPU 11 as serial bit pairs on the conductors 219 and 220. As the telegraph signals from the line units are of relatively long duration no storage is necessary in the access unit for the incoming signals, the duration of the pulses being sufficient to allow the selectors 217 and 218 to select the bit repairs in sequence and transmit them along the conductors 219 and 220.

It will be appreciated that the exchange described is only one possible example of the use of a digital computer according to the invention. Moreover, apart from possible changes to the computer, in the exchange changes can be made in, for example, the digit rate of the telegraph signals, the number of line and access units provided, the capacity of the random access and read only memories and the details of the facilities provided by the various units. In addition, the computer could be arranged to perform other function algorithms as single functions by the provision of special logical units. Furthermore, the exchange need not include all of the facilities described above but may be constructed more simply so as to provide an exchange having less flexibility but at a lower cost.

WHAT WE CLAIM IS: 1. A method of testing a digital computer in which instructions forming a program of the computer are divided into groups each followed by a stop instruction, so that during the normal running of the program a group of instructions is started at the beginning of

**WARNING** end of DESC field may overlap start of CLMS **.

Claims (22)

**WARNING** start of CLMS field may overlap end of DESC **. units are connected by a common highway to the central processing unit and these connections will become evident from the description of Figure 4, being all connections other than those connected to the line units. Referring now to Figure 4, the access unit shown includes four bit stores, each allocated to a respective line unit. The stores have the references 201 to 204 and are connected respectively to line units L1, L2, L3 and L4. Data input conductors 199 and 200 are connected to each store. An address decode logic unit 205 has a group of input conductors 206 via which address information is received from the CPU 11. The unit 205 has six output conductors which are connected to the stores 201 to 204, of which conductors 207 and 208 are connected to all of the stores 201 to 204, a conductor 209 is connected to the store 201, a conductor 210 to the store 20, a conductor 211 to the store 203 and a conductor 212 to the store 204. The unit 205 has three other output conductors 213, 214 and 215 which are connected to other units in the access unit. The access unit in cludes a 64 bit random access memory 216 which serves as a status store able to store sixteen 4 - bit words, each word representing the status of a respective one of the line units L1 to L4. The address information for the status store 216 is obtained via the conductors 213, 214 and 215. Two selectors 217 and 218 are provided, which also receive their address information via the conductors 213, 214 and 215. Each of the selectors 217 and 218 has twelve input conductors divided into two groups of six of which four from each group are used. Of the selector 217 inputs Al to A4 and B1 to B4 are connected respectively to two output conductors of the line units L1 to L4. Similarly, inputs C1 to C4 and D1 to D4 of the selector 218 are connected respectively to two outputs of the line units L1 to L4. The manner of the con nection is that the output connections of the line unit L1 are connected to the conductors Al, B1, C1 and D1 of the selectors 217 and 218. The selector 217 has a single output conductor 219 and the selector 218 has a single conductor 220. The conductors 219 and 220 are connected to the CPU 11. Two further selectors 221 and 222 of similar construction to the selectors 217 and 218 are provided, these selectors also being addressed by signals applied over the conductors 213, 214 and 215. The selectors 221 and 222 provide over conductors 223 and 224 respectively the class of service and class of traffic codes for the line units L1 to L4. This coded information is derived from switched inputs applied to the various input connections of the selectors 221 and 222. In the operation of the access units shown in Figure 4, the CPU 11 applies over the conductors 206 address signals identifying a line unit. These address signals cause the status store 216 to produce a 4 bit output signal representing the status of the address line unit which, as mentioned above, would indicate whether the line unit is busy or free and will include the state of CP9 indicating whether the line unit has been used recently by the CPU 11. Assuming that the CPU 11 wishes to transmit data to, for example, the line unit L1 and that this line unit is free to receive signals, then the CPU 11 updates the status store 216 changing the status of the line unit L1 to busy. The data from the CPU 11 is applied to the store 201 which is selected by an address signal over the conductor 209 via the conductors 199 and 200. The data signals from the CPU 11 take the form of two bits on each of the conductors 199 and 200 in serial from and these are routed to the four output conductors of the store 201 under the control of signals on conductors 207 and 208, a signal on the conductor 207 occurring during the first bits on conductors 199 and 200 and a signal on the conductors 208 occurring during the second such bits. If, however, the CPU 11 is to receive signals from the line unit L1, these would be received via conductors Al, B2, C1 and D1 as inputs to the selectors 217 and 218 and will be transmitted to the CPU 11 as serial bit pairs on the conductors 219 and 220. As the telegraph signals from the line units are of relatively long duration no storage is necessary in the access unit for the incoming signals, the duration of the pulses being sufficient to allow the selectors 217 and 218 to select the bit repairs in sequence and transmit them along the conductors 219 and 220. It will be appreciated that the exchange described is only one possible example of the use of a digital computer according to the invention. Moreover, apart from possible changes to the computer, in the exchange changes can be made in, for example, the digit rate of the telegraph signals, the number of line and access units provided, the capacity of the random access and read only memories and the details of the facilities provided by the various units. In addition, the computer could be arranged to perform other function algorithms as single functions by the provision of special logical units. Furthermore, the exchange need not include all of the facilities described above but may be constructed more simply so as to provide an exchange having less flexibility but at a lower cost. WHAT WE CLAIM IS:

1. A method of testing a digital computer in which instructions forming a program of the computer are divided into groups each followed by a stop instruction, so that during the normal running of the program a group of instructions is started at the beginning of

a time period allocated to that group and the stop instruction will have been reached before the end of that time period, and therefore the program is stopped for a brief interval at the end of each such time period, and, for each group of instructions, at the end of the time period allocated to the particular group of instructions, a test is made to ascertain whether the program has been stopped.

2. A method according to claim 1 wherein the computer is arranged so that if the test reveals that the program has not been stopped by the end of the time period the program is stopped and restarted so that at least the particular group of instructions is performed again.

3. A method according to claim 2 wherein if the program has not been stopped by the end of the time period the entire program is performed again from the beginning.

4. A method according to claim 1, 2 or 3 wherein the same time period is allocated to the performance of at least a plurality of the groups of instructions.

5. A method of testing a digital computer substantially as described herein with reference to the accompanying drawings.

6. A digital computer including means for storing a program including a plurality of instructions, means for selecting the instructions sequentially, means for decoding the selected instructions, means for executing the decoded instructions, timing means for controlling the selection and execution of the instructions and means for detecting a stop instruction when selected by the selecting means, wherein the instructions are divided into groups each of which is started at the beginning of a respective allocated time period and is terminated by a stop instruction, and testing means is provided responsive to the timing means for ascertaining for each group of instructions whether the stop instruction has been reached before the end of the time period allocated to the performance of the particular group of instructions.

7. A computer according to claim 6 including means for causing the selecting means to return to a datum instruction if the stop instruction has not been reached before the end of the time period.

8. A computer according to claim 7 in which the selecting means includes an instruction counter which is set to zero if the stop instruction has not been reached before the end of the time period.

9. A computer according to claim 6, 7 or 8 in which the same time period is allocated to the performance of at least a plurality of groups of instructions.

10. A digital computer substantially as described herein with reference to Figure 3 of the accompanying drawings.

11. An automatic telegraph exchange having a plurality of ports for connection to respective lines leading to other telegraph apparatus, at least one access unit connected to the ports and a digital computer according to any of claims 6 to 10 connected to the or each access unit, the digital computer including means for receiving and storing instructions obtained from telegraph data and means for sending control signals to the or each access unit to regulate the transfer of telegraph data between the access unit and the digital computer, wherein the digital computer is arranged to form independent virtual interconnection paths between the ports defined by instructions stored by the storing means and which are serviced in sequence a plurality of times within the duration of each digit of the telegraph data.

12. An exchange according to claim 11 wherein the digital computer includes means for sampling each digit of the telegraph data for a short period compared with the duration of the telegraph digit interval.

13. An exchange according to claim 12 wherein the short period is located at the middle of the telegraph digit interval.

14. An exchange according to claim 13 wherein the telegraph digit interval is 20 ms and the sampling period is 62.5 ,as.

15. An exchange according to claim 13 or 14 wherein the digital computer is arranged to cause the sampling means to sample the telegraph digit intervals at a succession of adjacent sampling periods, the computer being arranged to identify the sampling periods in which the digit is positive and those in which it is negative and to determine therefrom the timing of the central sampling periods in the digit intervals.

16. An exchange according to any of claims 11 to 15 wherein the digital computer includes a broadcasting facility by means of which an incoming message can be transmitted to a plurality of lines as specified by a caller, the facility including a store for representation of the identities of lines to which the message is to be broadcast.

17. An exchange according to claim 16 wherein the facility includes storage means for the message to be broadcast, and means for transmitting a message stored in the storage means to at least one line a representation of the identity of which is stored in the store.

18. An exchange according to any of claims 11 to 17 wherein the or each access unit includes a status store for recording which of the lines connected to the particular access unit is free and which busy, means being provided for updating the status store when a change occurs in the status of any of the lines of the particular access unit.

19. An exchange according to claim 18 wherein the digital computer is arranged to test whether it is handling signals for any line indicated in the status store as being busy.

20. An exchange according to claim 19 wherein the digital computer is arranged to generate a predetermined condition for a period of time, e.g. 30 seconds, when it is accessed to handle data from a line, to compare the presence or absence of the condition with the status of the particular line indicated by the status store, and to change the stored status from busy to free if the condition is absent.

21. An exchange according to any preceding claim wherein the or each access unit includes storage means for storing for each line connected to the access unit the class of service allocated to the particular line and/or the class of traffic which the particular line provides.

22. An automatic telegraph exchange substantially as herein described with reference to the accompanying drawings.