GB1598026A

GB1598026A - Scanning processes and apparatus

Info

Publication number: GB1598026A
Application number: GB1885778A
Authority: GB
Original assignee: Ricoh Co Ltd
Current assignee: Ricoh Co Ltd
Priority date: 1977-05-16
Filing date: 1978-05-11
Publication date: 1981-09-16
Also published as: DE2821240A1; FR2391513B1; FR2391513A1; JPS53141520A; DE2821240C2

Description

(54) IMPROVEMENTS IN AND RELATING TO SCANNING PROCESSES AND APPARATUS (71) We, RICOH COMPANY, LTD., a Japanese Body Corporate of 3-6, l-chome Naka Magome, Ohta-ku, Tokyo, Japan, do hereby declare the invention, for which we pray that a patent may be granted us, and the method by which it is to be performed, to be particularly described in and by the following statement: The invention relates to optoelectronic scanning processes and apparatus, for facsimile systems for example.

According to the invention, there is provided an optoelectronic scanning process comprising the steps of focusing a light image onto a photosensor array having a plurality of photosensor elements, sequentially scanning all of the elements at a constant speed once during each one of a succession of constant time periods of duration A to produce a succession of output signal trains, gating the output signal trains for a period A once during each of a plurality of successive time intervals of duration KA and selecting the value of K to be an integer accordto a desired signal transmission rate.

According to the invention, there is further provided an optoelectronic scanning apparatus, comprising a photosensor array having a plurality of photosensor elements, optical means for focussing a light image onto the array, scanning means for scanning the array by sequentially scanning all of the elements at a constant speed once during a constant time period of duration A and continuously scanning the array during consecutive time periods of length A to produce a succession of output signal trains, gate means for gating the output signal trains for a period ofduration A once during each of a plurality of successive time periods of duration KA, where K is an integer, and means for varying the value of K.

According to the invention, there is yet further provided optoelectrical scanning apparatus, comprising an array of photosensitive elements, scanning means for scanning the array at a constant rate during each of a succession of scanning periods of equal duration to produce a succession of pulse trains to be fed to an output terminal, and means for inhibiting one or more pulse trains at the output terminal, and means for inhibiting one or more pulse trains at the output terminal at regular intervals in accordance with a desired signal transmission rate.

Scanning apparatus and processes embodying the invention will now be described, by way of example, with reference to the accompanyine diagrammatic drawings, in which: Figure 1 is a block diagram of the variable speed optoelectronic scanning apparatus embodying the present invention; Figure 2 is a timing diagram of the present apparatus; Figure 3 is a more detailed electronic schematic diagram of part of the present apparatus; and Figure 4 is a timing diagram of the circuitry shown in Figure 3.

Referring now to the various figures of drawing, a variable speed optoelectronic scanning apparatus embodying the present invention is generally designated by the reference numeral 11 and comprises two lamps 12 and 13 for illuminating a linear portion of an original document 14. The document 14 is moved face down over a transparent platen (not shown) by means of a sub scan drive motor 16 and a feed roller 17 in increments perpendicular to the illuminated linear portion thereof. A plane mirror 18 disposed below the document 14 reflects a light image of the linear portion through a converging lens 19 which focusses the light image via a plane mirror 21 and slit 22 onto a solid state linear photosensor array 23. Although not shown in detail, the array 23 comprises a plurality, such as 1728, photosensor elements arranged in a row. A main scan drive unit 24 scans the elements in sequence to thereby scan the light image on the array 23. Each time the array 23 is scanned, the subscan drive motor 16 moves the document 14 by one increment. Thus, the main or horizontal scan is accomplished by electronically scanning the array 23 and sub scan or vertical scan is accomplished by incrementally moving the document 14.

The output signals of the array 23 are collectively designated as D' and are fed through the drive unit 24 to an input of a comparator 26. The output signals D' are analog and correspond in level to incident light intensity. Also, the output signal levels are generally proportional to the scanning speed per photosensor element. However, in accordance with an important feature of the present invention this scanning speed is constant and therefore the output signal levels correspond only to incident light intensity.

The levels of the signals D' are compared with a reference or quantization threshold level which is applied to another input of the comparator 26 from a quantization level signal generator unit 27. The comparator 26 produces a logically high output whenever a signal D' is above the threshold level and vice-versa.

Typically, the comparator 26 produces high output signals D corresponding to white areas of the document 14 and low output signals D corresponding to dark areas of the document 14.

The quantized (binary) signals D are applied through a gate 28 to a previously proposed latch unit 29 which samples and latches the signals D as they are serially fed to the latch unit 29 from the unit 24 during scanning and holds the signal D until the next sampling operation. The signals D are then processed in a well known manner for example by employing a compression unit 31 to reduce the transmission time and fed through a modem 32 and transmission line to a receiver (not shown) which operates on the signals to reproduce the document 14.

Clock pulses from a clock pulse generator 33 are processed by a scan pulse generator 34 to produce main scan pulses B which are fed to the main scan drive unit 24. These pulses B are applied to the array 23 to scan the individual elements in sequence. The pulses B are also applied to a frequency divider 36 which divides the frequency of the pulses B by a factor of 1744 to produce subscan pulses C. These pulses C are applied to a sub scan drive unit 37 which has an output connected to the drive motor 16.

The motor 16 is driven to move the document 14 by one increment each time a pulse C is applied thereto.

The apparatus 11 is capable of transmitting data signals at various speeds in such a manner that the main scan speed is constant and the subscan speed is varied, and for this reason comprises a pulse generator 38 which functions as a variable frequency divider and gate means as will be understood from further description.

In the example illustrated, the apparatus 11 is capable of scanning signals at speeds of V, V/2, V/3 and V/4 which correspond to periods of 5, 10, 15 and 20ms respectively. In terms of frequency, these speeds correspond to 200, 100, 66.6 and 50 scan lines per second. Although the present apparatus 11 is capable of transmitting at 200 lines per second, many older facsimile transceivers can only operate at speeds up to 50 or 100 lines per second. Thus, the present apparatus 11 is compatible with both old and new facsimile transceivers.

As best seen in Figure 2, the array 23 is continuously scanned at a constant speed during consecutive time periods of length A, where in this example A = Sms. In other words, during each period A all of the photosensor elements are scanned once to produce 1728 output signals D'. The signals B and C are applied to the generator 38 from the frequency divider 36. Depending on the selected scanning speed, the generator 38 functions to generate various gate signals in such a manner that the output signals D are gated once during consecutive respective time periods of length KA, where in this case K is an integer equal to 1, 2, 3 or 4 for the speeds V, V/2, V/3 and V/4 respectively.

At the maximum speed V (K = 1), the output signals D are latched once during each time interval A of Sms. Thus, during each 5ms time interval, all of the output signals D are latched, compressed and transmitted to the receiving facsimile unit.

At the speed V/2 (K = 2), although the array 23 is scanned twice during each consecutive time period KA = toms, the signals D are latched and transmitted only once. As is clearly illustrated in Figure 2, the signals D are latched only during every second scanning operation of the array 23.

In other words, every other scan line is skipped.

The compression unit 31 and modem 32 function to transmit each latched scan line during a time period of toms. Therefore, the transmission speed is reduced by a factor of 50%. However, it will be noted that the array 23 is always scanned at the same speed and the periods of the main scan pulses B are always the same. Thus, the output signal levels of the array 23 will be the same at all scan speeds.

In a similar manner, at the speed V/3 only the first, second or third scan line is gated.

Thus, only one scan line is gated during each time period KA = lems. At the speed V/4, every first, second, third or fourth scan line is gated and only one line is gated during a time period of KA = 20ms.

The generator 38 further produces gate signals El' to E4' depending on the selected scar speed and the signals El' to E4' are applied to the gate 28 to control the same to gate the signals D.

At the maximum speed V, a gate signal El' is produced during each consecutive time period A. These gate signals El' applied to the gate 28 cause the data signals D to be gated therethrough as indicated at D1. In other words, each scan line is gated through the gate 28.

At the speed V/2, the gate signal E2' is generated only during every second time period A. Thus, signals D are gated through the gate 28 during each time period A which is contained in each respective time period KA, or during every second time period A. At the speed V/3, signals E3' cause the signals D to be gated through the gate 28 during each third time period A, as indicated at D3. Similarly, at the speed V/4, a signal E4' is generated during each fourth time period A to gate the signals D through the gate 28 as indicated at D4.

The signals El' to E4' are also applied to a gate 39 to gate the main scan pulses B therethrough as main scan latch synchronization pulses. These pulses are designated as El to E4 and are produced in groups of 1728 pulses.

Whenever one of the signals El' to E4' is applied to the gate 39, 1728 pulses B are gated therethrough as pulse groups El to E4 to the latch unit 29 to synchronize latching of the signals Dl to D4 respectively.

Also illustrated is a gate 41 to gate the subscan pulses C to the latch unit 29 as subscan synchronization pulses Cl to C4. As best seen in Figure 2, the pulses C1 to C4 are applied to the latch unit 29 before the respective signals El to E4. The signals C1 to C4 reset the latch unit 29 in preparation for latching a new scan line.

Referring now to Figures 3 and 4, the frequency divider 36 comprises three, four-bit binary counters 51,52 and 53 connected in cascade. The numbers in parenthesis indicate the decimal numbers represented by the corresponding binary counter bits. The main scan pulses B are applied to the clock input of the counter 51. The (8) output of the counter 51 is connected to the clock input of the counter 52. The (128) output of the counter 52 is connected to the clock input of the counter 53.

The (64) and (128) outputs of the counter 52 are connected to inputs of an AND gate 54.

The (512) and (1024) outputs of the counter 53 are connected to other inputs of the AND gate 54. The AND gate 54 therefore produces a high output at the count of (1728) = (64)+ (128)+(512)+(1024), or after 1728 pulses B have been applied to the clock input of the counter 51.

The output of the AND gate 54 and the (16) output of the counter 52 are connected to inputs of an AND gate 56, the output of which is connected to the reset inputs of the counters 51,52 and 53. The output of the AND gate 56 goes high on the count of (1744) = (1728)+(l6), resetting all of the counters 51, 52 and 53. This decoding arrangement causes the counters 51,52 and 53 in combination to function as a modulo 1744 counter.

The (1), (2) and (8) outputs of the counter 51 in addition to the output of the AND gate 54 are connected to respective inputs of an AND gate 57, which produces a high output on the count of(1739) = (1728)+(8)+(2)+(l). The output of the AND gate 57 is connected to the K input of a JK flip-flop 58. The (1), (2) and (8) outputs of the counter 51 are also connected to inputs of an AND gate 59, the output of which is connected to the J input of the flip-flop 58. The (1024) output of the counter 53 is connected through an inverter 61 to another input of the AND gate 59. The AND gate 59 produces a high output on the count of(1 1) = (8)+(2)+(1). The clock pulses B are applied to the clock input of the flip-flop 58.

The Q output of the flip-flop 58 constitutes a signal E when high.

The Q output of the flip-flop 58 is connected to the clock input of a flip-flop 62. The Q output of the flip-flop 62 is connected to an input of an AND gate 63. The Q output of the flipflop 62 is connected to the input of an AND gate 64 and also to an input of a NAND gate 66. The output of the NAND gate 66 is connected to the clock input of a flip-flop 67, the Q output of which is connected to an input of an AND gate 68. The Q output of the flip-flop 67 is also connected to an input of a NAND gate 69, the output of which is connected to the J and K inputs of the flip-flop 62. The J and K inputs of the flip-flop 67 are connected to a logically high voltage of +SVDC.

The Q outputs of the flip-flops 58 and 67 are connected to inputs of a NAND gate 71, the output of which is connected to an input of the NAND gate 66. The Q output of the flip-flop 67 is connected to another input of the AND gate 63. The Q output of the flipflop 58 is connected to an input of an AND gate 72 and also to inputs of the AND gates 63,64 and 68.

Scan speed selection signals V, V/2, V/3 and V/4 are applied to inputs of the AND gates 72, 64, 68 and 63 respectively. The V/3 signal is applied to inputs of the NAND gates 69 and 71. The outputs of all of the AND gates 63, 64, 68 and 72 are connected to inputs of an OR gate 73, the output of which is connected to an input of an AND gate 74. The pulses B are applied to another input of the AND gate 74. The output of the OR gate 73 is also connected to inputs of the gates 28 and 39. The output of the AND gate 74.is connected to an input of the latch unit 29.

The (1), (2), (4) and (8) outputs of the counter 51 in addition to the output of the AND gate 54 are connected to inputs of an AND gate 76 which produces a high output on the count of(1743)= (1728)+(8)+(4)+(2)+(1).

The output of the AND gate 76 is connected to the K input of a flip-flop 77, the J input of which is connected to the (4) output of the counter 51. The pulses B are applied to the clock input of the flip-flop 77.

The Q output of the flip-flop 77 is connected to the J input of a flip-flop 78, the clock input of which is connected to receive the pulses B.

The Q output of the flip-flop 77 and the Q output of the flip-flop 78 are connected to inputs of an AND gate 79, the output of which is connected to the clock input of a flip-flop 81.

The high output of the AND gate 79 constitutes the signal C.

The Q output of the flip-flop 81 is connected to an input of an AND gate 82. The Q output of the flip-flop 81 is connected to an input of an AND gate 83 and also to an input of a NAND gate 84. The output of the NAND gate 84 is connected to the clock input of a flipflop 86, the Q output of which is connected to an input of an AND gate 87. The Q output of the flip-flop 86 is also connected to an input of a NAND gate 88, the output of which is connected to the J and K inputs of the flip-flop 81. The J and K inputs of the flip-flop 86 are connected to a logically high voltage of +SVDC.

The Q output of the flip-flop 86 and the output of the AND gate 79 are connected to inputs of a NAND gate 89, the output of which is connected to an input of the NAND gate 84.

The Q output of the flip-flop 86 is connected to another input of the AND gate 82. The output of the AND gate 79 is connected to an input of an AND gate 91 and also to inputs of the AND gates 82, 83 and 87.

The scan speed selection signals V, V/2, V/3 and V/4 are applied to inputs of the AND gates 91,83, 87 and 82 respectively. The V/3 signal is applied to inputs of the NAND gates 88 and 89.

The outputs of all of the AND gates 82,83, 87 and 91 are connected to inputs of an OR gate 92, the output of which is connected to an input of the latch unit 29.

In operation, the counters 51, 52 and 53 continuously count up to 1744 and reset in the manner described above. The flip-flop 58 is set on the count of 11 and reset on the count of 1739. Thus, the Q output of the flip-flop 58 is high for 1728 pulses B. The Q output of the flipflop 58 is designated as E and is applied to the AND gate 72 and flip-flop 62.

The flip-flops 62 and 67 in combination with their associated gates constitute a modulo 3 or 4 counter. When the V/3 signal is high, the flipflops 62 and 67 function as a modulo 3 counter.

When the V/3 signal is low, the flip-flops 62 and 67 function as a modulo 4 counter.

The scan speed is selected by making the corresponding signal V, V/2, V/3 or V/4 logically high and the other signal logically low.

Where the signal V-is high, the AND gate 72 is enabled whereas the AND gates 64, 68 and 63 are inhibited. Thus, all of the signals E are gated through the AND gate 72 and OR gate 73 as the signals El'. These signals El' are applied to the AND gate 74 to enable the same for the duration of 1728 pulses B. Thus, 1728 pulses B are gated through the AND gate 74 as the signal El for each applied signal El'.

The V/2 signal enables the AND gate 64 the other input of which is connected to the Q output of the flip-flop 62. The flip-flop62 functions as a modulo 2 counter, so that the Q output thereof is high during the first or second signal E. In other words, the flip-flop 62 divides the frequency of the signals E by a factor of 2. The output of the AND gate 64 is therefore constituted by the signals E2'.

The signals V/3 and V/4 enable the AND gates 68 and 63 respectively. For V/3 the flipflops 62 and 67 function to divide the frequency of the signals E by a factor of 3 so that the AND gate 68 produces the signal E3'. For V/4 the flip-flops 62 and 67 divide the frequenc) of the signals E by a factor of 42 and the AND gate 63 produces the signals E4 The flip-flops 77 and 78 function as a shift register. The flip-flop 77 is set by the 4th pulse and reset by the 1743rd pulse. At the time of occurrence of the 1743rd pulse the high Q output of the flip-flop 77 causes the flip-flop 78 to be set. The high Q output of the flip-flop 78 and the high Q output of the flipflop 77 cause the output of the AND gate 79 to go high. Thus, the AND gate 79 produces a high output for the duration of one pulse B.

This is the subscan pulse signal C.

The flip-flops 81 and 86 are identical in construction and operate on the signal C in the same manner that the flip-flops 62 and 67 operate on the signal E. Thus, for the signals V, V/2, V/3 and V/4 the AND gates 91, 83, 87 and 82 produce the signals C1, C2, C3 and C4 respectively.

Where 1728 pulses are required to scan the array 23, the operating cycle of the apparatus 11 is 1744 pulses. The extra 16 pulses allow time for shifting of the signals D into internal analog shift registers (not shown) in the array 23.

WHAT WE CLAIM IS: 1. An optoelectronic scanning process, comprising the steps of focusing a light image onto a photosensor array having a plurality of photosensor elements, sequentially scanning all of the elements at a constant speed once during each one of a succession of constant time periods of duration A to produce a succession of output signal trains, gating the output signal trains for a period A once during each of a plurality of successive time intervals of duration KA, and selecting the value of K to be an integer according to a desired signal transmission rate.

2. Optoelectronic scanning apparatus, comprising a photosensor array having a plurality of photosensor elements, optical means for focusing a light image onto the array, scanning means for scanning the array by sequentially scanning all of the elements at a constant speed once during a constant time period of duration A and continuously scanning the array during consecutive time periods of length A to produce a succession of output signal trains, gate means for gating the output signal trains for a period of duration A once during each of a plurality of successive time periods of duration KA, where K is an integer, and means for varying the value of K.

3. Apparatus according to claim 2, comprising a pulse generator for generating one sub scan pulse and a plurality of main scan pulses during each period of duration A and feeding them to

**WARNING** end of DESC field may overlap start of CLMS **.

Claims

**WARNING** start of CLMS field may overlap end of DESC **. output of the flip-flop 81 is connected to an input of an AND gate 83 and also to an input of a NAND gate 84. The output of the NAND gate 84 is connected to the clock input of a flipflop 86, the Q output of which is connected to an input of an AND gate 87. The Q output of the flip-flop 86 is also connected to an input of a NAND gate 88, the output of which is connected to the J and K inputs of the flip-flop 81. The J and K inputs of the flip-flop 86 are connected to a logically high voltage of +SVDC. The Q output of the flip-flop 86 and the output of the AND gate 79 are connected to inputs of a NAND gate 89, the output of which is connected to an input of the NAND gate 84. The Q output of the flip-flop 86 is connected to another input of the AND gate 82. The output of the AND gate 79 is connected to an input of an AND gate 91 and also to inputs of the AND gates 82, 83 and 87. The scan speed selection signals V, V/2, V/3 and V/4 are applied to inputs of the AND gates 91,83, 87 and 82 respectively. The V/3 signal is applied to inputs of the NAND gates 88 and 89. The outputs of all of the AND gates 82,83, 87 and 91 are connected to inputs of an OR gate 92, the output of which is connected to an input of the latch unit 29. In operation, the counters 51, 52 and 53 continuously count up to 1744 and reset in the manner described above. The flip-flop 58 is set on the count of 11 and reset on the count of 1739. Thus, the Q output of the flip-flop 58 is high for 1728 pulses B. The Q output of the flipflop 58 is designated as E and is applied to the AND gate 72 and flip-flop 62. The flip-flops 62 and 67 in combination with their associated gates constitute a modulo 3 or 4 counter. When the V/3 signal is high, the flipflops 62 and 67 function as a modulo 3 counter. When the V/3 signal is low, the flip-flops 62 and 67 function as a modulo 4 counter. The scan speed is selected by making the corresponding signal V, V/2, V/3 or V/4 logically high and the other signal logically low. Where the signal V-is high, the AND gate 72 is enabled whereas the AND gates 64, 68 and 63 are inhibited. Thus, all of the signals E are gated through the AND gate 72 and OR gate 73 as the signals El'. These signals El' are applied to the AND gate 74 to enable the same for the duration of 1728 pulses B. Thus, 1728 pulses B are gated through the AND gate 74 as the signal El for each applied signal El'. The V/2 signal enables the AND gate 64 the other input of which is connected to the Q output of the flip-flop 62. The flip-flop62 functions as a modulo 2 counter, so that the Q output thereof is high during the first or second signal E. In other words, the flip-flop 62 divides the frequency of the signals E by a factor of 2. The output of the AND gate 64 is therefore constituted by the signals E2'. The signals V/3 and V/4 enable the AND gates 68 and 63 respectively. For V/3 the flipflops 62 and 67 function to divide the frequency of the signals E by a factor of 3 so that the AND gate 68 produces the signal E3'. For V/4 the flip-flops 62 and 67 divide the frequenc) of the signals E by a factor of 42 and the AND gate 63 produces the signals E4 The flip-flops 77 and 78 function as a shift register. The flip-flop 77 is set by the 4th pulse and reset by the 1743rd pulse. At the time of occurrence of the 1743rd pulse the high Q output of the flip-flop 77 causes the flip-flop 78 to be set. The high Q output of the flip-flop 78 and the high Q output of the flipflop 77 cause the output of the AND gate 79 to go high. Thus, the AND gate 79 produces a high output for the duration of one pulse B. This is the subscan pulse signal C. The flip-flops 81 and 86 are identical in construction and operate on the signal C in the same manner that the flip-flops 62 and 67 operate on the signal E. Thus, for the signals V, V/2, V/3 and V/4 the AND gates 91, 83, 87 and 82 produce the signals C1, C2, C3 and C4 respectively. Where 1728 pulses are required to scan the array 23, the operating cycle of the apparatus 11 is 1744 pulses. The extra 16 pulses allow time for shifting of the signals D into internal analog shift registers (not shown) in the array 23. WHAT WE CLAIM IS:

1. An optoelectronic scanning process, comprising the steps of focusing a light image onto a photosensor array having a plurality of photosensor elements, sequentially scanning all of the elements at a constant speed once during each one of a succession of constant time periods of duration A to produce a succession of output signal trains, gating the output signal trains for a period A once during each of a plurality of successive time intervals of duration KA, and selecting the value of K to be an integer according to a desired signal transmission rate.

the scanning means, and wherein the gate means is arranged to gate therethrough as latch synchronization pulses one subscan pulse and a respective plurality of main scan pulses during one period of duration A in each time period of duration KA.

4. Apparatus according to claim 3, wherein the gate means comprises a variable frequency divider having means for varying the frequency division ratio by the integer K.

5. Apparatus according to claim 3, wherein the gate means is arranged to gate the output signals from the elements therethrough only when receiving the subscan and main scan pulses.

6. Optoelectrical scanning apparatus, comprising an array of photosensitive elements, scanning means for scanning the array at a constant rate during each of a succession of scanning periods of equal duration to produce a succession of pulse trains to be fed to an output terminal, and means for inhibiting one or more pulse trains at the output terminal at regular intervals in accordance with a desired signal transmission rate.

7. An optoelectrical scanning process substantially as hereinbefore described with reference to the accompanying drawing.

8. Optoelectrical scanning apparatus substantially as hereinbefore described with reference to the accompanying drawing.

9. Facsimile transmission apparatus including optoelectrical scanning apparatus according to any preceding claim.