GB1596028A

GB1596028A - Computer terminals

Info

Publication number: GB1596028A
Application number: GB5062077A
Authority: GB
Original assignee: Vickers Ltd
Current assignee: Vickers Ltd
Priority date: 1978-05-30
Filing date: 1978-05-30
Publication date: 1981-08-19

Description

(54) COMPUTER TERMINALS (71) We, VICKERS LIMITED, a British company, of Vickers House, Millbank Tower, Millbank, London, SWlP 4RA, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement: The present invention relates to computer interface circuitry.

Computer interface circuitry is employed between one computer device, for example a computer terminal, such as a VDU (video display unit) or a teleprinter, or a computer proper, and another computer device. Interface circuitry which passes data in a serial fashion, for example between a computer terminal and the computer, is currently in use.

Serial data passed between a computer and a computer terminal is commonly passed in the form of current loop signals or symmetrical modem signals. Interface circuitry for passing such data between computer and terminal is commonly designed to handle 20mA current loop signals and/or symmetrical modem signals in accordance with CCITT (The Consultative Committee International Telegraph and Telephone) standard V24 or El A (Electronic Industries Association) standard RS 232.

The interface circuitry is operable to convert received such current loop signals or modem signals into logic signals for onward delivery to the computer terminal, and is operable to convert received logic signals into current loop signals or modem signals for onward delivery to the computer.

When a number of computer terminals have been connected (multiplexed) to a computer, and data is to be passed serially between each terminal and the computer, separate input/output ports have been provided at the computer for passing data between the computer and the respective terminals. A separate interface card has been provided for each terminal, together with wiring connecting the terminal to the interface card.

This can be inconvenient since the computer will have only a finite number of input/output ports and it may be desirable to connect more terminals to the computer than there are input/output ports.

According to the present invention there is provided computer interface circuitry for use in passing serial data to and from a computer device, comprising a main input/ output circuit and an extension input/output circuit each operable to receive serial data in a predetermined signal form at a first input thereof and to pass on that data, in a respective different signal form, from a first output thereof, and to receive serial data, in the different signal form appropriate to the input/output circuit concerned, at a second input thereof and to pass on that data, in the said predetermined signal form, from a second output thereof, the first input of the main input/output circuit being connected for receiving data passed from the computer device, in the said predetermined signal form, when the circuitry is in use, and also data passed from the second output of the extension input/output circuit, and the second output of the main input/output circuit being connected for delivering data, in the said predetermined signal form, for passing to the said computer device, when the circuitry is in use, and being also connected to the first input of the extension input/output circuit.

Computer interface circuitry embodying the present invention may be used with a computer terminal, the said predetermined signal form being a logic signal form (in which definite ranges of voltages indicate definite data values, for example "1" and "0", e.g. for TTL inputs OV-0.8V is "0" and 2.4V-5V is "1" in positive logic), and the different signal forms being either current loop or modem signal forms.

The use of interface circuitry embodying the present invention can enable more than one computer device, e.g. terminal, to be connected to a signal input/output port of a computer, for example, in a "daisy-chain", so that data can be passed serially between the input/output port and each terminal connected thereto. This can increase the efficiency with which the computer is employed, especially where each terminal connected to an input/output port would itself employ only a small fraction of the capacity of the input/output port. The amount of connection wiring needed can also be reduced. Data may be passed between the interface circuitry of successive terminals of the daisy chain in current loop signal form or in modem signal form. Both signal forms may be used along the daisy-chain.

For a better understanding of the present invention, and to show how the same may be carried into effect, reference will now be made, by way of example, to the accompanying drawings, in which: Figure I is a block diagram schematically illustrating computer-computer terminal connections, Figure 2 is a block diagram schematically illustrating computer/computer terminal connection when interface circuitry embodying the present invention is employed, Figure 3 is a block diagram schematically illustrating interface circuitry embodying the present invention in a computer terminal, Figures 4 and 5 are block circuit diagrams illustrating parts of respective embodiments of the present invention, and Figure 6 is a more detailed circuit diagram corresponding to Figure 3.

Figure 1 illustrates the previously used "star"arrangement employed when connecting a number of computer terminals 7 (numbered 1 to 4) to a computer 5 where information is to be passed serially between the computer and each terminal. As can be seen, each terminal 7 is connected to a separate input/output port (numbered 1 to 4) 6 of the computer.

Figure 2 illustrates the arrangement employed for connecting the same number of computer terminals 7 to computer 5 when interface circuitry embodying the present invention is employed in respect of each of terminals 1 to 3.

It will be seen that the terminals are connected to the computer 5 by way of a single input/output port 6 in a "distributed" or "daisy chain" connection arrangement.

It will be appreciated that interface circuitry embodying the present invention could be constructed in a separate plug-in unit for attachment to a computer terminal for example. The following description, however, relates to cases in which interface circuitry embodying the present invention is built into a computer terminal.

As illustrated in Figure 3, terminal 1, for example, includes interface circuitry comprising a modem input/output circuit 8 and a current loop input/output circuit 9. The modem input/output circuit and the current loop input/output circuit are connected to the serial input and the serial output of U.A.R.T. (Universal Asynchronous Receiver/Transmitter or Asynchronous data interface) 13. The interface circuitry further comprises an additional or extension current loop input/output circuit 10.

Serial data fed in from the current loop input/output circuit 9 (main input/output circuit) is fed to the serial input of UART 13 via OR gate 12 and is also fed to the current loop extension input/output circuit 10. The OR gate 12 also receives data fed in from the modem input/output circuit 8 (auxiliary input/output circuit).

Serial output data from UART 13 is fed to the modem (auxiliary) input/output circuit 8 and, via OR gate 11, to the current loop (main) input/output circuit 9. Serial data fed in through the current loop (extension) input/output circuit 10 is also fed, via OR gate 11, to the current loop (main) input/output circuit 9.

The modem input/output circuit 8 is for transmission and reception of data signals modulated on a carrier, for example for passing along a Post Office telephone line.

The current loop input/output circuits 9 and 10 are for transmission and reception of data signals which are passed as baseband (unmodulated) currents along, for example, local data lines. Typically used is a 20 mA current loop with 20aA as "0" and OmA as "1".

From Figures 2 and 3 it will be seen that the provision of current loop extension input/output circuits 10 in each of terminals 1 to 3 will enable serial data to be passed as a current loop signals from the computer 5 to terminal 1 and hence to terminals 2. 3 and 4 in succession, and will enable data to be passed from any one of terminals 1 to 4 to the computer 5.

Current loop signals received from computer 5 at a current loop input of current loop (main) input/output circuit 9 of terminal 1, for example, are converted to logic signals and passed to UART 13 from a logic signal output of circuit 9, via OR gate 12, and also to a logic signal input of extension circuit 10 at which they are re-coverted to current loop signals for onward delivery to terminal 2 from a current loop output of circuit 10.

Current loop signals received from ter minal 2 at a current loop input of extension circuit 10 are converted to logic signals and delivered, via OR gate 11, to a logic signal input of main input/output circuit 9 at which they are reconverted to current loop signals for onward delivery to computer 5 from a current loop output of circuit 9.

Passage of data between terminals 1 to 4 is possible without the need for the data to be passed first from the sending terminal to computer 5 and then from computer to the destination terminal. Since current loop signals are converted to logic signals and back again between circuits 9 and 10 of each terminal, the signals can be regenerated with no significant loss of quality. This being so, signal degradation need not be a limiting factor on the maximum number of terminals which can be "daisy-chained". However the maximum acceptable signal propagation delay between the computer and the final terminal in a chain is a limiting factor.

It will be appreciated that embodiments of the present invention can be provided in which an extension input/output circuit operates to convert logic signals received from the main input/output circuit 9 into modem signals for onward delivery, and to convert received modem signals into logic signals for delivery to main circuit 9. Further, it will be appreciated that the main input/output circuit (e.g. circuit 9 in Figure 3) in respect of which the extension input/output circuit is provided may operate on the basis of conversion between logic and modem signals. The extension input/output circuit may operate on the basis of the same conversion as the main input/output circuit or on a different conversion basis. In each case an auxiliary input/output circuit (e.g. circuit 8 in Figure 3) operating on a conversion basis different to that of the main input/output circuit can be provided.

It will be further appreciated, for example by reference to Figure 3, that since data delivered as current loop signals from the computer 5 is delivered to the serial input of the UART 13 of each terminal in a chain, and since such data will in general be destined for only one terminal of the chain, it will almost always be necessary that the data include an address code uniquely designating the destined terminal, and that each terminal be arranged so as to accept and act upon only data addressed thereto. Each terminal will include means for carrying out decoding and detection so that it responds to address codes in the data. Such decoding and dectection may be effected by hardware or, in a programmable terminal, by software.

As shown in Figure 3, UART 13 converts received serial input data into a parallel form. This parallel data is passed to address decoder 14 which, for example, is operable to activate a transmission enable flip-flop 15 only when the received data is found to contain the address code of the terminal concerned, which flip-flop then enables transmission of data from the terminal to the computer in response to a command from the computer addressed to the terminal.

Different methods of addressing individual terminals may be employed.

Figure 4 illustrates in more detail the configuration of address decoder 14 and flip-flop 15 in accordance with a first addressing method.

In this method each terminal in a chain has a unique address code which corresponds to an ASCII (American Standard Code for Information Exchange) character.

The address decoder 14 has input terminals 21 to which respective bits of 7-bit parallel received data are passed from UART 13. Each input terminal is connected directly to an input link 18 and via an inverter 16 to an input link 17. One link from each pair of input links 17 and 18 is connected to a corresponding output link 19. Each ouput link is connected to an input of an 8-input positive NAND gate 20. The arrangement of connections between the output links and the corresponding input links defines the 7-bit received data code which is the address code of the computer terminal. The link connections illustrated in Figure 3 correspond to an address code 0408 which is the character code word for "space" in the 7-bit ASCII code.

When address code 0408 is received from UART 13 all inputs to NAND gate 20 are logical "1" and thus the output of the NAND gate is "0". This output is employed by flip-flop 15 to generate a transmission enable signal. The flip-flop 15 is dual D-type positive edge triggered flip-flop with reset and clear. The clear input Cr is set to "1".

The preset input Pr is connected to receive an inverted "initialise" signal. An initialise signal is a "high" (i.e. logical "1") signal, of a few milliseconds duration, which occurs only when the terminal is powered on. An initialise signal is normally provided for most logic circuits to ensure they start in the correct state. The clock input is connected to receive a "data available" signal. Output Q provides a transmission enable signal when its level is high ("1"). The output of NAND gate 20 is connected to input D of the flip-flop 15. When the signal supplied to the preset input is "1" and the "date available" signal rises to a "1" level, but a "1" is received from NAND gate 20, the output Q becomes "0" thereby disabling transmission. If a "0" is received from NAND gate 20 output Q becomes "1", thus enabling transmission. It will thus be seen that only when the address code set by the link connection arrangement is received can transmission be enabled. Reception of any other address code (ASCII character) will disable transmission. It will be appreciated that Figure 4 relates to a system in which, upon reception of its address code from computer 5, the computer terminal concerned is simply to transmit data held therein.

Figure 5 shows a modification of the address decoder 14 of Figure 4. The method of addressing a computer terminal offered by the arrangment of Figure 5 requires that once transmission has been enabled (by reception of the appropriate address code) a specific transmission disable code is required to terminate transmission.

AND gate 22, having two inverting inputs, is connected to receive a signal, from line 26. which is '0" when the address code set for the terminal is received, and an inverted "data available" signal from inverter 23 via line 27.

AND gate 24, having two inverting inputs, is connected to receive a signal from inverter 23 and, via line 28, a signal which is "0" when the transmission disable code is received.

NOR gate 25 receives the output signal from AND gate 24 and an "initialise" signal which is normally i'0" (see above).

In this case the transmission enable signal is derived from the Q output of flip-flop 15.

The Q output provides a "1" output, to enable transmission when the address code appropriate to the terminal concerned is received, and provides a "0" output to disenable trasmission when the appropriate transmission disable code is received.

The preset and D inputs of the flip-flop are set at "1", and the outputs of gates 22 and 25 are connected to the clock and clear inputs of the flip-flop respectively.

The pulses shown adjacent signal lines in Figure 5 illustrate the situation in which the transmission disable code is received and transmission is disabled.

It should be noted that the numerals (e.g.

02, 04. 74. 30) shown within the various gates etc. of Figures 4 and 5 indicate device numbers of devices in the 54/74 familv of SSI TTL circuits (manufactured by Texas Instruments for example) on which the gates etc. are provided. UART 13 in Figure 3 may be MOS LSI Device No. TMS 6011 manufactured by Texas Instruments Limited, or General Instrument AY-5-1013.

If a microprocessor-based or other programmable terminal is used, the address functions will normally be performed by software. In this case, the interface circuitry will remain unchanged, but address decoding and detection circuits will not be needed. An address decode portion of the terminal's program will compare any address it receives with its own terminal address. If it is different, the program will branch to a mode where it is waiting for the next address. If the address is correct, it will branch to its internal data transfer application program, whilst checking for the arrival of another address to disable data transmission.

Interface circuitry embodying the present invention can be applied to barcode reader terminals. Such barcode reader terminals are low speed terminals and by providing interface circuitry embodying the present invention in each terminal of a chain of barcode reader terminals (except, prossibly, the last) a relatively large number of terminals can be connected to a single computer input/output port, thereby providing for more efficient and cost effective computer usage than if individually ports were provided for each terminal.

The terminals of such a chain may be polled in turn (and data read out therefrom) by the sending of a string of ASCII character codes from the computer to address the terminals in turn.

The number of ASCII codes, for example, which are available for use (i.e. are not used for other purposes) as address codes may limit the maximum number of terminals which can be connected in a chain.

Figure 6 shows in detail parts of serial interface circuitry embodying the present invention that can be employed in a barcode reader terminal. The circuitry shown in Figure 6 corresponds in general to that of Figure 3;input/output circuit 3.

Modem input/output circuit 8 comprises Modem input circuit 81, composed of Mullard IC's Signetics Dual communications EIA/MIL Receiver with Hysteresis 8T16, and ancilliary components such as 10V zener diodes BZX61 (Phillips), and modem output circuit 82, composed of Mullard IC's Signetics Duel Communications EIA/MIL Line Driver 8T15 and ancilliary components.

Current loop input/output circuit 9, comprises current loop input circuit 91, composed of an optical isolator (Motorola 4N33) with a photodiode and a photodarlington, and ancilliary components, and current loop output circuit 92, also composed of an optical isolator 4N33 and ancilliary components such as silicon rectifier IN 4001 (ITT semiconductors). Receiver 8T16 and line driver 8T15 conform to EIA standard RS232.

The current loop extension input/output circuit comprises an input circuit 10 and an output circuit 102, both utilising optical isolators.

The input/output circuits are connected to one another and to UART 13 via a number of gates in the manner illustrated.

The utilisation of optical isolators in the current loop input/output circuits ensures that in a chain of terminals each section of current loop is isolated from the others.

WHAT WE CLAIM IS: 1. Computer interface circuitry for use in passing serial data to and from a computer device, comprising a main input/output circuit and an extension input/output circuit each operable to receive serial data in a predetermined signal form at a first input thereof and to pass on that data, in a respective different signal form, from a first output thereof, and to receive serial data, in the different signal form appropriate to the input/output circuit concerned, at a second input thereof and to pass on that data, in the said predetermined signal form, from a second output thereof, the first input of the main input/output circuit being connected for receiving data passed from the computer device, in the said predetermined signal form, when the circuitry is in use, and also data passed from the second output of the extension input/output circuit, and the second output of the main input/output circuit being connected for delivering data, in the said predetermined signal form, for passing to the said computer device, when the circuitry is in use, and being also connected to the first input of the extension input/output circuit.

2. Circuitry as claimed in claim 1, wherein the predetermined signal form is a logic signal form, and the different signal form is, for both the main and extension input/output circuits. a current loop signal form.

3. Circuitry as claimed in claim 1, wherein the predetermined signal form is a logic signal form, and the said different form is. for both the main and extension input output circuits, a modem signal form.

4. Circuitry as claimed in claim 1, wherein the predetermined signal form is a logic signal form. and the different signal form for one of the main and extension input/output circuits is a modem signal form. whilst the different signal form for the other of the main and extension input/ output circuits is a current loop signal form.

5. Circuitry as claimed in claim 1, 2, 3, or 4. further comprising an auxiliary input/ output circuit operable to receive serial data. in the said predetermined signal form, at a first input thereof, and to pass on that data, in a different signal form, from a first output thereof, and to receive serial data, in the different signal form appropriate to the auxiliary input/output circuit, at a second input thereof and to pass on the data, in the said predetermined signal form, from a second output thereof, the first input of the auxiliary input/output circuit being connected in common with the first input of the main input/output circuit for receiving data, passed from the said computer device, in the said predetermined signal form, when the circuitry is in use, and the said second output of the auxiliary input/output circuit being connected in common with the said second output of the main input/output circuit for delivering data in the said predetermined signal form, for passing to the said computer device, when the circuitry is in use.

6. Circuitry as claimed in claim 5, read as appended to claim 2, wherein the different signal form for the auxiliary input/ output circuit is a modem signal form.

7. Circuitry as claimed in claim 5, read as appended to claim 3, wherein the different signal form for the auxiliary input/ output circuit is a current loop signal form.

8. Circuitry as claimed in claim 5, read as appended to claim 4, wherein the different signal form for the auxiliary input output circuit is the same as the different signal form for the extension input/output circuit.

9. Circuitry as claimed in claim 2, 4, 6, 7 or 8, wherein the or each input/output circuit for which the different signal form is a current loop signal form employs optical isolators for isolating signals applied to the inputs of the circuit from signals supplied from the outputs of the circuit.

10. Circuitry as claimed in any preceding claim, further comprising address detection means operable to detect, in data the passing to the computer device, an address identifying the computer device as a destination for the data.

11. Circuitry as claimed in claim 10, comprising a universal asynchronous receiver/transmitter operable to convert data passed from the computer device in parallel form into serial data, in the said predetermined signal form, for passage to the first input of the main input/output circuit, and to convert serial data delivered from the second output of the main input/output circuit in the said predetermined signal form into parallel data, for passing to the computer device.

12. Circuitry as claimed in claim 11, wherein the address detection means are operable to detect the address in the parallel data by comparing a plurality of data bits to be passed in parallel to the computer device with a predetermined address for the device.

13. Circuitry as claimed in any preceding claim, in operative combination with the computer device.

14. Circuitry as claimed in claim 13, wherein the computer device is a bar-code reader terminal.

15. A computer system, including a main computer and a plurality of computer

**WARNING** end of DESC field may overlap start of CLMS **.

Claims

**WARNING** start of CLMS field may overlap end of DESC **. The utilisation of optical isolators in the current loop input/output circuits ensures that in a chain of terminals each section of current loop is isolated from the others. WHAT WE CLAIM IS:

1. Computer interface circuitry for use in passing serial data to and from a computer device, comprising a main input/output circuit and an extension input/output circuit each operable to receive serial data in a predetermined signal form at a first input thereof and to pass on that data, in a respective different signal form, from a first output thereof, and to receive serial data, in the different signal form appropriate to the input/output circuit concerned, at a second input thereof and to pass on that data, in the said predetermined signal form, from a second output thereof, the first input of the main input/output circuit being connected for receiving data passed from the computer device, in the said predetermined signal form, when the circuitry is in use, and also data passed from the second output of the extension input/output circuit, and the second output of the main input/output circuit being connected for delivering data, in the said predetermined signal form, for passing to the said computer device, when the circuitry is in use, and being also connected to the first input of the extension input/output circuit.

15. A computer system, including a main computer and a plurality of computer

devices each in combination with computer interface circuitry as claimed in claim 10, 11 or 12, wherein the computer devices are connected by way of the computer interface circuitry of each device, the extension input/ output circuit of one device connected to the main input/output circuit of the next device, in a daisy chain, to a single input/output port of the main computer.

16. Computer interface circuitry substantially as hereinbefore described with reference to Figure 3, or Figures 3 and 4 or Figures 3 and 5 of the accompanying drawings, or as described with reference to Figures 3 and 6, 4 and 6 or Figures 3, 5 and 6 of the accompanying drawings.