GB1595446A - Facsimile transceivers - Google Patents

Description

(54) IMPROVEMENTS IN OR RELATING TO FACSIMILE TRANSCEIVERS (71) We, RICOH COMPANY, LTD., a Japanese Body Corporate of 3-6, l-chome Naka Magome, Ohta-ku, Tokyo, Japan, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed to be particularly described in and by the following statement:- The present invention relates to facsimile transceivers.

According to the invention, there is provided a facsimile transceiver, comprising line connection means for connection to a signal transmission path and arranged to transfer signals between a common path and the signal transmission path, a plurality of units including at least a scan unit and a printing unit, each unit of said plurality being connected to said common path, each unit of said plurality of units including address receiver means and instruction receiver means, and a central control unit having address circuit means connected to each said address receiver means, and instruction circuit means connected to each said ininstruction receiver means, the control unit being operative to selectively enable the transmission of signals between the common path and the units connected to the path.

According to the invention there is further provided a facsimile transceiver, comprising a line connection unit for connection to a signal transmission path, a modem unit for modulating signals received from a common path and feeding the modulated signals to the line connection unit, and for demodulating signals received from the line connection unit and feeding the demodulated signals to the common path, a plurality of replaceable units including at least a scanning unit and printing unit connected in parallel to the common path, and a central unit operable to selectively actuate each said unit in accordance with the desired mode of operation of the transceiver.

Transceivers embodying the invention will now be described, by way of example, with reference to the accompanying diagrammatic drawings in which: Figure 1 is a block diagram of a prior art facsimile transceiver; Figure 2 is a block diagram of a facsimile transceiver embodying the present invention; Figure 3 is a more detailed block diagram of the transceiver of Figure 2; Figure 4 is a block diagram of a second embodiment of a facsimile transceiver of the present invention Figure 5 is a more detailed block diagram of the transceiver of Figure 4; and Figure 6 is a simplified diagram of an interface unit of the transceivers of Figure 3 and 5.

Referring now to Figure 1 of the drawing, a prior art facsimile transceiver is generally designated by the reference numeral 11 and comprises a line connection unit 12 for conection of the transceiver 11 to a telephone line 13. For facsimile transmission, a scanner 14 scans an original document (not shown) and produces binary electrical signals indicating the presence or absence of visual information in the respective areas of the document. These signals are fed through a central processing unit (CPU) 16 to a signal processing unit 17 which compresses the signals through run length encoding or another known compression technique to reduce the transmission time. From the unit 17, the compressed signals are fed to a modem 18 which utilizes the signals to modulate an audio carrier wave. The modulated carrier wave is fed through the line connection unit 12 and telephone line 13 to a similar transceiver (not shown) which processes the signals and reproduces the original document in response thereto.

For reception of a modulated carrier wave over the telephone line 13, the wave is fed through the line connection unit 12 to the modem 18 which demodulates the same to recover the compressed data signals.

These signals are fed to the signal processing unit 17 which expands the compressed data signals to recover the original binary signals.

These are fed to a printer 19 which produces a hard copy of the original document on a sheet of paper in response thereto. A control and display unit 21 comprises a control panel by which the transceiver operator controls the operation of the transceiver 11 and a display panel which typically comprises lights (not shown) indicating the operating status of the transceiver 11.

It will be clearly recognized that due to the series arrangement of the various units in the transceiver 11, each unit functions upon receipt of signals from the unit immediately preceding the same in the flow path of the signals. For this reason, any modification which alters the configuration of the signals in one unit necessitates modification of the adjacent units.

This problem is overcome in the facsimile transceiver 31 shown in Fig 2. which comprises a line connection unit 32, modem unit 33, signal processing unit 34, scan unit 36, printing unit 37, and control and display unit 38 which generally perform the same functions as the corresponding units in the transceiver 11. However, rather than being connected in series, these units are interconnected in parallel through a signal bus means 39. A central control unit 41 is connected to each of the units 33, 34, 36, 37 and 38 through an address bus 42, instruction bus 43 and flag bus 44. The line connection unit 32 is connected to a telephone line 46.

The signal bus means 39 may comprise a single bus of typically 4 wires or may comprise two or more busses, each of which is connected to all of the units 33, 34, 36, 37 and 38. Alternatively, the bus means 39 may comprise two or more buses, each of which is connected to two or more, but not all, of the units 33, 34, 36, 37 and 38.

The connection of the signal bus means 39 to the units 33, 34, 36, 37 and 38 may be advantageously embodied by tri-state logic, in which a particular unit may present a substantially infinite impedance to, or be effectively disconnected from the signal bus means 39 where desired. The central control unit 41 feeds an address signal designating one of the units 33, 34, 36, 37 and 38 which is required to be activated over the address bus 42. As shown in Figure 6, each of the units 33, 34, 36, 37 and 38 comprises an interface 45 having an address receiver or decoder 47, with an input connected to the address bus 42. Upon receipt of the address signal for the respective unit, the address decoder 47 produces a logically high signal on a line 51 which activates the unit to respond to an instruction on the instruction bus 43.

Each interface 45 further comprises an instruction decoder 48 connected to the instruction bus 43 which decodes an instruction signal thereon from the central control unit 41 and produces a corresponding control signal on a line 52. It will be understood that only the addressed unit will respond to the instrument signal. In response to the instruction signal, the addressed unit performs the operation represented by the instruction.

For example, the central processing unit 41 may address the modem unit 33 and feed an instruction thereto causing the modem unit 33 to operate in the modulation mode.

In order to synchronize the operation of the transceiver 31, each unit 33, 34, 36, 37 and 38 comprises a status or flag register 49 which indicates the status of the respective unit. Signals from the various parts of the respective unit are applied to the flag register 48 through a line 53. These signals represent the status of the respective unit and are stored and constantly updated in the flag register 49. By interrogating the flag register 49 of a particular unit through the flag bus 44, the central control unit 41 may determine the status of the respective unit. For example.

the central control unit 41 may address the signal processing unit 34 and feed an instruction thereto causing the same to function in the compression mode. After the compression operation is completed, the flag register of the signal processing unit 34 will indicate the same, and the central control unit 41 will feed an instruction to the signal processing unit 34 causing the same to be deactivated to a standby condition.

The address and instruction signals also cause various units to be connected together via the signal bus means 39. For example, at a certain time during reception of facsimile information, suitable addresses and instructions will be produced causing the output of the signal processing unit 34 and the input of the printing unit 37 to be connected to the signal bus means 39. Conversely, during transmission, suitable signals will be produced causing the output of the scan unit 36 and the input of the signal processing unit 34 to be connected to the signal bus means 39. Where two or more separate buses are provided in the signal bus means 39, the instruction will contain information as to which of the signal buses an addressed unit is to be connected. Typically, the address, signal and flag buses each comprises 8 lines, so that a total of 28=256 different signal combinations may be produced.

As a modification of the transceiver 31, the buses 42, 43 and 44 may be integral and the address, instruction and flag signals fed therethrough on the basis of time sharing or multiplexing. Conversely, each of the buses 42, 33 and 44 may comprise two or more bus lines, each connecting the central control unit 41 only to certain units. It will be understood that although the transceiver 31 is shown and described as communicating with another similar transceiver via a telephone line, such communication may be via radio, microwave link or the like.

Figure 3 shows the present facsimile transceiver 31 in greater detail. Although a number of internal components of the various units are shown and labeled, only those components which are relevant to an understanding of the present invention are designnated by reference numerals and described hereinbelow.

The interfaces for the units 33, 34, 36, 37 and 38, which are collectively designated as 45 in Figure 6, are designated in Figure 3 as 61, 62, 63, 64 and 66 respectively. The signal bus means 39 comprises 4 wires which are connected to switch units 67, 68, 69 and 71 of the units 33, 34, 36 and 37 respectively.

The display and control unit 38 comprises a control panel 72 which typically includes a number of switches (not shown) by which the operator of the transceiver 31 controls the operation thereof. The switches control the transceiver 31 to receive, transmit, start, stop, etc., and are connected to the central control unit 41 through the flag bus 44. The output of the control panel 72 is connected to the interface 66 through an operation input-output (I/O) unit 73.

The unit 38 further comprises a display unit 74 which is connected to the interface 66 through a display drive unit 76. Although not shown in detail, the display unit 74 comprises a plurality of lights which indicate the operating status of the transceiver 31.

A buzzer 77 is provided to indicate any malfunction.

Upon receipt of the corresponding address and instruction signals, the interface 61 of the modem unit 33 feeds a gate signal to the switch unit 67 causing the same to connect the input or output of the modem unit 33 to the signal bus means 39 as required. The interfaces and switch units of the units 34, 36 and 37 function in essentially the same manner.

The modem unit 33 comprises a modem 66 and a modem 1/0 unit 78 connecting the modem 66 to the interface 61. As is customary, the modem 66 comprises a modulator 79 and a demodulator 81 which are activated by respective instruction signals. A secondary data modulator 82 and a secondary data demodulator 83 are connected to the interface 61 through a secondary data I/O unit 84.

The modulator 79 modulates an audio carrier wave suitable for transmission over the telephone line 46 with the compressed data signals from the signal processing unit 34.

The secondary data modulator 82 further modulators the carrier wave with secondary data signals for system control and response.

The demodulator 81 and secondary data demodulator 83 perform the opposite functions. Further illustrated is a clock pulse generator 86 which generates timing signals for system control.

A detailed construction of the interface 61 is shown in Figure 7 and comprises gate units 140 and 141, a buffer amplifier 142, an I/O chip selector 143 and an I/O port 144.

The gate unit 140 is adapted to transmit an interruption signal to the instruction bus 43. More specifically, when a signal capable of interruption is present on the flag bus 44, the gate unit 140 is controlled through an output line 145 of the I/O port 141 to produce an interruption signal fed thereto from the secondary data I/O unit 84 or the modem I/O unit 78. Made up of an output gate and an input gate, the gate unit 141 opens the output gate when a signal designating the modem unit 33 is present on the address bus 42 and a reference signal on the instruction bus 43, thereby producing an output signal on the flag bus 44. The reference signal on the instruction bus 43 represents the connection status or change in the status of the line connection unit 32 or the mode of operation of the modem unit 33. When conversely secondary data is present on the flag bus 44, the gate unit 141 applies the data to the secondary data I/O unit 84 and I/O port 144.

The buffer amplifier 142 is adapted to amplify a signal (current) on the instruction bus 43 and applies it to the I/O port 144 and secondary data I/O unit 84. The I/O chip selector 143 selects from signals on the address bus 42 a signal for selecting an input latch chip or an output latch chip and feeds it to the I/O port 144 as a chip selection signal independent of the other. The I/O port 144 comprises an input latch chip serving as a status register, an output latch chip and a gate and is adapted to temporarily hold a signal fed from the flag bus 44, line connection unit 32, secondary data I/O unit 84 or modem 110 78 in response to an I/O write or an I/O read signal from the instruction bus 43. In case where the modem I/O unit 78 includes the I/O port 144 and chip selector 143 therein, the interface 61 will be made up of the gate units 140 and 142 and buffer amplifier 142. Also, if an encoder and a decoder for secondary data are absent in the secondary data I/O unit 84, the encoder and decoder will then be included in the interface 61.

It is appreciated that the interfaces 62, 63, 64 and 76 function in essentially the similar manner to the interface 61 as mentioned above.

The central control unit 41 comprises a microcomputer 87 and a clock pulse generator 88 which generates clock pulses for timing the operation of the microcomputer 87. The microcomputer 87 is connected to the buses 42, 43 and 44 through an I/O control unit 89.

An operating program comprising addresses and instructions to be applied in sequence to the buses 42 and 43 is stored in a readonly memory (ROM) 91 which is connected to the microcomputer 87 through the unit 89. An address decoder 92 is provided to the ROM 91 by which the microcomputer 87 addresses the required memory locations in the ROM 91. The central control unit 41 further comprises a random access memory (RAM) 93 for storage of intermediate data.

An address decoder 94 is provided to the RAM 93 by which the microcomputer 87 may address the memory locations in the RAM 93 for reading or writing. In general, the microcomputer 87 addresses a memory location in the ROM 91 containing an address and instruction for a step of the operating program. The address and instruction are applied to the buses 42 and 43 respectively, causing the proper unit to perform the required operation. The flag bus 44 is sensed until it is determined that the operation has been completed. Then, microcomputer 87 steps to the next memory location in the ROM 91 which contains the address and instruction for the next step in the operating program. Temporary data required for branching operations and the like is stored in the RAM 93.

A detailed construction of the I/O control unit 89 is shown in Figure 8 and comprises an interruption control unit 150, an I/O port 151, a system controller 152, buffer amplifiers 153 and 154 and gate units 155 and 156. The interruption control unit 150 is responsive to an interruption signal from the gate unit 140 of each of the interfaces 61, 62, 63, 64 and 76 through the instruction bus 43 to encode and feed it to the I/O port 151. The I/O port 151 on the other hand feeds a signal required for interruption to the microcomputer 87 and, concurrently, feeds a branch instruction code to the input of the flag bus 44 at the system controller 152, the branch instruction code being specified by an output signal of the interruption control unit 150. The system controller 152 comprises a gate and a timing control circuit to control input and output of the microcomputer 87. More specifically, the system controller 152 is adapted to feed to the microcomputer 87 interrupt and flag signals applied thereto from the units 32, 33, 34, 36, 37 and 38 while transmitting instruction and flag signals from the microcomputer 87 to the buses 43 and 44 respectively. An address signal for specifying each of the units is fed from the microcomputer 87 to the address bus 42 through the buffer amplifier 154.

The gate unit 155 is opened when the microcomputer 87 produces an address signal designating the ROM 91 on the address bus 42 and the system controller 152 produces a read timing signal on the instruction bus 43, thereby transmitting data read out from the ROM 91 to the flag bus 44. Though controlled in the same manner by an address signal from the microcomputer 87 and a timing signal fom the system controller 152, the gate unit 156 opens its input gate when the system controller 152 commands writing to provide the RAM 93 with a status designating signal which is fed from each unit to the flag bus 44. When the system controller 152 commands reading, an output gate of the gate 156 will be opened to feed a status designating signal of each unit already stored to the flag bus 44.

The signal processing unit 34 comprises a compression-expansion unit 95 including a data compression unit 96 for compressing data signals from the scan unit 36 in accordance with run-length encoding or other known compression technique. A block unit 97 divides the compressed data into blocks and adds a header to each block.

The unit 95 is connected to the interface 62 through a data I/O unit 98. Further illustrated is a setup data I/O unit 99 which adds and recovers setup data as required.

The setup data includes data for reception setup and adjustment, and is added to the compressed data in the compression unit 96 by the unit 99.

The unit 95 further comprises an expansion unit 101 for expanding data received from the modem unit 33. The setup data unit 99 recovers the setup data and applies the same to synchronize reception. Further illustrated are an error unit 102 to detect errors in the received data and a block syncronization unit 103 to synchronize expansion of the blocks of data.

In order to absorb overflow of data signals during compression and expansion, the signal processing unit 34 further comprises a random access memory unit 104 which comprises a RAM 106. The RAM 106 is connected to the expansion-compression unit 95 through a RAM I/O unit 107. Where the rate at which data signals are applied to the expansion-compression unit 95 exceeds the rate at which the unit 95 can operate, the excess signals are temporarily stored in the RAM 106, thereby eliminating the possibility of lost data. Various components of the unit 95 may be used for both compression and expansion.

The scan unit 36 comprises a scanner 108 for scanning an original document 111 and producing analog electrical signals representing the same, and a quantization unit 109 which converts the analog signals into binary signals. The internal components of the scanner 108 are shown only symbolically, and include a light source 112 for illuminating the document 111 which is wound around a drum (not shown) and an optoelectronic converter 113. Connected to the interface 63 through a scan control I/O unit 114 are an AC drive unit 116 for rotataably driving the drum for horizontal scan and a step drive unit 117 for moving a scan head (not designated) in a stepwise manner by means of a stepping motor (not shown) for vertical scan.

The printing unit 37 comprises a printer 118 which includes a cutter 119 for cutting to length a copy sheet 123 provided in roll form, a plotter 121 for electrically reproducing an original document on the copy sheet 123 and a developing unit 122 for developing copy sheet 123.

The printing unit 37 further comprises an AC drive unit 124 for driving the cutter 119 and a step drive unit 126 for moving the copy sheet 123 through the plotter 121 in a stepwise manner for reproducing the scan lines of the original document.

The units 124 and 126 are connected to the interface 64 through a print control I/O unit 127. The operation of the plotter 123 is controlled by a print control unit 129 which controls a high voltage power supply 128.

The plotter 121 comprises an electrode plate 121b which is disposed below the copy sheet 123 and is elongated to correspond to the width of the copy sheet 123. Disposed above the electrode plate 121b in conjugate relation is an electrode assembly 121a comprising a large number of pins arranged in a row which can be individually energized by the power supply 128.

A voltage of typically 300V is applied to the electrode plate 121b from the power supply 128. In accordance with the received data signals, a voltage of 300V of the opposite polarity is applied to corresponding ones of the individual pins of the electrode assembly 121a from the power supply 128 under control of the unit 129. Whereas a voltage of 300V will not cause printing on the copy sheet 123, which is specially treated, a voltage of 600V will. Each scan line is printed on the copy sheet 123 by selective activation of the pins of the electrode assembly 121a and the sheet 123 is stepped through the plotter 121 to successively print the scan lines.

Since the operation of the various units of the transceiver 31 is controlled by the central control unit 41, modification of any unit or addition of more units may be performed without the necessity of modification of any other unit. The change in the sequence of operations of the transceiver 31 is accommodated merely by changing the program in the ROM 91. The ROM 91 may be of the programmable, erasable variety (EROM), facilitating program modification without replacement of the ROM 91. Alternatively, where the ROM 91 is provided as one or more integrated circuit chips, the program may be changed merely by replacement of the chip which may be performed in a plug-in manner.

It will be further understood that various components in the transceiver 31, especially the interfaces, have a high potential for interchangeability. This greatly reduces the number of spare parts required to maintain the transceiver 31. In addition, the various units of the transceiver 31 may be standardized and used in a series of transceivers which vary in capability and price.

Figures 4 and 5 illustrate a modified embodiment of the present invention which is generally designated as 131. Like elements are designated by the same reference numerals used in Figures 2 and 3. Similar but corresponding elements are designated by the same reference numerals primed.

Units 331, 34, 36l and 371 differ from the units 33, 34, 36 and 37 in that the switch units 67, 68, 69 and 71 are omitted, Instead, the units 331, 341, 361, and 371 are connected through signal lines 331a, 341a, 36la and 371a to a switch unit 132 which is connected to a central control unit 411 through the buses 42, 43 and 44. Upon suitable instructions from the central processing unit 411, the switch unit 132 connects required ones of the signal lines 331a, 341a, 36la, and 371a together.

The signal processing unit 341 is shown as further comprising a clock switch unit 133 for producing various synchronization signals for compression and expansion operations based on clock pulses from a clock pulse generator 124 under the control of a program timer 136.

WHAT WE CLAIM IS:- 1. A facsimile transceiver, comprising line connection means for connection to a signal transmission path and arranged to transfer signals between a common path and the signal transmission path, a plurality of units including at least a scan unit and a printing unit, each unit of said plurality being connected to said common path, each unit of said plurality of units including address receiver means and instruction receiver means, and a central control unit having address circuit means connected to each said address receiver means, and instruction circuit means connected to each said instruction receiver means, the control unit being operative to selectively enable the transmission of signals between the common path and the units connected to the path.

2. A transceiver according to claim 1, wherein the common path is defined by a single signal bus.

3. A transceiver according to claim 1, wherein the common path is defined by a plurality of signal buses.

4. A transceiver according to claim 3, wherein the central control unit is operative to generate an instruction signal to cause a selected one of said units connected to the common path to be connected to a selected one of the signal buses.

5. A transceiver according to any preceding claim, in which the address circuit means comprises an address bus and the instruction circuit means comprises an instruction bus.

6. A transceiver according to ony pre

**WARNING** end of DESC field may overlap start of CLMS **.

Claims (1)

1. **WARNING** start of CLMS field may overlap end of DESC **.

   The printing unit 37 comprises a printer 118 which includes a cutter 119 for cutting to length a copy sheet 123 provided in roll form, a plotter 121 for electrically reproducing an original document on the copy sheet 123 and a developing unit 122 for developing copy sheet 123.

   The printing unit 37 further comprises an AC drive unit 124 for driving the cutter 119 and a step drive unit 126 for moving the copy sheet 123 through the plotter 121 in a stepwise manner for reproducing the scan lines of the original document.

   The units 124 and 126 are connected to the interface 64 through a print control I/O unit 127. The operation of the plotter 123 is controlled by a print control unit 129 which controls a high voltage power supply 128.

   The plotter 121 comprises an electrode plate 121b which is disposed below the copy sheet 123 and is elongated to correspond to the width of the copy sheet 123. Disposed above the electrode plate 121b in conjugate relation is an electrode assembly 121a comprising a large number of pins arranged in a row which can be individually energized by the power supply 128.

   A voltage of typically 300V is applied to the electrode plate 121b from the power supply

   128. In accordance with the received data signals, a voltage of 300V of the opposite polarity is applied to corresponding ones of the individual pins of the electrode assembly 121a from the power supply 128 under control of the unit 129. Whereas a voltage of 300V will not cause printing on the copy sheet 123, which is specially treated, a voltage of 600V will. Each scan line is printed on the copy sheet 123 by selective activation of the pins of the electrode assembly 121a and the sheet 123 is stepped through the plotter 121 to successively print the scan lines.

   Since the operation of the various units of the transceiver 31 is controlled by the central control unit 41, modification of any unit or addition of more units may be performed without the necessity of modification of any other unit. The change in the sequence of operations of the transceiver 31 is accommodated merely by changing the program in the ROM 91. The ROM 91 may be of the programmable, erasable variety (EROM), facilitating program modification without replacement of the ROM 91. Alternatively, where the ROM 91 is provided as one or more integrated circuit chips, the program may be changed merely by replacement of the chip which may be performed in a plug-in manner.

   It will be further understood that various components in the transceiver 31, especially the interfaces, have a high potential for interchangeability. This greatly reduces the number of spare parts required to maintain the transceiver 31. In addition, the various units of the transceiver 31 may be standardized and used in a series of transceivers which vary in capability and price.

   Figures 4 and 5 illustrate a modified embodiment of the present invention which is generally designated as 131. Like elements are designated by the same reference numerals used in Figures 2 and 3. Similar but corresponding elements are designated by the same reference numerals primed.

   Units 331, 34, 36l and 371 differ from the units 33, 34, 36 and 37 in that the switch units 67, 68, 69 and 71 are omitted, Instead, the units 331, 341, 361, and 371 are connected through signal lines 331a, 341a, 36la and 371a to a switch unit 132 which is connected to a central control unit 411 through the buses 42, 43 and 44. Upon suitable instructions from the central processing unit 411, the switch unit 132 connects required ones of the signal lines 331a, 341a, 36la, and 371a together.

   The signal processing unit 341 is shown as further comprising a clock switch unit 133 for producing various synchronization signals for compression and expansion operations based on clock pulses from a clock pulse generator 124 under the control of a program timer 136.

   WHAT WE CLAIM IS:-

   1. A facsimile transceiver, comprising line connection means for connection to a signal transmission path and arranged to transfer signals between a common path and the signal transmission path, a plurality of units including at least a scan unit and a printing unit, each unit of said plurality being connected to said common path, each unit of said plurality of units including address receiver means and instruction receiver means, and a central control unit having address circuit means connected to each said address receiver means, and instruction circuit means connected to each said instruction receiver means, the control unit being operative to selectively enable the transmission of signals between the common path and the units connected to the path.

   2. A transceiver according to claim 1, wherein the common path is defined by a single signal bus.

   3. A transceiver according to claim 1, wherein the common path is defined by a plurality of signal buses.

   4. A transceiver according to claim 3, wherein the central control unit is operative to generate an instruction signal to cause a selected one of said units connected to the common path to be connected to a selected one of the signal buses.

   5. A transceiver according to any preceding claim, in which the address circuit means comprises an address bus and the instruction circuit means comprises an instruction bus.

   6. A transceiver according to ony pre

   ceding claim, wherein said plurality of units includes a switching unit, said switching unit being arranged to control the connection of each of the other units of said plurality to the common path in response to instructions from the central control unit.

   7. A transceiver according to any preceding claim, wherein each unit of said plurality of units includes flag means to indicate whether or not the unit is in an operative state, and wherein the central control unit includes flag circuit means connected to each of said flag means to establish the state of the unit.

   7. A transceiver according to claim 2, wherein the central control unit is operative to feed an instruction signal through the instruction circuit means to cause a selected one of said plurality of units to be connected to the signal bus, each of said plurality of units including a switch means for connecting the respective unit to the respective instruction signal.

   9. A transceiver according to any preceding claim, wherein the central control unit comprises a computer having a memory unit with an operating program for the transceiver stored therein, the program comprising a plurality of addresses and corresponding instructions for sequential application to the address and instruction circuit means.

   10. A transceiver according to any preceding claim, wherein the line connection means comprises a line connection unit and a modem unit.

   11. A facsimile transceiver, comprising a line connection unit for connection to a signal transmission path, a modem unit for modulating signal received from a common path and feeding the modulated signals to the line connection unit, and for demodulating signals received from the line connection unit and feeding the demodulated signals to the common path, a plurality of replaceable units including at least a scanning unit and printing unit connected in parallel to the common path, and a control unit operable to selectively actuate each said unit in accordance with the desired mode of operation of the transceiver.

   12. A transceiver according to claim 11, wherein said plurality of units further includes a signal processing unit for compressing or expanding the signal transmitted along the common path.

   13. A transceiver substantially as hereinbefore described with reference to Figures 2, 3 and 6 of the accompanying drawings.

   14. A transceiver substantially as hereinbefore described with reference to Figures 4, 5 and 6 of the accompanying drawings.