GB1594400A - Symmetry control system for a converter - Google Patents

Description

(54) SYMMETRY CONTROL SYSTEM FOR A CONVERTER (71) We, COUTANT ELECTRONICS LIM ITED, a British company, of Kingsley Avenue, Ilfracombe, Devon, EX34 8ES, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement:- This invention relates to a converter circuit where a DC power source is converted into a square wave for the purpose of transformation and control.

Figure 1 shows a known converter circuit which comprises a transformer T having a primary winding 10 with a centre tap connected to one pole Vcc of the DC power supply. Each of the ends of the primary winding 10 is connected by way of a respective transistor 12 and 14 to the other pole of the power supply. The two transistors 12 and 14 are alternately switched on at a constant frequency by a pulse-width modulator circuit 16 of fixed symmetry which is connected to a waveform generator 18 and to an amplifier 20 which senses the output voltage. The secondary winding 22 of the transformer T is also centre-tapped and connected together with two diodes 24 and 26 to form a full wave rectifier, the output voltage being smoothed by a choke 28 and a capacitor 30. The frequency of switching of the transistors 12 and 14 is constant but the power is controlled by varying the "ON" time of each transistor.

It will be appreciated that if the "ON" times of both transistors are identical, the average magnetization of the transformer T will be zero. This assumes identical turns on each half of the primary winding, identical transistor saturation and switching properties, and no short term variation of the DC input supply. In practice, there will always be a net DC magnetisation of the transformer even when extreme care is taken to ensure a symmetrical circuit, unless specific steps are taken to detect and avoid asymmetry.

Pulse-width control systems of this type have been produced without taking such steps but these circuits suffer from the inherent disadvantages of transformer D.C.

magnetization, namely reduced efficiency and unreliability of power transistors owing to the high peak currents and associated voltages. In the absence of any symmetry control, some over-specification of both transistors and transformer is necessary.

However, this procedure is most unsatisfactory since it depends on balance being maintained probably over a wide temperature range with perfect thermal matching of the power transistors. Power transistors must necessarily come in matched pairs, resulting in the added inconvenience of specialised testing and spares provision.

In order to overcome the problems of the circuit shown in Figure 1, there has already been proposed a circuit as shown in Figure 2 which takes special steps to avoid asymmetry. In Figure 2, the elements common with Figure 1 have been allocated the same reference numerals and need not therefore be described further. In Figure 2, a form of modulator 16 is modified to have variable symmetry, and is shown as 16'. Current sensors 32 and 34 are connected respectively in the collector circuits of the transistors 12 and 14. The output of the current sensor 32 is directly applied to an integrator 36 which is also connected to receive the output of the sensor 34 by way of an inverter 38. The time integral of the difference between the currents flowing in the respective transistors is applied to the variable symmetry modulator 16' in order to reduce the asymmetry.

When the circuit in Figure 2 is balanced, the output from the integrator is zero but for a small imbalance the output integrator will gradually increase or decrease depending on the direction of the imbalance. Thus, a signal is provided for the variable symmetry pulsewidth modulator 16' which then varies the ratio of the output-widths in such a direction as to correct the imbalance.

This system, in common with other known systems, has two control loops, one which controls the fundamental pulse-width according to the output power requirements and a second feed-back loop which controls the symmetry. It will be appreciated that some care must be taken in choosing the time constant of the integrator 36 in relation to the switching frequency period and the rate of change of transformer magnetizing current as determined by the primary inductance and supply voltage. It will be further appreciated that the symmetry control loop must be faster than the fundamental pulse-width loop in order to preserve reasonable balance during dynamically varying pulse-width conditions.

In the latter system, the sensed collector currents compnse a component dependent on load current and a further component (the magnetizing current) dependent only on pulse-width and supply voltage. At normal and high values of output power, the magnetizing component is normally a very small proportion of the total current. Since symmetry is achieved by balancing the magnetizing currents, fairly precise circuitry is required to have a satisfactory degree of control. It may also be postulated that if the load current varies in a synchronous manner with the switching frequency, the symmetry control may even operate so as to set up an undesirable D.C. flux in the transformer.

With a view to mitigating at least some of the foregoing disadvantages of the prior art systems, there is provided in accordance with the present invention a converter comprising a transformer having a centre-tapped primary winding controllable electronic switches for switching the currents in the respective halves of the primary winding on and off, means for rendering the said electronic switches conductive alternately and means for varying the relative conduction times of the electronic switches by detecting a pair of signals proportional only to the magnetization of the transformer, each of said signals being derived by sensing the difference between the total current flowing in a respective half of the primary winding and that flowing in the said half of the primary as a result of current flowing in the corresponding half of the secondary winding of the transformer.

It has been conventional to provide waveform generators to provide a ramp in the prior art circuits such as described in Figures 1 and 2 but if a signal is produced proportional only to the magnetizing component of the current flowing in the primary winding, then owing to the inductance of the primary winding this signal will of itself provide a ramp function. This feature may be used to advantage to further simplify the circuit and provide a single control loop enabling both the power and the symmetry to be controlled simultaneously.

Thus, in an advantageous development of the present invention, the means for alternately rendering the electronic switches conductive comprise means for producing a signal proportional to the difference between the desired and actual output voltage level, means for summing with the latter error signal a ramp function representative of the magnetizing currents flowing in the primary winding of the transformer and a bistable circuit arranged to change state each time the sum exceeds a reference threshold, the outputs of the bistable circuit being applied by way of respective gates in accordance with the state of a "clock" signal to the control terminals of the respective electronic switches.

Conveniently, the electronic switches are transistors.

The invention will now be described further, by way of example, with reference to the accompanying drawings, in which: Figures I and 2 earlier described are circuit diagrams of known converters, and Figure 3 is the circuit diagram of a converter in accordance with the present invention. In Figure 3, elements common to the prior art circuits have again been allocated the same reference numerals.

In addition to the current sensors 32 and 34 which detect the current flowing through the collectors of the respective transistors 12 and 14, there are provided current sensors 42 and 44 to detect the current flowing through the secondary winding of the transformer T.

The current sensors 32, 34 and 42, 44 may be current transformers or current sense resistors. The difference between the load current as would be reflected to the primary winding detected by the sensors 42 and 44, and the total current in the primary winding is a signal representative of the magnetizing component. Following suitable synchronous demodulation this signal will rise as a ramp each time one of the transistors 12 and 14 is switched on. The ramp generated by combining the signals from the sensors 32 and 42 is summed in a circuit 46 with the output of the amplifier 20 and as soon as this sum exceeds a threshold a comparator 50, which is connected in circuit with a similar comparator 52 to form a bistable circuit, changes state setting the bistable circuit, 50 and 52. Similarly, the output from the amplifier 20 is summed in a summation circuit 48 with the difference between the signal from sensor 34 and that from sensor 44 and when the sum exceeds the said threshold the comparator 52 resets the bistable circuit. The sense of the summing and sensing elements is so arranged as to provide the required synchronous demodulation. Thus the combination of the amplifier 20, the summation circuits 46 and 48 and the comparators 50 and 52 together form a pulse-width modulator which takes into account both the power output requirements and the asymmetry of the currents flowing in the windings. The complementary output signals of the bistable 50 and 52 are applied by way of inverters 54 and 56 and respective clocked "AND" gates 58 and 60 to the bases of the transistors 14 and 12. The "clock" inputs of the gates 58 and 60 achieve the predetermined switching frequency, complementary "clock" signals being applied to the gates 58 and 60. The gates 58 and 60 have further inputs connected respectively to the collectors of the transistors 12 and 14 to ensure that it is impossible for a transistor to be rendered conductive whilst the other is simultaneously conductive. In operation, each transistor will commence to conduct with the leading edge of a clock pulse, the clock pulses being chosen to be longer than the maximum time possible for the bistable circuit 50, 52 to change states. When the bistable changes states, the transistor will cease to conduct and will simultaneously apply an enable signal to the AND gate of the other transistor but that other transistor will not commence conducting until the next leading edge of its "clock" pulse. Thus the transistors are triggered with constant frequency but the pulse-widths will vary with the power and also to maintain the minimal average magnetization of the transformer 10.

WHAT WE CLAIM IS: 1. A converter comprising a transformer having a centre-tapped primary winding, controllable electronic switches for switching the currents in the respective halves of the primary winding on and off, means for rendering the said electronic switches conductive alternately and means for varying the relative conduction times of the electronic switches by detecting a pair of signals representative only of the magnetisation of the transformer, each of said signals being derived by sensing the difference between the total current flowing in a respective half of the primary winding and that flowing in the said half of the primary as a result of current flowing in the corresponding half of the secondary winding of the transformer.

2. A converter as claimed in claim I, wherein the means for alternately rendering the electronic switches conductive comprise means for producing an error signal proportional to the difference between the desired and actual output voltage level, means for summing with the latter error signal a ramp function derived from the magnetisation waveform of the transformer and a bistable circuit arranged to change state each time the sum exceeds a reference threshold, the outputs of the bistable circuit being applied by way of respective clocked gates to the control terminals of the respective electronic switches:.

3. Aiconverter as claimed in claim I or claim 2, wherein the electronic switches are transistors.

4. A converter as claimed in claim I or claim 2, wherein said pair of signals are derived by means incorporating one or thor current transformers.

5. A converter as claimed in claim I or claim 2, wherein said pair of signals are derived by means incorporating one or more current sense resistors.

6. Converter constructed substantially as hereinbefore described with reference to and as illustrated in Figure 3 of the accompanying drawings.

**WARNING** end of DESC field may overlap start of CLMS **.

Claims (6)

**WARNING** start of CLMS field may overlap end of DESC **. the bases of the transistors 14 and 12. The "clock" inputs of the gates 58 and 60 achieve the predetermined switching frequency, complementary "clock" signals being applied to the gates 58 and 60. The gates 58 and 60 have further inputs connected respectively to the collectors of the transistors 12 and 14 to ensure that it is impossible for a transistor to be rendered conductive whilst the other is simultaneously conductive. In operation, each transistor will commence to conduct with the leading edge of a clock pulse, the clock pulses being chosen to be longer than the maximum time possible for the bistable circuit 50, 52 to change states. When the bistable changes states, the transistor will cease to conduct and will simultaneously apply an enable signal to the AND gate of the other transistor but that other transistor will not commence conducting until the next leading edge of its "clock" pulse. Thus the transistors are triggered with constant frequency but the pulse-widths will vary with the power and also to maintain the minimal average magnetization of the transformer 10. WHAT WE CLAIM IS:

1. A converter comprising a transformer having a centre-tapped primary winding, controllable electronic switches for switching the currents in the respective halves of the primary winding on and off, means for rendering the said electronic switches conductive alternately and means for varying the relative conduction times of the electronic switches by detecting a pair of signals representative only of the magnetisation of the transformer, each of said signals being derived by sensing the difference between the total current flowing in a respective half of the primary winding and that flowing in the said half of the primary as a result of current flowing in the corresponding half of the secondary winding of the transformer.

2. A converter as claimed in claim I, wherein the means for alternately rendering the electronic switches conductive comprise means for producing an error signal proportional to the difference between the desired and actual output voltage level, means for summing with the latter error signal a ramp function derived from the magnetisation waveform of the transformer and a bistable circuit arranged to change state each time the sum exceeds a reference threshold, the outputs of the bistable circuit being applied by way of respective clocked gates to the control terminals of the respective electronic switches:.

3. Aiconverter as claimed in claim I or claim 2, wherein the electronic switches are transistors.

4. A converter as claimed in claim I or claim 2, wherein said pair of signals are derived by means incorporating one or thor current transformers.

5. A converter as claimed in claim I or claim 2, wherein said pair of signals are derived by means incorporating one or more current sense resistors.

6. Converter constructed substantially as hereinbefore described with reference to and as illustrated in Figure 3 of the accompanying drawings.