GB1593762A

GB1593762A - Transceiver circuits

Info

Publication number: GB1593762A
Application number: GB325777A
Authority: GB
Original assignee: UK Secretary of State for Defence
Current assignee: UK Secretary of State for Defence
Priority date: 1978-01-18
Filing date: 1978-01-18
Publication date: 1981-07-22

Description

(54) IMPROVEMENTS IN OR RELATING TO TRANSCEIVER CIRCUITS (71) 1, SECRETARY OF STATE FOR DE FENCE, LONDON, do hereby declare the invention, for which I pray that a patent may be granted to me, and the method by which it is to be performed, to be particularly described in and by the following statement: The present invention relates to computer systems of the kind including a plurality of modular units connected to a common bus, and to transceiver circuits for use in such connections.

It is common practice to construct computer systems or data processing systems as a plurality of modular units interconnected by a common bus, which generally comprises a plurality of data signal lines and a plurality of control lines.

The modular units in a system may include one or more central processor units, various store units, and other peripheral devices. At least some of the modular units will be able to do some internal operations independently, and in an efficient system several modular units will often be engaged on different internal tasks simultaneously.

However many signals must be sent from one unit to another, to initiate the next steps or report the results or to convey data or instructions. Thus each unit may need to send signals through the bus to other units and to receive and identify signals sent to it through the bus. The bus structure may be used to convey signals from any unit and to any unit; its usage is time-shared, and some control circuits are provided to control the application of signals to and from the bus, so that it may be used efficiently according to a prescribed system of priorities and so that signals are never lost or superimposed.

To increase the efficiency of the bus structure and its usage it is common practice to provide output latch circuits and input latch circuits for each modular unit. When signals are to be sent from the modular unit they are usually loaded into the output latch circuits and held there until the bus becomes free and available to carry them; and when signals appear on the bus they are loaded into the input latch circuits and may be held there temporarily if they are destined for the modular unit concerned but it cannot receive them immediately or simultaneously. This enables the various modular units and the bus to be operated asynchronously or on different time-scales so that limitations on the access time or speed of operation of certain modular units do not necessarily delay the whole system.

In a system where various modular units may operate simultaneously, the known arrangement wherein all output signals from a modular unit have to be passed via the output latch circuits to the bus can cause an embarrassing bottleneck situation. If the modular unit has loaded its output latching circuits with signals awaiting the availability of the bus when an interrogation signal arrives on the bus asking for the modular unit to provide some data in an immediate reply, this raises considerable problems. The signals already in the output latching circuits must not be lost or misinterpreted as a reply to the interrogation, and it is important to minimise the delay involved in getting the required reply on to the bus. The object of the invention is to provide an alternative arrangement which avoids these problems.

According to the present invention there is provided a transceiver circuit for connecting a modular unit to a bus in a computer system, comprising output latch circuits for holding signals from an output of the modular unit which are to be applied to the bus, a direct connection path through which signals from the said output of the modular unit can be applied immediately to the bus, bus driver circuits connected to the output latch circuits, a bus driver circuit connected in said direct connection path, and means for inhibiting signals from the output latch circuits when evcr signals are being sent through the direct connection pith.

The transceiver circuit may further comprise input latch circuits for holding signals from the bus which are to be supplied to the modular unit.

The transceiver circuit may include means whereby the modular unit controls the output latch circuits. and may further include means whereby an external bus control circuit controls the bus driver circuits.

The term "computer system" herein should be interpreted widely so as to include any kind of data processing system regardless of whether its operations include computation or merely comprise the retrieval or rearrangement of information.

An embodiment of the invention will now be described by way of example only and with reference to the drawing accompanying the Provisional Specification. which is a schematic block circuit diagram showing a transceiver circuit connected between a bus and a user module in a computer system.

The drawing shows the bus I controlled by arbiter circuits 2, a typical modular unit or user module 3, a transceiver circuit 4 arranged to connect the bus I to the user module 3 and vice versa. and a bus control unit 5 for controlling the passage of signals through the transceiver circuit 4. In a typical system there would be several user modules connected to the bus I by transceiver circuits 4, with a separate bus control circuit 5 for each user module. It is intended that the transceiver circuits 4 shall be made as 4-bit slice devices; that is to say made as integrated circuits each capable of handling 4-bit signals, and suitable for use in pairs to transfer 8-bit signals or in fours to transfer 16-bit signals. Thus a user module operable on 8-bit signals would be connected to the bus I by two transceiver circuits 4 connected substantially in parallel, each handling four specified bits of each 8-bit signal.

The transmitter part of each transceiver circuit 4 includes an address latch circuit 6, a data latch circuit 7 and a bus driver circuit 8 all connected to the signal output lines of the user module 3. Output connections from the latch circuits 6 and 7 are connected to bus driver circuits 9 and 10 respectively.

The bus driver circuits 8, 9 and 10 are basically power amplifiers and their outputs are connected through a common bus connection line of the circuit 4 to the bus 1. The bus driver 8 effectively provides a direct connection from the signal output lines of the user module 3 to the bus I, bypassing the latch circuits 6 and 7 and not including any storage elements. It is controlled by a direct drive control line (DDCL) 11 from the bus control unit 5. This line DDCL also controls two inhibiting gates 12 and 13 connected in series with control lines from the bus control unit 5 which control the bus driver circuits 9 and 10 respectively. The latch circuits 6 and 7 are controlled by a transmitter load control line (TLCL) 14 which is connected to the user module 3.

In operation the user module 3 will apply switching signals to the TLC line 14 to control loading operations of the latch circuits 6 and 7. The address latch circuit 6 responds to positive-going pulse edges and the data latch circuit 7 responds to negativegoing pulse edges on the TLC line 14. This arrangement is indicated on the drawing by the upwards vertical arrow on circuit 6 and the downwards vertical arrow on circuit 7.

The receiver part of the transceiver circuit 4 includes an address latch circuit 16 and a data latch circuit 17, both having inputs connected through the common bus connection line to the bus I and both controlled by a receiver load control line (RLCL) 18 from the bus control unit 5. Positive-going pulse edges on the line 18 will cause the address latch circuit 16 to load itself with the signals present on the bus I. Negative-going edges on the line 18 will cause the data latch circuit 17 to load itself with the signals present on the bus 1. This arrangement is indicated on the drawing by the upwards vertical arrow on circuit 16 and the downwards vertical arrow on circuit 17.

Outputs of the address latch circuit 16 are connected to a user address comparator circuit 19 and to address input connections of the user module 3. Outputs of the data latch circuit 17 are connected to data input connections of the user module 3. The user address comparator 19 is also connected to receive user address signals from the user module 3, and has an output connection 20 which is connected to the bus control unit 5.

The bus control unit 5 has separate outputs connected to the receiver load control line 18, the direct control line 11, and the lines controlling bus driver circuits 9 and 10 via gates 12 and 13 of each of the transceiver circuits connected to its user module 3, and will have a plurality of control lines 21 connecting it to the user module 3. The user module 3 has a plurality of signalling lines 22 which are connected to the bus control unit 5.

A typical user module may use the bus in any one of three ways; for a read cycle, for a write cycle, or for a read-modify-write cycle.

In the case of a write cycle, where the user module 3 has to send data signals through the bus to a specific destination in another module, it presents the required destination address signals to its signal output lines and a positive-going pulse edge to the TLC line 14, causing the destination address to be loaded into the address latch circuit 6. Then it applies the data signals to its signal output lines and a negative-going pulse edge to the TLC line 14, causing the data signals to be loaded into the data latch circuit 7. The user module then sends a "write cycle required" signal through lines 22 to the bus control unit 5. The bus control unit 5 then removes an enabling signals from one of the lines 21 to stop the module 3 doing anything which would require the use of latch circuits 6 or 7.

It also sends a request signal, through control lines in the bus 1, to the arbiter circuit 2.

When the arbiter circuit 2 determines that the bus 1 can be allocated to carry the signals from the module 3 it applies access granted signals to appropriate control lines in the bus 1. These signals cause the bus control unit 5 for module 3 to enable the bus driver circuit 9 and to apply another signal to the bus control lines which causes every other bus control unit in the system to apply a positivegoing pulse edge to its RLCL line, thereby allowing the address signals in the latch circuit 6 of the transceiver circuit for module 3 to pass through the bus and into the address latch 16 of each of the transceiver circuits connected to other user modules. In each of these transceiver circuits the address signals received are compared with address signals provided by their user modules. In the transceiver circuits connected to the user module containing the destination indicated by the address signals, the comparisons will produce a match energising lines corresponding to the line 20. These match-indicating signals are applied to the bus control unit 5 for the destination module. In cases where a plurality of 4-bit transceiver circuits are used to connect one module to the bus, the bus control unit 5 will have a gate circuit connected to determine when the matchindicating signals do indicate that the address is within the module. The source module 3 and its bus control unit 5 will hereinafter be called the master units, and the module containing the destination and its bus control unit will be called the slave units.

The slave bus control unit then applies a signal through a control line indicating that the destination address has been recognised.

In the case where the master module requires to write data signals into the destination address, the master bus control unit then energises its bus driver circuit 10 causing it to apply the data signals from the latch circuit 7 on to the bus 1, and the slave bus control unit lowers the voltage of its RLC line 18 causing the data signals to be loaded into the data latch circuits 17 of the slave module's transceiver circuits. The bus control units are then returned to their normal or standby condition and signals indicating completion of the cycle are sent to the arbiter circuit 2.

The enabling signal to the user module 3 is restored, allowing it to resume any activities which may need to load fresh signals into the latch circuits 6 and 7.

When the master module requests a read cycle (requiring to read some data signals from a specific address in another module) the action is somewhat similar. In this case the master module does not have to apply any data signals to its data latch circuits 7, and when the address has been recognised signals from the slave bus control unit cause the slave module to read the desired signals on to its output lines, then energise its DDCL line, and then send control signals through the bus 1 to tell the master bus control circuit that the desired signals are now available, being applied to the bus 1 by the bus driver circuits 8 of the slave module's transceivers.

The master bus control circuit then applies a negative-going signal to its RLC line 18 causing the desired signals to be loaded into its latch circuit 17. The control circuits then return to their normal or standby condition and signal to the arbiter that the action is completed.

When the master module requests a readmodify-write cycle, this starts like a read cycle but the bus allocation is held and the destination address is kept in the slave address latch circuits while the master user module is allowed to modify the data signals to present their modified form to the driver circuit 8 and to signal their availability to its bus control unit. The master bus control unit passes the latter signal via control lines in the bus to make the slave control unit lower its RLCL voltage, thereby loading the modified signals into its transceiver latch circuits 17.

Cycles of any one of these three kinds may be initiated by any user module in the system, and may occur in any order though the arbiter unit 2 will ensure that only one cycle controlled by one specific user module can be operated at any one time. The provision of the direct line bus driver circuits allows access to read data as required in any cycle from any module, even if that module has already filled its conventional output latch circuits with signals awaiting transmis sion.

WHAT I CLAIM IS:- I. A transceiver circuit for connecting a modular unit to a bus in a computer system, comprising output latch circuits for holding signals from an output of the modular unit which are to be applied to the bus, a direct connection path through which signals from the said output of the modular unit can be applied immediately to the bus, bus driver circuits connected to the output latch circuits, a bus driver circuit connected in said direct connection path, and means for inhibiting signals from the output latch circuits whenever signals are being sent through the direct connection path.

2. A transceiver circuit according to Claim I including means whereby the modular unit controls the output latch circuits.

**WARNING** end of DESC field may overlap start of CLMS **.

Claims

**WARNING** start of CLMS field may overlap end of DESC **.

loaded into the data latch circuit 7. The user module then sends a "write cycle required" signal through lines 22 to the bus control unit 5. The bus control unit 5 then removes an enabling signals from one of the lines 21 to stop the module 3 doing anything which would require the use of latch circuits 6 or 7.

It also sends a request signal, through control lines in the bus 1, to the arbiter circuit 2.

When the arbiter circuit 2 determines that the bus 1 can be allocated to carry the signals from the module 3 it applies access granted signals to appropriate control lines in the bus 1. These signals cause the bus control unit 5 for module 3 to enable the bus driver circuit 9 and to apply another signal to the bus control lines which causes every other bus control unit in the system to apply a positivegoing pulse edge to its RLCL line, thereby allowing the address signals in the latch circuit 6 of the transceiver circuit for module 3 to pass through the bus and into the address latch 16 of each of the transceiver circuits connected to other user modules. In each of these transceiver circuits the address signals received are compared with address signals provided by their user modules. In the transceiver circuits connected to the user module containing the destination indicated by the address signals, the comparisons will produce a match energising lines corresponding to the line 20. These match-indicating signals are applied to the bus control unit 5 for the destination module. In cases where a plurality of 4-bit transceiver circuits are used to connect one module to the bus, the bus control unit 5 will have a gate circuit connected to determine when the matchindicating signals do indicate that the address is within the module. The source module 3 and its bus control unit 5 will hereinafter be called the master units, and the module containing the destination and its bus control unit will be called the slave units.

The slave bus control unit then applies a signal through a control line indicating that the destination address has been recognised.

In the case where the master module requires to write data signals into the destination address, the master bus control unit then energises its bus driver circuit 10 causing it to apply the data signals from the latch circuit 7 on to the bus 1, and the slave bus control unit lowers the voltage of its RLC line 18 causing the data signals to be loaded into the data latch circuits 17 of the slave module's transceiver circuits. The bus control units are then returned to their normal or standby condition and signals indicating completion of the cycle are sent to the arbiter circuit 2.

The enabling signal to the user module 3 is restored, allowing it to resume any activities which may need to load fresh signals into the latch circuits 6 and 7.

When the master module requests a read cycle (requiring to read some data signals from a specific address in another module) the action is somewhat similar. In this case the master module does not have to apply any data signals to its data latch circuits 7, and when the address has been recognised signals from the slave bus control unit cause the slave module to read the desired signals on to its output lines, then energise its DDCL line, and then send control signals through the bus 1 to tell the master bus control circuit that the desired signals are now available, being applied to the bus 1 by the bus driver circuits 8 of the slave module's transceivers.

The master bus control circuit then applies a negative-going signal to its RLC line 18 causing the desired signals to be loaded into its latch circuit 17. The control circuits then return to their normal or standby condition and signal to the arbiter that the action is completed.

When the master module requests a readmodify-write cycle, this starts like a read cycle but the bus allocation is held and the destination address is kept in the slave address latch circuits while the master user module is allowed to modify the data signals to present their modified form to the driver circuit 8 and to signal their availability to its bus control unit. The master bus control unit passes the latter signal via control lines in the bus to make the slave control unit lower its RLCL voltage, thereby loading the modified signals into its transceiver latch circuits 17.

Cycles of any one of these three kinds may be initiated by any user module in the system, and may occur in any order though the arbiter unit 2 will ensure that only one cycle controlled by one specific user module can be operated at any one time. The provision of the direct line bus driver circuits allows access to read data as required in any cycle from any module, even if that module has already filled its conventional output latch circuits with signals awaiting transmis sion.

WHAT I CLAIM IS:- I. A transceiver circuit for connecting a modular unit to a bus in a computer system, comprising output latch circuits for holding signals from an output of the modular unit which are to be applied to the bus, a direct connection path through which signals from the said output of the modular unit can be applied immediately to the bus, bus driver circuits connected to the output latch circuits, a bus driver circuit connected in said direct connection path, and means for inhibiting signals from the output latch circuits whenever signals are being sent through the direct connection path.
2. A transceiver circuit according to Claim I including means whereby the modular unit controls the output latch circuits.
3. A transceiver circuit according to

Claim I or Claim 2 further comprising input latch circuits fi,r holding signals from the bus which arc to be supplied to the modular unit.
4. A transceiver circuit according to Claim 3 including means whereby an external bus control circuit controls the bus driver circuits and the input latch circuits
5. A transceiver circuit substantially as described herein with reference to the drawing accompanying the provisional specifica tion.