GB1593140A

GB1593140A - Position indicating apparatus

Info

Publication number: GB1593140A
Application number: GB5049/78A
Authority: GB
Original assignee: Westinghouse Electric Corp
Current assignee: CBS Corp
Priority date: 1977-02-18
Filing date: 1978-02-08
Publication date: 1981-07-15
Also published as: BE864080A; CA1125918A; IT1104427B; JPS53102786A; JPS6232809B2; IT7841525A0; DE2806889A1; FR2381419A1

Description

(54) POSITION INDICATING APPARATUS (71) We, WESTINGHOUSE ELECTRIC CORPORATION of Westinghouse Building, Gateway Center, Pittsburgh, Pennsylvania, United States of America, a company organised and existing under the laws of the Commonwealth of Pennsylvania, United States of America, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement: This invention relates to an improved position indicating apparatus including a resolver.

In many applications it is required to convert angular displacements into digital information. In numerical control applications for example, resolver angular displacements are converted to a binary representation of the shaft position, and pulses are generated which are a function of the shaft displacement. Conventional resolver apparatus using analog voltagecontrolled oscillators to perform this function, require considerable maintenance and special care to preserve accuracy.

It is an object of this invention to provide an improved position indicating apparatus including a resolver which overcomes the deficiencies of the prior art.

The invention resides in a position indicating apparatus comprising a resolver having stator means and a rotor means, resolver exciter means for generating resolver excitation signals to be applied to said stator means, means connected to said rotor means for successively defining a measuring time interval between the occurrences of zero crossing in one direction of signals induced in said rotor means, counter means operative in a single direction for successively counting a predetermined sequence of counts between a negative and a positive limit through zero, means for strobing and holding an instantaneous count on said counter means upon the initiation of each measuring time interval, said held count representing an incremental rotational movement of said rotor means during the preceding measuring time interval, means responsive to said held count for advancing or retarding the counting sequence to change the relative phase of zero count such that the next held count would be zero if no incremental rotation of said rotor means takes place during the current measuring time interval, and means for accummulating from measuring time interval to measuring time interval said counts as strobed and held, thereby to derive incrementally an indication of the rotational position of said rotor means relative to its origin.

The invention will become readily apparent from the following decription of an exemplary embodiment thereof when read in conjunction with the accompanying drawings, in which: Figure 1 is a block diagram of a position indicating apparatus in accordance with the invention, and illustrating its utilization in a numerical control environment; Fig. 2 is a simplified block diagram of the phase tracking counter employed in the apparatus of Fig. 1; Fig. 3 is a table used in explaining the phase track count sequence; Fig. 4 is a more detailed block diagram of the phase tracking counter of Fig. 3; Fig. 5 is a table of the addresses and outputs of the read-only memory (ROM) portion of the phase tracking counter of Fig. 4; Fig. 6 is a block diagram of the phase error register, the pulse rate multiplier, and the advance and retard flip flops shown in the embodiment of Fig. 1; and Fig. 7 is a block diagram of the logic .circuitry for generating preset and advance and retard signals for the ROM addresses.

Referring now to Figure 1, the position indicating apparatus of the invention, indicated generally at 10, is here illustrated in the environment of the numerical control of a machine tool indicated generally at 12.

Typically, the machine tool 12, which may be a planner mill or the like, is actuated through a drive gear box 14 which is driven by a motor 16. A computer 18 controls the rotary displacement of the drive motor 16 through a drive amplifier 20.

A rotary control transformer (RCT) indicated generally at 22, has its rotor shaft coupled to precision gearing 24 to receive a shaft angular displacement 0 which is a function of the linear axial displacement of the lead screw of the machine tool 12. The electrical output of the rotor R,R2 of the resolver 22 is sent to a signal processing portion indicated generally at 26.

Two sine waves are required to excite the stator winding S,S3; S2S4 of the rotary control transformer 22. The sine waves must be ninety degrees apart or in quadrature. It is of extreme importance that this quadrature relationship be maintained with a high degree of precision.

These waves may be generated in any convenient and inexpensive manner so long as the requisite phase accuracy is nlaintained. Advantageously, a pulse width modulation technique may be utilized such as taught in an article entitled "Reduce Static Inverter Weight and Cost by Harmonic Neutralization" -P. W. Koetsch appearing in the publication EDN on January 15, 1971. Pulse width modulated sine and cosine PWMSIN and PWMCOS are applied to the stator winding of RCT 22 through drivers 28 and 30, respectively.

For phase encoded resolver position measurement, the two stator windings S1-S3 and S2-S4 of the rotary control transformer 22 (which are physically wound to produce flux vectors in spatial quadrature) are excited with fixed frequency identical amplitude A.C. signals PWMSIN, PWMCOS which are in temporal quadrature, i.e. shifted in time by 90". The resulting rotor output (R,R2) is a constant amplitude A.C. signal whose phase, with respect to one of the excitation A.C. signals, is linearly proportional to the rotor shaft position ,b of the. RCT 22.

The output of the rotary control transformer 22 is a complex wave having a number of harmonics which are the inherent result of generating a square wave, in addition to those contributed by the nonlinearity of the RCT 22 itself. Interest is only in the fundamental which is of constant amplitude, having a nominal.

frequency of 2000 Hz, which moves along as the rotor shaft turns, that is, if we synchronize on the sine wave, the phase will shift forward or backward in time as the shaft rotates in one direction or the other.

This is identifiable by the zero crossing of the sine wave.

The output of the RCT 22 is fed to a differential amplifier 32 and then to a filter 34. The lines RESFB1 and RESFB2 represent the two sides of the rotor coil R1R2, the actual signal being the voltage difference between them. The signals are passed through the differential amplifier 32 for common mode rejection and for scaling to the proper amplitude for the filter 34.

The filter 34 effectively rejects the higher harmonics which are riding in the phase encoded signal. The excitation effectively creates a flux vector in the resolver 22 that is rotating at 2000 revolutions per second..

The filtered output is passed to a zerocrossing detector (ZCD) 36 and to a synchronizing circuit indicated generally at 36, where the phase data is extracted from the fundamental, converted to a digital logic level by the ZCD, and is then synchronized to the system clock which accomplishes the quantization of the otherwise smooth variation of phase with the resolver shaft position. The filtered output is fed to the ZCD 36 because it is desired to square the wave -the only interest is in phase and not the amplitude of the signal.

The squared feedback phase synchronized signal (FBPS) is effectively compared with the phase output of a phase tracking counter 38 to develop a digital phase error a binary number representing the magnitude and direction of the phase error. The measurement is accomplished by using the leading edge of the synchronized digital pulse to strobe the contents of the free running phase tracking counter 38 into the phase error register 40. As will be explained, the counter 38 is continuously counting and has a special count sequence (implemented by a read-only memory (ROM) and some counters). The special count sequence is arranged so that when the phase tracking counter 38 and the phase feedback are in phase, the contents of the counter 38 are zero at the occurrence of the leading edge of the phase feedback signal.

When the phase tracking counter 38 is behind the phase feedback from the resolver, advance pulses are sent to the counter 38 to cause it to catch up; conversely, when the counter 38 is ahead of the phase feedback from the resolver, pulses are sent to retard the counter to slow it down. The number of advance or retard pulses sent to the counter 38 is a function of how far the resolver shaft has been displaced.

A phase error register 40 is connected to the phase tracking counter 38. When the feedback phase synchronized (FBPHS) signal strobes are contents of the phase tracking counter 38 into the phase error register 40, the contents of the register (called a phase/error PHER word) represents the magnitude of the phase error at the time of strobing or sampling.

The phase error word PHER is coupled to a pulse rate multiplier (PRM) and synchronizing circuit 42. The PHER word controls the pulse rate multiplier (PRM) 42, generating a frequency proportional to the magnitude of the PHER word. This frequency, in conjunction with the sign of the PHER word, generates count up (CTUP) or count down (CTDN) pulses causing the phase tracking counter 38 to phase advance (ADV) or phase retard (RET) (by counting by two for one clock time or by remaining in the same count state for two clock times respectively). In this manner the count pulses cause the phase of the phase tracking counter 38 to track of the phase of the resolver feedback signal. Thus if the phase error is 10 counts behind, the PRM 42 will send out 10 ADVANCE (CTUP) pulses to the phase track counter 38. However, these pulses will not be sent in a bunch, but instead will be evenly spaced in time between the times of the strobes by the FBPS signal. Stated differently, 10 count pulses will be evenly supplied in time between the times when the leading edges of the FBPS signal goes from 0 to ONE (marked on the FBPS signal by the x's in Fig. 1).

The count pulses CTUP, CTDN also go to the delta position counter (DELPOS) 44 and to the theta counter 46 where they are accumulated. The accumulated magnitude in these counters 44, 46 is read into the computer 18 upon signal from the control logic 48. The logic 48 is controlled by the input/output signals from the computer 18.

The logic 48, inter alia, signals the read out and reset control for the DELPOS counter 44. Upon a signal to control logic 48 from the computer 18, the register of the DELPOS counter 44 is read, that is, a 16 bit word is transferred from its register to an accumulator in the computer 18, and the counter 44 is reset to ZERO. The counter 44 is a delta or incremental reading which indicates how far the resolver 22 has moved since the last reading. The counter 44 accumulates pulses until the computer 18 signals read out and then resets it to begin the cycle again.

The theta counter 46 is never reset except at power turn on when it is synchronized with the electrical zero of the resolver 22. It feeds its information into the computer 18 upon signal from the control logic 48. The theta counter 46 indicates the absolute rotary position of the shaft during 360" of revolution. From counter 46 the resolver shaft position is known between 0--360" of revolution. The computer 18 keeps track of the number of revolutions by sampling the register of the theta counter 46.

The phase tracking counter 38, shown schematically in Fig. 2, comprises a readonly memory (ROM) 50, a plurality of flip flops indicated generally at 52, and two 4 bit binary up-down counters 54, 56.

The output of the counter is 11 bits: K, A, B, C, D, E, F,G, H, I, J.Kisasignbit,Ais the least significant bit, and J is the most significant bit. The ROM 50 and the flip flops 52 control the state of the counter 38.

The bits A to J have the weighted magnitudes indicated in Fig. 2. Since this is binary notation, the counter can count from 0 to 1024 in each direction for a total of 1024x2 or 2048 states.

Only 2000 states are desired, so when the counter reaches +0, it is preset to -1, and when the counter reaches -1000 it is preset to +999. This is accomplished by the ROM 50 which is addressed by the bits K, A, B plus two additional bits, a retard or preset, and an advance or preset.

The preset function is performed as follows. Referring now to Fig. 3, when the counter is counting, the K bit identifies the direction of count. For example, when the count sequence is +7, +6, +5, +4 etc. K=0; when the count sequence is -1,-2, -3, etc.

K=l. The ROM 50 is also cognizant of the addresses Ao (A bit), A1 (B bit) plus A3 (retard or preset) and A4 (advance or preset). From logic circuitry which will be explained in connection with Fig. 7, when the preset conditions are approached (i.e.

-1 and +999) A3 and A4 become ONES (the same logic signal occurs as both states are approached, but these states are numerically far enough apart so no ambiguity obtains). The ROM 50 is programmed so that when K=0 and a preset condition is indicated, the counter continues to count until A=0 B=0 -the ROM 50 now gives the appropriate output and the counter is at -1. As will be seen from Fig. 3, -1 is like +1 except that the sign bit has changed, K now equals +1.

Similarly, when it is desired to preset to +999, (A3 and A4 are ONES as previously explained) the counter is at K=l, and when A=0 B=0, the ROM will provide the correct output and the counter will move to +999-K is now 0. Note again +999 is like -999 except that the sign bit has changed.

When the tracking counter 38 and the feedback FBPS are in phase, the contents of the counter 38 are zero at the occurrence of the leading edge of the phase feedback signal. When the counter 38 is behind the phase-feedback from the resolver ADVANCE pulses are sent to the counter 38 to catch up. Conversely, when the counter 38 is ahead of the phase feedback from the resolver 22, pulses are sent to RETARD the counter 38 to slow it down.

The ADVANCE and RETARD conditions are also illustrated in Fig. 3. When an ADVANCE is sent to the counter 38, it skips one state and goes to the next. When a RETARD is sent to the counter 38 it remains at the same state instead of moving on to the next state. The number of advance or retard pulses sent to the counter 38 is a function of the angular displacement of the rotor shaft.

The phase tracking counter 38 is shown in greater detail in Fig. 4. The flip flops generally identified at 52 in Fig. 2, are now further identified as 58, 60, 62, 64 and 66.

The ROM 50 is programmed to have the definitive outputs Q,...Q, when addressed at A0A1. . A4 as shown in Fig. 5. During a normal counting A3A4 are ZEROS. When presetting to either -1 or +999, both A3 and A4 are ONES. When an ADVANCE pulse is indicated, A3=ONE and A4=ZERO. When a retard pulse is required these positions are reversed viz. A3=ZERO and A4=ONE.

The ROM 50 outputs Ql to Q, are shown in Fig. 5. The Q4 output provides m which is a count enable signal to counter 54. The Qs output DN provides the direction, that is, when DN=0 the count is up, and when DN=l the count is down. Q6 and Q, provide the next count up (CTUP) and the next count down (CTDN) signals respectively which are applied to driver 68 in the circuitry of Fig. 6.

In Fig. 6 there is shown the phase error register 40, the pulse rate multiplier 42 and the advance and retard flip flops indicated generally at 70. The phase error register 40 stores the 11 bits from the phase track counter 38 (Fig. 4) at the time that the feedback phase synchronized (FBPS) signal goes from a zero to a one. By virtue of the particular count sequence of the phase track counter 38, the resulting contents of the phase error register 40 contains both the magnitude and the sign of the number of up or down counts required to ADVANCE or RETARD the phase track counter 38 back into synchronism with the feedback phase synchronized (FBPS) signal.

The pulse rate multiplier 42 receives the bit inputs A...J. The K bit out of the phase error register will be identified as PHERPL and this is applied to the flip flops 70.

The required number of pulses are not generated in one quick burst but are evenly spread out during the period of time before the next leading edge of the FBPHS signal goes from zero to one, i.e., during the 500 micro-seconds between the leading edges of the 2000 Hz signal.

The pulse rate multiplier 42 is a binary counter connected to a plurality of gates, one gate for each stage. The outputs are indicated in Fig. 6. For example 1/16 means that one of out of 16 will be gated out, 1/32 means that one out of thirty two will be gated out, etc. The output frequency fo of the pulse rate multiplier is PHER fo=4MHzx 4096 where PHER is the phase error magnitude.

Thus, if the phase error magnitude is 1, fo will be approximately 2000 Hz or 1 pulse in the 500 microseconds between the leading edges of the FBPHS signal.

Although ten bits are used for the PHER magnitude, normally the higher magnitude bits will only be used when initially synchronizing the phase track counter 38.

Each pulse fo out of the pulse rate multiplier is a request to advance or retard the phase track counter. The flip flop 70 comprise two D flip flops 72 and 74. These two flip flops act as buffers for the requested change to the phase tracking counter 38 until the proper state of the counter 38 allows the CTUP or CTDN to reset the flip flops. ~~~~~~~~ When the phase error is +, PHERPL is -(ZERO). When a clock pulse arrives, ADVANCE=ONE, i.e. in flip flop 72 Q=l, Q=0. At the same time RETARD=ZERO, i.e. in flip flop 74 Q=ZERO and =ONE.

When the phase error is-, PHERPL is + (ONE). When a clock pulse arrives, RETARD=ONE and ADVANCE=ZERO.

In the retard flip flop 74, Q=ONE, Q=0. In the advance flip flop 72, Q=ONE, Q=ZERO. When CTUP and CTDN occur, the ADVANCE and RETARD flip flop 72, 74 are reset.

The ADVANCE and RETARD signals are applied to the logic circuitry of Fig. 7.

The advance pulse is applied to OR gate 76 and the retard pulse is applied to OR gate 78. The 8 bits CDEFGHIJ are applied to DECODE LOGIC 80, the output, PRESET -001, PRESET +999 being applied to OR gates 76, 78. The output of the OR gates are applied to the ROM 50 of the phase tracking counter 38.

The decode logic 80 outputs, two ones at both PRESET -001 and +999, as well as ADVANCE OR RETARD ONES as explained above. The OR gates 76, 78 develops a ONE output if there is a ONE at any one of its inputs.

WHAT WE CLAIM IS: 1. A position indicating apparatus comprising a resolver having stator means and a rotor means, resolver exciter means for generating resolver excitation signals to be applied to said stator means, means connected to said rotor means for

**WARNING** end of DESC field may overlap start of CLMS **.

Claims

**WARNING** start of CLMS field may overlap end of DESC **.

RETARD the counter 38 to slow it down.

The ADVANCE and RETARD conditions are also illustrated in Fig. 3. When an ADVANCE is sent to the counter 38, it skips one state and goes to the next. When a RETARD is sent to the counter 38 it remains at the same state instead of moving on to the next state. The number of advance or retard pulses sent to the counter 38 is a function of the angular displacement of the rotor shaft.

The phase tracking counter 38 is shown in greater detail in Fig. 4. The flip flops generally identified at 52 in Fig. 2, are now further identified as 58, 60, 62, 64 and 66.

The ROM 50 is programmed to have the definitive outputs Q,...Q, when addressed at A0A1. . A4 as shown in Fig. 5. During a normal counting A3A4 are ZEROS. When presetting to either -1 or +999, both A3 and A4 are ONES. When an ADVANCE pulse is indicated, A3=ONE and A4=ZERO. When a retard pulse is required these positions are reversed viz. A3=ZERO and A4=ONE.

The ROM 50 outputs Ql to Q, are shown in Fig. 5. The Q4 output provides m which is a count enable signal to counter 54. The Qs output DN provides the direction, that is, when DN=0 the count is up, and when DN=l the count is down. Q6 and Q, provide the next count up (CTUP) and the next count down (CTDN) signals respectively which are applied to driver 68 in the circuitry of Fig. 6.

In Fig. 6 there is shown the phase error register 40, the pulse rate multiplier 42 and the advance and retard flip flops indicated generally at 70. The phase error register 40 stores the 11 bits from the phase track counter 38 (Fig. 4) at the time that the feedback phase synchronized (FBPS) signal goes from a zero to a one. By virtue of the particular count sequence of the phase track counter 38, the resulting contents of the phase error register 40 contains both the magnitude and the sign of the number of up or down counts required to ADVANCE or RETARD the phase track counter 38 back into synchronism with the feedback phase synchronized (FBPS) signal.

The pulse rate multiplier 42 receives the bit inputs A...J. The K bit out of the phase error register will be identified as PHERPL and this is applied to the flip flops 70.

The required number of pulses are not generated in one quick burst but are evenly spread out during the period of time before the next leading edge of the FBPHS signal goes from zero to one, i.e., during the 500 micro-seconds between the leading edges of the 2000 Hz signal.

The pulse rate multiplier 42 is a binary counter connected to a plurality of gates, one gate for each stage. The outputs are indicated in Fig. 6. For example 1/16 means that one of out of 16 will be gated out, 1/32 means that one out of thirty two will be gated out, etc. The output frequency fo of the pulse rate multiplier is PHER fo=4MHzx

4096 where PHER is the phase error magnitude.

Thus, if the phase error magnitude is 1, fo will be approximately 2000 Hz or 1 pulse in the 500 microseconds between the leading edges of the FBPHS signal.

Although ten bits are used for the PHER magnitude, normally the higher magnitude bits will only be used when initially synchronizing the phase track counter 38.

Each pulse fo out of the pulse rate multiplier is a request to advance or retard the phase track counter. The flip flop 70 comprise two D flip flops 72 and 74. These two flip flops act as buffers for the requested change to the phase tracking counter 38 until the proper state of the counter 38 allows the CTUP or CTDN to reset the flip flops. ~~~~~~~~ When the phase error is +, PHERPL is -(ZERO). When a clock pulse arrives, ADVANCE=ONE, i.e. in flip flop 72 Q=l, Q=0. At the same time RETARD=ZERO, i.e. in flip flop 74 Q=ZERO and =ONE.

When the phase error is-, PHERPL is + (ONE). When a clock pulse arrives, RETARD=ONE and ADVANCE=ZERO.

In the retard flip flop 74, Q=ONE, Q=0. In the advance flip flop 72, Q=ONE, Q=ZERO. When CTUP and CTDN occur, the ADVANCE and RETARD flip flop 72, 74 are reset.

The ADVANCE and RETARD signals are applied to the logic circuitry of Fig. 7.

The advance pulse is applied to OR gate 76 and the retard pulse is applied to OR gate 78. The 8 bits CDEFGHIJ are applied to DECODE LOGIC 80, the output, PRESET -001, PRESET +999 being applied to OR gates 76, 78. The output of the OR gates are applied to the ROM 50 of the phase tracking counter 38.

The decode logic 80 outputs, two ones at both PRESET -001 and +999, as well as ADVANCE OR RETARD ONES as explained above. The OR gates 76, 78 develops a ONE output if there is a ONE at any one of its inputs.

WHAT WE CLAIM IS: 1. A position indicating apparatus comprising a resolver having stator means and a rotor means, resolver exciter means for generating resolver excitation signals to be applied to said stator means, means connected to said rotor means for

successively defining a measuring time interval between the occurrences of zero crossing in one direction of signals induced in said rotor means, counter means operative in a single direction for successively counting a predetermined sequence of counts between a negative and a positive limit through zero, means for strobing and holding an instantaneous count on said counter means upon the initiation of each measuring time interval, said held count representing an incremental rotational movement of said rotor means during the preceding measuring time interval, means responsive to said held count for advancing or retarding the counting sequence to change the relative phase of zero count such that the next held count would be zero if no incremental rotation of said rotor means takes place during the current measuring time interval, and means for accummulating from measuring time interval to measuring time interval said counts as strobed and held, thereby to derive incrementally an indication of the rotational position of said rotor means relative to its origin.
2. A position indicating apparatus as claimed in claim I wherein said counter means includes at least one up/down counter and a read-only memory (ROM), said up/down counter being responsive to said ROM for outputting said predetermined sequence of counts, said ROM being responsive to the outputted count of said up/down counter for stepping said counts in the succession of said sequence.
3. A position indicating apparatus as claimed in claim 2 wherein said counts are binary numbers having an associated binary sign, said means responsive to the held count including means responsive to the magnitude of a held binary number for converting the same into an aggregated number of binary command signals outputted during the current measuring time interval, each of said binary command signals being effective through said ROM to cause one of an advance step and a retard step in the said sequence of counts, each of such said advance and retard steps being performed in relation to the sign associated with the corresponding binary number, thereby to change the relative phase of the zero count by a number of steps equal to said aggregated number.
4. A position indicating apparatus as claimed in claim 3 wherein said means responsive to the held count includes means for evenly distributing said aggregated number of command signals throughout the current measuring time interval.
5. A position indicating apparatus as claimed in claim 4 wherein said means responsive to the held count includes pulse rate multiplier means responsive to said held count for generating a frequency signal having a frequency proportional to the magnitude of said held binary number, said frequency signal being effective to produce a train of said command signals throughout the measuring time interval.
6. A position indicating apparatus substantially as hereinbefore described with reference to, and as shown in, the accompanying drawings.