GB1590015A - Secure coded transmission systems - Google Patents

Description

(54) IMPROVEMENTS IN OR RELATING TO SECURE 8 CODED TRANSMISSION SYSTEMS (71) We, THE MARCONI COMPANY LIMITED, of Marconi House, New Street, Chelmsford CMl 1PL, Essex, a British Company, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement: The present invention relates to secure coded transmission systems and more particularly to a receiver for the reception of securely coded digital signals.

For the purpose of the present specification a "secure coded transmission system" is defined as a transmission system in which the transmitted information ("a securely coded digital signal") is derived by combining input data in digital form with a digital coding sequence obtained from a sequence generator.

In secure coded transmission systems it is necessary for the receiving equipment to be in synchronism with the transmitting equipment so that the transmitted information can be decoded correctly. In one known type of transmission system synchronism of the receiver is obtained by transmitting at the start of each message the coding information in the form of the digital coding sequence to synchronise the receiver. A known receiver for this system includes a sequence generator and a comparator, the digital coding sequence being fed into the comparator and into the sequence generator. When a comparison is obtained over a given number of digits between the output of the sequence generator and the input to the receiver a switch is operated which changes the sequence generator over to a self-circulating sequence generator and the receiver is then in synchronism with the transmitter.This type of receiver suffers from the disadvantage that if during the transmission of a message synchronism is lost the receiver must be capable of detecting such a loss of synchronism and of reestablishing synchronism.

It is an object of the present invention to provide a receiver for a secure coded transmission system which synchronises automatically with incoming signals.

Accordingly the present invention in its most general aspect provides a receiver for receiving information transmitted digitally in coded form, including a first sequence generator, a second sequence generator, a two input digital comparator which produces an output signal when an agreement is obtained between a predetermined number of bits of a first and second binary sequence received at its first and second input, switch means, having a first and a second condition, for connecting either the output of the first or the second sequence generator to the first input of the comparator for comparison with the receiver input signal and control means arranged to change over the switch means from one condition to the other condition in response to the output from the comparator.

The present invention also provides a secure coded transmission system having a receiver as specified in the last paragraph.

An embodiment of the present invention will now be described, by way of example, with reference to the drawings accompanying the provisional specification in which: Figure 1 shows a secure coded transmission system including a known receiver.

Figure 2 shows a transmission system according to the present invention.

Referring now to Figure 1, digital information Tx CLEAR is produced by means not shown and fed as one input of a two input adder ADD 1. The adder ADD 1 may be a circuit performing a simple summation but,in the case of binary signals, it is generally a modulo-2 adder and in the case of m-ary signals (signals with m levels) it is generally a modulo-m adder.

The input information Tx CLEAR may for example be of three different types and the type of information will determine the bit rate at which the information is required to be transmitted and will therefore determine the bit rate of a digital sequence generator S.G.1 the output sequence of which is added to Tx CLEAR in the adder ADD 1. The three types of information and approximate associated bit rates are: facsimile (i.e. transmission of pictures, photographs) - 2 to 4 K bits/sec.; Speed - 16 K bits/sec.; Telegraph - 50 bits/sec. The sequence generator S.G.I will hereinafter be assumed to be designed to operate at a suitable bit rate for each type of transmission and therefore no further reference will be made to bit rates.

The output of the adder ADD 1, Tx CODE, is transmitted by any suitable means, e.g.

frequency modulation of a carrier signal, to a receiver Rx where it is demodulated in known apparatus (not shown). The demodulated signal, Rx CODE, will, assuming no transmission errors, be equal to Tx CODE, and is fed to one input of a two input comparator C1. A changeover switch SW is connected so that in position 1 as shown its wiper can feed Rx CODE into a sequence generator S.G.2 and in position 2 the output of the sequence generator S.G.2 is fed back into the input. These positions 1,2, of the wiper are respectively known as the FILL and CIRCULATE positions of the switch SW. Sequence generator S.G.2 is identical in design to sequence generator S.G.1 and its output is fed to an adder ADD 2 in which it is added to the received signal Rx CODE to form the decoded signal Rx CLEAR.

The position of the wiper of switch SW is controlled by an output signal S.C. from a bistable By , which output signal occurs when comparator C1 finds agreement between the ouptut of sequence generator S.G.2 and the input signal Rx CODE. Bistable B1 is resettable by an out-of-synchronisation signal O.S.

received at a terminal T.

The known synchronising procedure for this system is as follows:- Each sequence generator S.G.1, S.G.2 produces a sequence Sn when its input is connected to its output. This sequence Sn is therefore a deterministic function of a FILL signal Fn. The transmitting station Tx has the FILL input Fl connected to the sequence generator output S1 so that the following equation is satisfied: S1(F1)=F1 The receiving sequence generator S.G.2 is filled via switch SW which can connect input F2 to either the output S2 of sequence generator S.G.2 or to the transmitted signal.

The known synchronising procedure is as follows: 1. At the beginning of a transmission, and optionally at other times during the transmission, the transmit clear data is suppressed to all zeros. Thus the transmitted data is equal to F1.

2. The switch SW is set to the FILL position Thus signal at F2 = signal sequence at Fl 3. After all memory stages in the receive sequence generator have been purged of any non-deterministic states, then S2(F2)=S1(F1)=F1 = F2 Thus the comparator will be fed with two equal signals, and this can be detected by bistable B and used to change the switch to the CIRCU LATE position. After this has occurred, the receive sequence generator will continue in step with the send sequence generator without reference to the transmitted signal, and the Transmit clear data need no longer be suppressed.

This known system suffers from one serious drawback: How is the system to know when to put the switch SW back to the FILL position? This needs to be done if: (a) There has been a long break in transmission, so that relative timing errors have occurred.

(b) A second secure transmitter has taken over or has interrupted the first.

(c) If the logic hardware has made an error, so that the sequence is disturbed.

To satisfy requirement (a) is relatively easy, and requires some form of input-signal detector.

To satisfy (b) and (c) requires that something characteristic should be present in the clear data, so that its absence may be detected if the system is out of synchronism. This, in turn, may mean that some restrictions are placed on the clear data, and some of its digits may have to be forced to a known state.

The system of the present invention shown in Figure 2 obviates the need to take the decision "Is the system out of synchronisation?".

Referring now to Figure 2, the transmitter is identical to that of Figure 1. In the receiver the code received information signals Rx CODE are fed to contacts F of switches 200, 202 which switches are operated together. Though for simplification of the description the switches are referred to as mechanical switches it is preferable in a practical arrangement for the switches to be equivalent electronic switches and the term switch is to be interpreted as including both mechanical and electronic switches. It is thus arranged that one wiper is in contact with an F or FILL contact and one in contact with a C or CIRCULATE contact. The wipers of switches 200, 202 are respectively connected to the input of sequence generators 204, 206 the outputs of which sequence generators are each connected to one contact of both switches 208,210.The wiper of switch 208 is connected to an adder circuit 212 and the wiper of switch 210 to one input of a comparator 214 in which in the position of the switch as shown the output sequence of sequence generator 204 is compared with the input coded signal Rx CODE.

If an agreement between the sequences over a number of bits is found a signal is given to a bistable circuit 216 which bistable gives an output to change over the switches 200, 202, and 208 and 210. The output of the adder circuit 212 Rx CLEAR is, assuming synchronism is obtained between transmitter and receiver, identical to Tx CLEAR.

The switching is arranged so that there is always one sequence generator in the FILL mode and one in the CIRCULATE mode. As the diagram is drawn the upper generator 204 is filling and the lower 206 is circulating. The output of the filling register 204 is compared with its input to decide when it is in synchronism with the sending sequence generator. This will occur when the Tx clear Data has been suppressed or has been static for long enough for the non-deterministic states of the receive generator to be purged. (NB. In order to obtain a reliable decision that the two inputs to the comparator are the same as a result of synchronisation rather than by chance agreement it will normally be necessary to examine about 20 digits for agreement).

Once the comparator 214 detects agreement, the bistable 216 is toggled and all the switches 200, 202, 208, 210 are thrown to the other position. Thus the register 204 which has just synchronised is made to circulate, and is used to decrypt the incoming data, while the one 206 which was circulating is forced to start filling (whether or not it was already in synchronism). Thus the two receive sequence generators 204, 206 are used alternately to decrypt the message.

It will be seen that there is never a need to take the decision "Is the system out-ofsynchronisation?". Instead, this is replaced by a decision "Is the generator which is being filled in synchronism?". The hardware for this decision is already available (in the 'known' system - See Pages 285, 286 "Data Transmission" Bennett and Davey (McGraw-Hill) and also Proceedings of International Telemetering Conference Los Angeles 1970, Vol.VI, Pages 156, 157,163) and the decision can be taken without placing restrictions on the clear data other than the requirement for a sufficient length of supperessed data at the start of the message (at which time the output sequence of the sequence generator of the transmitting equipment of the system is transmitted unmodified to the receiving equipment).

WHAT WE CLAIM IS: 1. A receiver for receiving information transmitted digitally in coded form, including a first sequence generator, a second sequence generator, a two input digital comparator which produces an output signal when an agreement is obtained between a predetermined number of bits of a first and a second binary sequence received at its first and second input, switch means, having a first and a second condition, for connecting either the output of the first or the second sequence generator to the first input of the comparator for comparison with the receiver input signal and control means arranged to change over the switch means from one condition to the other condition in response to the output from the comparator.

2. A receiver for receiving information transmitted in digitally coded form substantially as described with reference to Figure 2 of the drawings accompanying the provisional specification.

3. A secure coded transmission system including a transmitter for coding information into a secure coded digital signal for transmission to a receiver, which is in accordance

Claims (1)

1. with claim 1.

   4. A secure coded transmission system substantially as described with reference to Figure 2 of the drawings accompanying the provisional specification.