GB1589639A - Television line output circuit - Google Patents

Description

(54) TELEVISION LINE OUTPUT CIRCUIT (71) We, PHILIPS ELECTRONIC AND ASSOCIATED INDUSTRIES LIMI TED, of Abacus House, 33 Gutter Lane, London, EC2V 8AH, a British Company, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement:- The present invention relates to a circuit arrangement for generating a line frequency sawtooth deflection current having a trace period and a retrace period through a deflection coil, said arrangement including a first sawtooth network comprising a first diode, said deflection coil, a trace capacitor and a retrace capacitor, a second sawtooth network comprising a second diode, a second coil, a second trace capacitor and a second retrace capacitor, the retrace period for the current when flowing through the second coil being approximately equal to the retrace period for the deflection current, the arrangement also including supply terminals for receiving a supply voltage from a source and a controlled switch which is non-conducing during the retrace period, said sawtooth networks being connected together such that the first and second diodes are connected in series with the same conductivity direction, the series arrangement of the diodes being connected in parallel across the controlled switch and control means for varying the voltage across one of the trace capacitors.

Such a circuit arrangement is described in our patent specification serial number 1,459,922 and may be used for providing correction for pin-cushion distortion in the East-West direction on television display tubes, for stabilisation against supply variations, or generally for obtaining any required variation of the voltage across the trace capacitor.

Figures 6 and 7 of our above mentioned patent specification show modifications of the circuits shown and described therein in which the ' S ' correction capacitor of the deflection circuit is formed by the capacitors Ct and C't. In such an arrangement the linearity of the line deflection can be improved where the ' S ' correction is modulated more by an East-West component than by the deflection current. This is also described in Philips' Application Information No.: 268, " All Transistor 1100 Colour Television" and in our further patent specification serial number 1,358,751.

The invention provides a circuit arrangement for generating a line frequency sawtooth deflection current having a trace period and a retrace period through a deflection coil as claimed in Claim 1 of patent specification No. 1,459,922 in which means are provided for maintaining the diode in the sawtooth network containing the second of the trace capacitors conducting during at least a part of the line scan period other than by the charge carried by the second of the trace capacitors. The means may in fact maintain the diode conducting during the whole of the scan period. In a particular construction of the invention, a switch may be connected to the junction of the first and second diodes which switch is closed during the line scan periods to apply a voltage of appropriate polarity to the junction of said diodes. The switch may be formed by a third diode poled in the appropriate direction, the electrode of the third diode not connected to the junction receiving, in operation, a line frequency pulse train whose markto-space ratio corresponds to the ratio between the retrace period and the trace period of each line period for maintaining the third diode conducting during the trace period.

The invention also provides a circuit arrangement for generating a line frequency sawtooth deflection current having a trace period and a retrace period through a deflection coil as claimed in Claim 1 of patent specification No.: 1,459,922 in which the trace capacitor for the first sawtooth network is formed by a plurality of capacitors one of which also constitutes the trace capacitor for the second sawtooth network, and further comprising a third diode one electrode of which is connected to the junction between said first and second diodes, a transformer the primary winding of which is connected in series with said controlled switch whilst the other elec trode of said third diode is serially connected with a secondary winding of said transformer and a load, the polarity of said third diode and the winding sense of said secondary winding being chosen such that in operation said third diode conducts during the trace period. The retrace capacitor for the second sawtooth network may be connected in parallel with the third diode. The load may be formed by a circuit which is energised by a voltage produced across the secondary winding and rectified by the third diode.

The circuit arrangement may be used to reduce ringing in one of the sawtooth networks at the start of a line scan period due to various circumstances in the circuit and/or may be used to keep one of the diodes in a sawtooth network conducting when due to a lack of charge on the trace capacitor it might become non-ronducting.

The above and other features of the invention will now be described with reference to the accompanying drawings in which: Figure 1 is a circuit diagram partially in block form of a television display apparatus incorporating a circuit arrangement according to the invention, and Figures 2 to 5 are diagrams of circuit arrangements also according to the invention.

The television display apparatus of Figure 1 is a modification of the apparatus shown in Figure 1 of our patent specification 1,459,922 and corresponding blocks and components have been given like references. The differences between the two figures are in the arrangement of the two sawtooth networks and the addition of certain components including an additional winding L3 on transformer T, a diode D3 and a capacitor C2. As in the publication Philips Application Information No. 268, " All Transistor 110 Colour Television " and our patent specification No.

1,358,751 the ' S ' correction is modulated more by the East-West component than by the deflection current and for this reason the capacitor C', of the lower sawtooth network is also included in the upper sawtooth network.

With no field frequency drive voltage from modulator M, at the junction X of components Li, R2 and C3, coil L' is adjusted so that all the line deflection coil current flows via the line deflection coil Lu and the coil L' in series, and none via the diode modulator.

For this to be so the pulse voltage across coil L' at Y must be equal to that developed across the winding L2 on transformer T. The diode modulator circuit then acts as a balanced bridge with windings L, and Lq and coils L2 and L' as the arms of the bridge. Under these conditions the d.c. voltage across capacitor C2 will be the same as that at X. Let this be VmO Under these conditions the coils L2 and L' are in series. Current flows through diodes D and D' in the energy recovery period which period is the first part of the trace period before current reversal as shown by the arrows a and b, diode D passing the current through coil L' and diode D the current through deflection coil L11. Forward scan current flows as normal during the second part of the trace period after current reversal via coils L, and L' in series and the transistor Tr.

During the flyback (retrace) period coils L2 and L' in series form a tuned circuit with retrace capacitor Cr and whose period of oscillation is twice the flyback (retrace) period.

Diode D' and the additional diode D3 also conduct during the trace period and carry the scan rectified current for a drain and provides a source of low voltage d.c. supply which as shown can be used as the supply for the modulator M1.

This situation gives the minimum scan amplitude case, and the effective average (scan) voltage across the deflection coil is VB - Vmo.

Thus during the trace period an effective average voltage exists across coil L' equal to Vm0 . . im = Vmo L' where ts is the scan time.

Also the voltage across deflection coils L2 during the trace period is equal to VBV,nO 2u . iV = VB - Vmo Ly and since i' = i2 for the above case: U L' = Vmo L2 (VBVmO) and hence the required L' value is known.

As the drive voltage V from modulator M1 is reduced below Vmo then the average value of the voltage waveform at the junction of diodes D and D' is reduced. However the voltage here is at earth during scan period due to diode D' conducting, so also must the peak flyback voltage be reduced at junction of diodes D and D' as the average voltage is reduced. Thus the peak voltage at Y must also be reduced and the effective scan voltage across coil L' is also reduced and takes the value of the drive voltage at X from modulator M1. The voltage across the line deflection coil L2 during scan therefore increases (since it is (Va - V,)) ) as the East-West modulating drive voltage V is reduced.

Thus the deflection coil current i2, will increase, and the modu ator choke (coil L') current i' will decrease, and with i2 greater than i', iy - i' must flow via diode 1)' to make up the difference, this current flowing via diode, D', deflection coil Ly and transistor Tr. Energy recovery current still flows during the energy recovery period in diodes D and D', but that in D' will decrease while that in D increases since current i' decreases and iv increases.

In the limit case where V = 0 and also i = O, all the forward scan deflection coil current then flows via diode D', deflection coil Ly and transistor Tr and no energy recovery current flows in diode D' (since im = 0) and energy recovery current flows only in D, Ly circuit.

In this case voltage Va exists across L2 during scan, which gives the maximum scan amplitude for the system. Thus by controlling V,n the amplitude of current in the deflection coil L2 can be controlled.

During the flyback (retrace) period when voltage at X is at earth potential due to the drive voltage Vm being substantially zero flyback current flows through the resonant circuit formed by the components Ly, C'tC',. winding L3, C2, C, and Ct. Capacitors Ct and C't are very large capacitors, but capacitor C' is chosen so that it has an effective reflected value in parallel with the main flyback capacitor C,., and thus affects the flyback time.

But, as explained earlier for the case of V, = V,, flyback current flows in La, L' and C, but not in C',. Thus the effect of L' can be exchanged with C'r as the East-West drive voltage V, is modulated, and by care ful selection of C',, it is possible to keep the flyback time constant as Vm, and hence the scan amplitude is varied. Also, V, is varied at field rate parabolically to correct for East West pin cushion distortion.

For all values of V, diode D' acts as a scan rectifier diode and a diode modulator diode, and D2 acts as a scan rectifier diode.

Capacitor Ct is the main ' S ' correction capacitor, but capacitor C't carries the diode modulator current and acts as a modulated S S ' correction capacitor, giving more ' S correction at the centre of scan, when diode modulator current takes its largest value.

A range of control over the deflection coil current i2 exists as the East-West drive voltage is varied from V,00 to O. In any circuit there will be a certain required amount of raster correction, width control variation, keystone control variation and anti-picture breathing (picture width stabilization against picture tube beam current) control variation taking into account tolerances and spreads, and this means a certain required amount of drive voltage for the diode modulator, which will be the voltage V, The circuit must not have a lower voltage range on the East-West drive than V since this will not give the required maximum range of control via the diode modu lator taking in the above conditions. Since also the voltage obtained from the scan rectified supply in V (for a perfectly balanced bridge) then the circuit can only supply low voltage supplies equal to or larger than the required minimum range of the diode modulator drive voltage V"", (unless we use resistive droppers, zener diodes, etc.). It is possible to use larger voltages than V , but the diode modulator choke L' must then be designed to balance with these large voltages. This would be a larger value of L' than for optimum case of The present circuit arrangement combines the advantage of the modulator circuit in our patent specification No. 1,459,922 which has become known as the high voltage diode modulator and the modulator as described in Mullard Application Note TP. 1444 "20 AX for 110 Colour Television, 20 AX Deflection and supply circuits" with reference to Figure 8 and which has become known as the low voltage diode modulator.

With the low voltage diode modulator a minimum drain requirement is necessary across the l.t. supply in order to prevent the supply voltage increasing, and this drain had to be greater than or equal to the average maximum energy recovery current value since this current flows via diode D2 (diode D would not be present). In practice with the present circuit a much smaller minimum drain is required on the l.t. supply since energy recovery current flows now via diode D and diode D2 is a scan rectifier diode in order to prevent this supply from increasing.

With diode D2 conducting immediately after the end of the flyback period to provide an l.t. scan rectified supply then any ringing present immediately after the end of flyback due to the diode modulator circuit is rapidly damped out. The ringing, if present, could be coupled or radiated such that it could be picked up in the signal processing stages of a colour T.V. receiver to produce interference therein and produce noticeable ringing at the beginning of scan on a picture screen raster.

The circuit arrangement thus has the advantage of eliminating or at least reducing such ringing.

The circuit arrangement was found to be tolerant to spreads in components, and even when the diode modulator was detuned the above mentioned ringing was negligible. The circuit arrangement is easily tunable by using a variable choke for L', and balancing the bridge with this variable choke.

As described in relation to Figure 7 of our above mentioned patent specification No.

1,459,922, it is possible for the current through the diode D' to attempt to become negative and for the diode to become non-conducting before the end of the energy recovery period and during a part of the trace period when transistor Tr is not forward biased which would lead to an undefined voltage at the junction of diodes D and D' and hence across the line deflection coil LZ,. Such a situation can occur when the base of transistor Tr is driven from a transformer in a switched mode power supply where the resulting base drive may have a variable pulse width e.g. as in our patent specication No. 1,309,661 or in the type of combined switch mode power supply/line deflection stage described in I.E.E.E. Transactions on Broadcast and Television Receivers, August 1972, Volume BTR-18, No. 3, pages 177 to 182 and others of our patent specifications including 1,459,922 (see Figure 3). With such circuits deflection current only passes through the switching transistor during the second half of the scan period as during the first half of the scan period deflection current passes through a separate diode. Figure 7 of patent specification No. 1,459,922 offers one solution to the above problem. However it has been found that the circuit arrangement of the present invention also solves this problem. In the arrangement of Figure 1 described above diodes D' and D2 conduct during the whole of the trace (scan) period due to the scan rectifying action of these diodes and then D' is maintained in conduction even when the charge stored in C't causes a change in polarity of the current in the second (lower) sawtooth network.

Considering the use of the invention in its basic form what is required is to impress a current through D' which is larger than the largest possible value of current of opposite polarity in the first half of the scan period.

A means for achieving this is shown in Figure 2 which is an extract from a circuit similar to that of Figure 1 and where common references have been used to indicate like components between the two figures. In Figure 2 diode D and winding L2 have been replaced by a switch S and voltage source Vs, switch S being closed during the scan period though of course it need only be closed during the first half of the scan period.

In a more practical form of circuit shown in Figure 3 the switch is replaced by the diode D, which is switched by the line frequency wave form present across the winding L3 connected to a load circuit Z and which provides the supply to maintain D' conducting during the scan period. In this Figure the capacitor C'r is connected to a tap on L1 as in Figure 7 of specification No. 1,459,922.

Figure 4 is a modification of Figure 3, the capacitor C', now being connected across the diode D3 so eliminating the need to provide a tap on winding L'. In television receivers the low voltage d.c. supply for the lower voltage circuits is often obtained by providing a winding on the line transformer and rectifying the line frequency waveform appearing across the winding during the scan period.

As diodes D' and D3 are conducting during the scan period it is possible to derive such a supply from the lower end of winding L3.

Such a circuit is shown in Figure 5 which is basically similar to the circuit of Figure 1, the capacitor C2 and the circuits energised by the supply forming the load Z. When used in such a manner it will be seen that the circuit of the present invention does not require any additional components as it would previously have been necessary to provide the diode and the extra winding simply for power supply purpose.

WHAT WE CLAIM IS: 1. A circuit arrangement for generating a line frequency sawtooth deflection current having a trace period and a retrace period through a deflection coil as claimed in Claim 1 of patent specification 1,459,922 comprising means for maintaining, in operation the diode in the sawtooth network containing the second of the trace capacitors conducing during at least part of the trace period other than by the charge carried by the second of the trace capacitors.

2. A circuit arrangement as claimed in Claim 1, in which said means comprises a switch connected to the junction of said first and second diodes, said switch being adapted to be closed during the trace periods for applying a voltage of appropriate polarity to the said junction.

3. A circuit arrangement as claimed in Claim 2, in which said switch comprise, a third diode poled in the appropriate dire tion, the electrode of said third diode not connected to said junction receiving, in operation, a line frequency pulse train whose mark-to-space ratio corresponds to the ratio between the retrace period and the trace period of each line period for maintaining the third diode conducting during the trace period.

4. A circuit arrangement for generating a line frequency sawtooth deflection current having a trace period and a retrace period through a deflection coil as claimed in Claim 1 of patent specification No. 1,459,922 in which the trace capacitor for the first sawtooth network is formed by a plurality of capacitors one of which also constitutes the trace capacitor for the second sawtooth network, and further comprising a third diode one electrode of which is connected to the junction between said first and second diodes, a transformer the primary winding of which is connected in series with said controlled switch whilst the other electrode of said third diode is serially connected with a secondary winding of said transformer and a load, the polarity of said third diode and the winding sense of said secondary winding being chosen such that in operation said third diode conducts during the trace period.

5. A circuit arrangement as claimed in Claim 4, in which the retrace capacitor for the second sawtooth network is connected in parallel with said third diode.

6. A circuit arrangement as claimed in Claim 4 or 5, in which said load is formed by a circuit which is energised by a voltage produced across said secondary winding and

**WARNING** end of DESC field may overlap start of CLMS **.

Claims (7)

**WARNING** start of CLMS field may overlap end of DESC **. variable pulse width e.g. as in our patent specication No. 1,309,661 or in the type of combined switch mode power supply/line deflection stage described in I.E.E.E. Transactions on Broadcast and Television Receivers, August 1972, Volume BTR-18, No. 3, pages 177 to 182 and others of our patent specifications including 1,459,922 (see Figure 3). With such circuits deflection current only passes through the switching transistor during the second half of the scan period as during the first half of the scan period deflection current passes through a separate diode. Figure 7 of patent specification No. 1,459,922 offers one solution to the above problem. However it has been found that the circuit arrangement of the present invention also solves this problem. In the arrangement of Figure 1 described above diodes D' and D2 conduct during the whole of the trace (scan) period due to the scan rectifying action of these diodes and then D' is maintained in conduction even when the charge stored in C't causes a change in polarity of the current in the second (lower) sawtooth network. Considering the use of the invention in its basic form what is required is to impress a current through D' which is larger than the largest possible value of current of opposite polarity in the first half of the scan period. A means for achieving this is shown in Figure 2 which is an extract from a circuit similar to that of Figure 1 and where common references have been used to indicate like components between the two figures. In Figure 2 diode D and winding L2 have been replaced by a switch S and voltage source Vs, switch S being closed during the scan period though of course it need only be closed during the first half of the scan period. In a more practical form of circuit shown in Figure 3 the switch is replaced by the diode D, which is switched by the line frequency wave form present across the winding L3 connected to a load circuit Z and which provides the supply to maintain D' conducting during the scan period. In this Figure the capacitor C'r is connected to a tap on L1 as in Figure 7 of specification No. 1,459,922. Figure 4 is a modification of Figure 3, the capacitor C', now being connected across the diode D3 so eliminating the need to provide a tap on winding L'. In television receivers the low voltage d.c. supply for the lower voltage circuits is often obtained by providing a winding on the line transformer and rectifying the line frequency waveform appearing across the winding during the scan period. As diodes D' and D3 are conducting during the scan period it is possible to derive such a supply from the lower end of winding L3. Such a circuit is shown in Figure 5 which is basically similar to the circuit of Figure 1, the capacitor C2 and the circuits energised by the supply forming the load Z. When used in such a manner it will be seen that the circuit of the present invention does not require any additional components as it would previously have been necessary to provide the diode and the extra winding simply for power supply purpose. WHAT WE CLAIM IS:

1. A circuit arrangement for generating a line frequency sawtooth deflection current having a trace period and a retrace period through a deflection coil as claimed in Claim 1 of patent specification 1,459,922 comprising means for maintaining, in operation the diode in the sawtooth network containing the second of the trace capacitors conducing during at least part of the trace period other than by the charge carried by the second of the trace capacitors.

2. A circuit arrangement as claimed in Claim 1, in which said means comprises a switch connected to the junction of said first and second diodes, said switch being adapted to be closed during the trace periods for applying a voltage of appropriate polarity to the said junction.

3. A circuit arrangement as claimed in Claim 2, in which said switch comprise, a third diode poled in the appropriate dire tion, the electrode of said third diode not connected to said junction receiving, in operation, a line frequency pulse train whose mark-to-space ratio corresponds to the ratio between the retrace period and the trace period of each line period for maintaining the third diode conducting during the trace period.

4. A circuit arrangement for generating a line frequency sawtooth deflection current having a trace period and a retrace period through a deflection coil as claimed in Claim 1 of patent specification No. 1,459,922 in which the trace capacitor for the first sawtooth network is formed by a plurality of capacitors one of which also constitutes the trace capacitor for the second sawtooth network, and further comprising a third diode one electrode of which is connected to the junction between said first and second diodes, a transformer the primary winding of which is connected in series with said controlled switch whilst the other electrode of said third diode is serially connected with a secondary winding of said transformer and a load, the polarity of said third diode and the winding sense of said secondary winding being chosen such that in operation said third diode conducts during the trace period.

5. A circuit arrangement as claimed in Claim 4, in which the retrace capacitor for the second sawtooth network is connected in parallel with said third diode.

6. A circuit arrangement as claimed in Claim 4 or 5, in which said load is formed by a circuit which is energised by a voltage produced across said secondary winding and

rectified by said third diode.

7. A circuit arrangement for generating a line frequency sawtooth deflection current through a deflection coil substantially as herein described with reference to the accompanying drawings.