GB1589616A

GB1589616A - Electronic timepieces

Info

Publication number: GB1589616A
Application number: GB3636577A
Authority: GB
Original assignee: Citizen Watch Co Ltd
Current assignee: Citizen Watch Co Ltd
Priority date: 1976-09-01
Filing date: 1977-08-31
Publication date: 1981-05-13

Description

(54) ELECTRONIC TIMEPIECES (71) We, CITIZEN WATCH COM PANY LIMITED, a corporaton organized under the laws of Japan, of No. 9-18, 1-chome, Nishishinjuku, Shinjuku-ku, Tokyo, Japan, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement: This invention relates to electronic timepieces.

In recent years there has been a sudden increase in the popularity of so-called digital display electronic timepieces which are equipped with a crystal controlled oscillator as a time standard and which display time by means of an electro-optical display device utilizing liquid crystals for example. In timepieces of this type, it is possible to effect control even of additional functions through electronic circuitry without requiring the installation of movable parts other than switches which serve as external control members.Accordingly, there has been a growing tendency towards a diversification of timepiece construction in conformance to customer demand since it is now possible to readily realize electronic timepieces which are equipped with additional functions such as a calendar display function, chronograph function, and alarm function which supplement the ordinary time display function.

The first problem which this increase in the number of additional functions has given rise to is concerned with the structure of means for selecting the function modes of the timepiece. In other words, in a timepiece having a plurality of function modes including, in addition to a time display function, a calendar display function, chronograph function and alarm function, it is necessary to provide an external control switch for function mode selection so that the wearer of the timepiece can optionally select any display mode. Thus, the problem mentioned above relating to means for selecting the function modes specifically involves minimizing the number of external control switches while making it possible for the wearer to readily operate the switches without difficulty.

On the other hand, there is also a second problem which must be solved relating to ways of obtaining a maximum restriction upon an increase in the types of electronic circuits which are employed in timepieces for the purpose of diversifying combinations of the additional functions. More specifically, it is extremely expensive to manufacture on a small scale a wide variety of integrated circuits, which are generally of the C-MOS or IIL type, for use in the electronic circuitry of timepieces. Furthermore, the preparation of diverse circuitry complicates production management and raises costs with respect to the manufacture of timepiece modules as well.

The present invention seeks to provide an electronic circuit for a timepiece which will make it possible to overcome the abovementioned problems.

According to the present invention, there is provided an electronic timepiece having an external control member arranged to produce output pulses upon actuation of the external control member and a mode selection circuit, said mode selection circuit comprising means for generating a plurality of mode selection signals in a sequential and cyclic manner in response to the output pulses generated by said external control member; and a mode number control terminal connected to said mode selection signal generating means and adapted to be preset to one of first and second predetermined logic levels during assembly of the timepiece; said mode selection signal generating means being responsive to said first and second predetermind logic levels to inhibit generation of a preselected one of said plurality of mode selection signals so that the number of said mode selection signals generated in the cyclic manner by said mode selection signals generating means varies in dependence on which of said predetermined logic levels is preset.

Embodiments of the present invention will now be described with reference to the accompanying drawings, in which: Figure I is a block diagram of the circuit of a first electronic timepiece in accordance with the present invention; Figure 2 is a circuit diagram which represents the specific construction of a function mode selection circuit included in the electronic circuit shown in Figure 1; Figure 3 is a block diagram of the circuit of a second electronic timepiece according to the present invention; Figure 4 is a detailed wiring diagram showing a correction mode selection circuit and a correction signal input circuit shown in Figure 3; Figure 5 is a plan view of the electronic timepiece whose circuit is shown in Figure 3; and Figure 6 is a plan view of another electronic timepiece according to the invention and incorporating the electronic circuit shown in Figure 3.

Figure 1 is a block wiring diagram of the circuit of a timepiece in accordance with the invention, and Figure 2 is a circuit diagram which represents the specific construction of a function mode selection circuit which constitutes a part of the circuit illustrated in Figure 1. The drawings are useful in describing two cases, one in which the circuit is employed in a 3-function timepiece including a calendar display function and alarm function in addition to a time display function, and one in which the circuit is employed in a 2-function timepiece including only a calendar display function in addition to the time display function.

With reference to Figure 1, reference numeral 10 denotes a crystal controlled oscillator to provide a relatively high frequency signal, 12 a frequency divider dividing down the relatively high frequency signal to provide a low frequency signal. 14 a time counter to provide time data in response to the low frequency signal and 16 a calendar counter to provide calendar data.

Reference numeral 18 designates an alarm memory the output side of which is connected to the input side of a coincidence detector 20 as is the output side of time counter 14. These circuits are arranged such that a buzzer 22 will be actuated by means of a buzzer driver circuit 24 which is supplied with an alarm coincidence signal A as produced by the coincidence detector 20 when there is coincidence between the content of time counter 14 and alarm memory 18.

The timepiece is equipped with three push-button switches S1-S3 which serve as external control switches. Function selection switch S1 is connected to function mode selection circuit 26, and digit selection switch S2 as well as correction signal input switch S3 are connected to correction mode control circuit 28. Further, reference numeral 30 denotes a display selection circuit, 32 a decoder/driver, and 34 an electro-optical display device. A group of function selection signals 26a produced by the function mode selection circuit 26 are applied to the input side of correction mode control circuit 28 and to the input side of the display selection circuit 30 at the function selection signal input terminal 30a thereof.In accordance with this arrangement, display selection circuit 30 selects either an output from the time counter 14, calendar counter 16 or alarm memory 18 and applies it to the input side of the decoder/driver 32. In addition, a group of correction signals 28a, 28b, 28c as produced by correction mode control circuit 28 are applied to the correction signal input terminals of time counter 14, calendar counter 16 and alarm memory 18, respectively.

In a similar manner, a group of digit selection signals 28d produced by correction mode control circuit 28 is applied to the input side of display selection circuit 30 at the digit selection signal input terminal 30b thereof. As a result, the display selection circuit 30 extinguishes the display of display device 34 except for the digit which is to be corrected depending on the display correction mode of the timepiece.

With reference to the function mode selection circuit 26 shown in Figure 2, one terminal 36 of function selection switch S, is connected to the input side of differentiating circuit 40 the output side of which is connected to toggle terminal T of flip-flop (hereafter referred to as FF) 42. The Q output terminal of FF 42 is connected to toggle terminal T of FF 44, INHIBIT (hereafter referred to as INH) circuit 46, and to one terminal on the input side of AND gate 54. The Q output terminal of FF 42 is connected to one terminal on the input side of AND gate 52 and to INH circuit 56.

The Q output terminal of FF 44 is connected to the input side of INH circuits 46, 56 and the Q output terminal is connected to the input side of OR gates 48, 50. Function mode number control terminal 38 is connected to the remaining input terminals of OR gates 48, 50 and to the INH input terminals of INH circuits 46, 56, the outputs produced by the OR gates 48, 50 being connected to the remaining input terminals of AND gates 52, 54, respectively. Finally, the output side of INH circuit 46 is connected to the reset terminal R of FF 42, 44, and the output signals obtained from AND gates 52, 54 and INH circuit 56 are applied, as the previously mentioned function selection signals 26a, to the function selection signal input terminals 30a of the display selection circuit 30 and to the input side of the correction mode control circuit 28.

The operation of the present circuit will now be described in terms of logic levels, wherein H will denote an H (high) logic level and L an L (low) logic level.

With regard to the outputs obtained from AND gates 52, 54 and INH circuit 56, a time display mode is designated when only the output provided by AND gate 52 is at an H level, a calendar display mode is designated when only the output of AND gate 54 is at an H logic level, and an alarm setting mode is designated only when the output of INH circuit 56 is at an H logic level. Moreover, the function mode number control terminal 38 is a terminal for presetting the operation of function mode selection circuit 26 by setting the terminal 38 to H or L levels during assembly depending upon whether the circuit of the present embodiment is employed in a 3-function timepiece or 2function timepiece.

A description of the circuit operation will first be given for a 3function timepiece in which the terminal 38 is held electrically at an L logic level. In this case, when both FF 42 and 44 are in a reset state, i.e., when their Q output terminals are at an H level, only the output side of AND gate 52, from among AND gates 52, 54 and INH circuit 56, is at an H level, whereby the function mode of the timepiece is the time display mode. Accordingly, if digit selection switch S2 and correction signal input switch S3 are operated in combination with the timepiece in this mode, it is possible to perform a correction of the displayed time.Next, if function selection switch S, is closed momentarily once, a single pulse produced by differentiating circuit 40 sets FF 42 and resets FF 44 so that, of AND gates 52, 54 and INH circuit 56, only the output side of AND gate 54 attains an H logic level; hence, the mode of the timepiece shifts from the time display mode to the calendar display mode. Operation of the digit selection switch S2 and correction signal input switch S3 with the timepiece in this mode allows the calendar display to be corrected.If function selection switch S, is closed momentarily a second time, a single pulse produced by diferentiating circuit 40 resets FF 42 and sets FF 44 so that, of AND gates 52, 54 and INH circuit 56, only the output of INH circuit 56 attains an H level; hence, the mode of the timepiece shifts from the calendar display mode to the alarm setting mode. Operation of the digit selection switch S, and correction signal input switch S3 allows setting of the alarm timing.Now, if function selection switch Sl is closed momentarily closed a third time, the single pulse produced by differentiating circuit 40 instantaneously sets both FF 42 and FF 44 while the output side of INH circuit 46 simultaneously attains an H logic level so that FF 42, 44 are immediately returned to the reset state; hence, the mode of the timepiece is restored from the alarm setting mode to the original time display mode. It thus follows that if the function mode number control terminal 38 is controlled so as to hold it electrically at an L logic level, the three function modes of the timepiece can be made to shift in a cyclic manner by operating the function selection switch S,. This makes it possible to easily select any one of the three function modes.

Next, a description of circuit operation will be given for a 2-function timepiece in which the terminal 38 is held electrically at an H logic level during assembly of the timepiece. In this case, the output side of both INH circuits 46, 56 is constantly held at an L level, thereby inhibiting the alarm function mode. Furthermore, resetting of FF 42, 44 is inhibited by the output of INH circuit 46, and the output side of OR gates 48, 50 is constantly held at an H logic level.

As a result, the output signals delivered by AND gates 52, 54 are determined by the state of FF 42 alone. Thus, differentiating circuit 40 produces a single pulse each time function selection switch Sl is closed momentarily, thereby resetting and setting FF 42 alternatively in a repetitive manner.

In consequence, the timepiece is selectively placed in either the time display mode or calendar display mode in an alternative manner responsive to the H logic level which appears alternately at the output side of AND gates 52, 54. It is also possible to correct the display of each of the display modes by operating digit selection switch S2 and correction signal input switch S. Thus, if the function mode number control terminal 38 is preset so as to hold it electrically at an H logic level, the two function modes of the timepiece can be made to shift alternatively and in a cyclic manner by operating the function selection switch S,; hence, it is possible to easily select either of the two available modes.Accordingly, when designing a 2-function timepiece, the function mode number control terminal 38 is held electrically at an H level, and it is permissible to eliminate the buzzer 22 as well as its driver circuit 24 composed of a bi-polar transistor, booster coil and the like.

The circuit constructed as described above can be used jointly in either a 3-function or 2-function timepiece and permits the respective function modes to selected by means of an extremely simple operation. Moreover, even when the circuit is utilized in a 2-function timepiece the appearance of an unused blank mode is inhibited in the cyclic step-by-step shifting of function modes so that the wearer of the timepiece will not be confused by the blank mode.

The function selection circuit described thus above is constructed so that it is possible to change the number of function modes which can be selected by a cyclic step-wise shift by presetting a control terminal of the timepiece function mode selection circuit. The present invention thus makes it possible to provide an extremely simple structure for an electronic function selection circuit in a multi-function timepiece with an easily operable function mode selection system.

Although the electronic function selection circuit of the first embodiment is assumed to have been used in a 2-functon and 3function timepiece, it goes without saying that the circuit can be modified to select combination of various additional functions.

In other words, by way of example, a circuit for two, three or four functions can be used commonly by providing two function mode number control terminals.

Finally, in the first embodiment, the function mode is related to both the display mode of the display device and the operating mode of the display correction switch.

However, it is acceptable if the function mode is related to only one of these two factors. Further, in relation to the digit selection circuit, the same structure as that of the first embodiment can be applied for a case where it is necessary to prevent the occurance of a blank digit selection mode.

Figure 3 shows a block wiring diagram of a second timepiece in accordance with the invention, and Figure 4 shows a circuit diagram which represents the specific construction of a correction mode selection circuit and a correction signal input circuit which form a part of the circuit system illustrated in Figure 3. Figure 5 is a plan view of the external appearance of a largesize men's digital timepiece which is equipped with a calendar display section and makes use of the electronic circuit shown in Figure 3. Figure 4 is a plan view of the external appearance of small-size women's digital timepiece which is not equipped with a calendar display section but does make use of the circuit shown in Figure 3.

With reference to Figure 3, reference numeral 60 denotes a crystal controlled oscillator and 62 a frequency divider the output of which is applied successively to the input side of a seconds counter 64, minutes counter 66 and hours counter 68 which form a time counter 69. Reference numerals 70 and 72 designate a date counter and day of the week counter, respectively, which form a calendar counter 73. Outputs obtained from the time counter 60 and calendar counter 73 are applied via display selection circuit 78 to the input side of decoder driver circuit 80 which drives the liquid crystal display device 82.

The timepiece in this illustrated embodiment is equipped with two push-button switches S2 and S3 which serve as external control switches. Of these, one terminal 84 of correction mode selection switch S2 is connected to correction mode selection circuit 74, while one terminal 86 of correction signal input switch S3 is connected to correction signal input circuit 76. A group of correction mode selection signals 74b produced by the correction mode selection circuit 74 are applied to the input side of correction signal input circuit 76 and to the input side of display selection circuit 78.As a result, only a display digit to be corrected, i.e., only one selected from among the display elements of liquid crystal display device 82, is caused to flash by means of display selection circuit 78 regardless of the display correction mode of the timepiece.

Finally, the output side of the correction signal input circuit 76 is conncted to the time counter and calendar counter.

With reference to the correction mode selection circuit 74 shown in Figure 4, one terminal 84 of correction mode selection switch S2 is connected to the input side of differentiating circuit 90 the output side of which is connected to toggle terminal T of FF 92. The Q output terminal of FF 92 is connected to toggle terminal T of FF 94, and the Q output terminal of FF 94 is connected to one terminal on the input side of AND gate 96. The output side of AND gate 96 is connected to toggle terminal T of FF 98, and the Q output terminal of FF 92, the Q output terminal of FF 94, and the Q output terminal of FF 98 are connected to the input side of AND gate 100. The output side of AND gate 100 is connected to the reset teminals R of FF 92 and FF 94 and to one terminal of the input side of OR gate 104 the output side of which is connected to the reset terminal R of FF 98. Correction mode number control terminal 74a is connected to the remaining input terminal of AND gate 96 and to the input side of inverter 102 the output side of which is connected to the remaining input terminal of OR gate 104.

As may be appreciated from Figure 4, either the Q or Q output terminals of FF 92, 94, 98 are connected to the input side of AND gates 106 - 114 which produce the correction mode selection signals that are applied to the input side of display selection circuit 78 and fed to one input terminal of respective AND gates 118 - 126 which constitute the correction signal selection circuit 76.

One terminal 86 of correction signal input switch SX is connected to the input side of differentiating circuit 116 the output side of which is connected to the remaining input terminals of AND gates 118 - 126. Finally, the output sides of AND gates 118 - 126 are connected to the correction signal input terminals of seconds counter 64, minutes counter 66, hours counter 68, date counter 70 and day of the weeks counter 72.

In the circuit of the this illustrated embodiment, any one of the correction modes from among the seconds zeroing, minutes correction, hours correction, date correction or day of the week correction modes is selected in response to an H logic level which will appear at the output side of any one AND gate from among the corresponding AND gates 106 - 114. The timepiece is in a normal state of operation when the output side of each of the AND gates is at an L logic level. Moreover, the correction mode number control terminal 74a is a terminal for presetting the correction mode number depending upon whether the circuit is employed in a timepiece having a calendar display section 130, as shown in Figure 5, or in a timepiece which does not possess such a display section, as illustrated in Figure 6.

A description of the circuit operation will first be given for a timepiece equipped with a calendar display section in which the correction mode number control terminal 74a is held electrically at an H logic level. In this case, since the output side of inverter 102 is held at an L level and AND gate 96 is held ON, there is a direct connection between the output side of AND gate 100 and reset terminal R of FF 98, and between the Q output terminal of FF 94 and toggle terminal T of FF 98. In consequence, FF 92, 94, 98 and AND gate 100 form a divide-bysix cyclic counter. The content of this counter is varied step-wise in a successive manner by means of a correction mode selection pulse produced one at a time by differentiating circuit 90 each time correction mode selection switch S2 is closed.

Accordingly, taking as a relative starting point the state in which the outputs obtained from the AND gates 106, 108, 110, 112, 114 are each at an L level, i.e., the state in which the timepiece is in the normal operating mode, it is possible to select any single correction mode from among the normal operating state and five correction modes by causing an H level to appear cyclically in order at the output of only one of the AND gates 106, 108, 110, 112, 114 responsive to the changes in the content of the divide-bysix cyclic counter.As a result, only one of the AND gates 118 - 126 of the correction signal input circuit 76 will turn ON, namely that particular one corresponding to the selected mode, i.e., depending upon which of the AND gates 106, 108, 110, 112, 114 has produced an H level output; it is therefore possible to perform the desired correction as selected by correction signal input switch 83.

Next, a description of circuit operation will be given for a timepiece which is not equipped with a calendar display section, the correction mode number control terminal 74a being preset at an L level. In this case, since the output side of inverter 102 is at an H level and AND gate 96 is held OFF, FF 98 is constantly held in a reset state and AND gate 100 is constantly held at an L logic level. In consequence, FF 92, 94 construct a cyclic divide-by-four counter, and the two AND gates 112, 114 the input sides of which are connected to the Q output terminal of FF 98 are constantly held at an L logic level; accordingly, selection of the data correction mode and day of the week correction mode is inhibited.Further, since the Q output terminal of FF 98 is constantly held at an H level, it is clear that AND gates 106 - 110 produce output signals the states of which are determined by the states of FF 92, 94, namely by the content of the abovementioned cyclic divide-by-four counter. In consequence, the content of this counter is varied step-wise in a successive manner each time correction mode selection switch S2 is closed, and the states of the output signals produced by AND gates 106, 108, 110 change accordingly.As a result, taking as a relative starting point the state in which the outputs obtained from the AND gates 106, 108, 110 are each at an L level, i.e., the state in which the timepiece is in the normal operating mode, it is possible to select any single correction mode from among the normal operating state and three correction modes by causing an H level to appear cyclically in order at the output of only one of the AND gates 106, 108, 110. Furthermore, AND gates 124, 126 of correction signal input circuit 76 are constantly held OFF, and only one of the AND gates 118, 120, 122 will turn ON, namely that particular one corresponding to the selected mode; hence, it is possible to correct the display by means of correction signal input switch 53.

Thus, according to the circuit construction of this illustrated embodiment of Figures 3 and 4, either five correction modes or three correction modes may be employed based upon whether the correction mode number terminal 74a is preset at an H or L logic level; accordingly, it is possible to employ the same circuit in a timepiece which is or is not equipped with a calendar display section.

The correction mode selection circuit is designed so as to select any single correction mode from a plurality of correction modes by shifting step-wise in a successive and cyclic manner the correction mode of the timepiece display each time a single correction mode selection pulse is produced. More specifically, the circuit is characterized by a construction which makes it possible to change the number of correction modes selected by a cyclic shift by presetting, a control terminal of the correction mode selection circuit.

The same correction mode selection circuit can be used in electronic timepieces having differing numbers of display functions while the correction operation is capable of being easily performed by means of a small number of external control switches for the purpose of display correction.

Finally, in the illustrated second embodiment, a timepiece has been provided with a time display section and calendar display section separately installed. However, the connection mode selection circuit may also be applied to a timepiece which is constructed such that both display modes occupy the same display section, the desired mode being chosen by appropriately switching over the display.

WHAT WE CLAIM IS: 1. An electronic timepiece having an external control member arranged to produce output pulses upon actuation of the external control member and a mode selection circuit, said mode selection circuit comprising means for generating a plurality of mode selection signals in a sequential and cyclic manner in response to the output pulses generated by said external control member; and a mode number control terminal connected to said mode selection signal generating means and adapted to be preset to one of first and second predetermined logic levels during assembly of the timepiece; said mode selection signal generating means being responsive to said first and second predetermined logic levels to inhibit generation of a preselected one of said plurality of mode selection signals so that the number of said mode selection signals generated in the cyclic manner by said mode selection signals generating means varies in dependence on which of said predetermined logic levels is preset.

2. An electronic timepiece according to claim 1, in which said mode selection signal generating means comprises a plurality of flip-flops responsive to the output pulses produced by said external control member to generate said plurality of mode selection signals.

3. An electronic timepiece according to claim 2, in which said mode selection signal generating means further comprises gate means connected to said mode number control terminal for operatively coupling and decoupling said plurality of flip-flops in dependence on said one of said first and second predetermined logic levels.

4. An electronic timepiece according to claim 1, in which said mode selection signal generating means comprises a plurality of output signal generating means composed of a plurality of flip-flops and gate means to produce output signals in response to said output pulses, at least one of said gate means being connected to said mode number control terminal, and in which said mode selection signal generating means comprises a series of gate means responsive to said output signals and adapted to provide said mode selection signals, at least one of said series of gate means being adapted to be inhibited to provide a mode selection signal when said mode number control terminal is preset to one of first and second predetermined logic levels.

5. An electronic timepiece according to claim 1, which comprises an oscillator circuit for producing a relatively high frequency signal, a frequency divider producing a low frequency signal, in response to said relatively high frequency signal, and a plurality of counter means to provide output data in a plurality of function modes, at least one of said counter means being responsive to said low frequency signal, a display section circuit connected to said mode selection circuit, display means for selectively displaying said output data, and a correction mode control circuit connected to said mode selection circuit and said counter means whereby selecting one of said plurality of function modes in response to said mode selection signals effects correction and displaying of selected output data.

6. An electronic timepiece according to claim 1, which comprises an oscillator circuit for producing a relatively high frequency signal, a frequency divider for producing a low frequency signal, counter means responsive to said low frequency signal to provide various time data, display means for displaying said time data, a correction signal input member adapted to provide output pulses each for one actuation of said correction signal input member, and a correction signal input circuit connected between said mode selection signal generating means and said counter means and responsive to said mode selection signals for selecting one of a plurality of time correction modes to be corrected by said correction signal input member.

7. An electronic timepiece incorporating a mode selection circuit according to any preceding claim.

**WARNING** end of DESC field may overlap start of CLMS **.

Claims

**WARNING** start of CLMS field may overlap end of DESC **. cyclic manner the correction mode of the timepiece display each time a single correction mode selection pulse is produced. More specifically, the circuit is characterized by a construction which makes it possible to change the number of correction modes selected by a cyclic shift by presetting, a control terminal of the correction mode selection circuit. The same correction mode selection circuit can be used in electronic timepieces having differing numbers of display functions while the correction operation is capable of being easily performed by means of a small number of external control switches for the purpose of display correction. Finally, in the illustrated second embodiment, a timepiece has been provided with a time display section and calendar display section separately installed. However, the connection mode selection circuit may also be applied to a timepiece which is constructed such that both display modes occupy the same display section, the desired mode being chosen by appropriately switching over the display. WHAT WE CLAIM IS:

1. An electronic timepiece having an external control member arranged to produce output pulses upon actuation of the external control member and a mode selection circuit, said mode selection circuit comprising means for generating a plurality of mode selection signals in a sequential and cyclic manner in response to the output pulses generated by said external control member; and a mode number control terminal connected to said mode selection signal generating means and adapted to be preset to one of first and second predetermined logic levels during assembly of the timepiece; said mode selection signal generating means being responsive to said first and second predetermined logic levels to inhibit generation of a preselected one of said plurality of mode selection signals so that the number of said mode selection signals generated in the cyclic manner by said mode selection signals generating means varies in dependence on which of said predetermined logic levels is preset.