GB1587792A - Digital flight guidance system - Google Patents
Digital flight guidance system Download PDFInfo
- Publication number
- GB1587792A GB1587792A GB17528/78A GB1752878A GB1587792A GB 1587792 A GB1587792 A GB 1587792A GB 17528/78 A GB17528/78 A GB 17528/78A GB 1752878 A GB1752878 A GB 1752878A GB 1587792 A GB1587792 A GB 1587792A
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- United Kingdom
- Prior art keywords
- output
- memory
- aircraft
- memory means
- flight
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- Expired
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- 230000009977 dual effect Effects 0.000 claims description 8
- 238000012544 monitoring process Methods 0.000 claims description 7
- 238000006073 displacement reaction Methods 0.000 claims description 3
- 230000006870 function Effects 0.000 claims description 3
- 238000006243 chemical reaction Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- RZVHIXYEVGDQDX-UHFFFAOYSA-N 9,10-anthraquinone Chemical compound C1=CC=C2C(=O)C3=CC=CC=C3C(=O)C2=C1 RZVHIXYEVGDQDX-UHFFFAOYSA-N 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05D—SYSTEMS FOR CONTROLLING OR REGULATING NON-ELECTRIC VARIABLES
- G05D1/00—Control of position, course, altitude or attitude of land, water, air or space vehicles, e.g. using automatic pilots
- G05D1/0055—Control of position, course, altitude or attitude of land, water, air or space vehicles, e.g. using automatic pilots with safety arrangements
- G05D1/0077—Control of position, course, altitude or attitude of land, water, air or space vehicles, e.g. using automatic pilots with safety arrangements using redundant signals or controls
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- Engineering & Computer Science (AREA)
- Aviation & Aerospace Engineering (AREA)
- Radar, Positioning & Navigation (AREA)
- Remote Sensing (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Automation & Control Theory (AREA)
- Traffic Control Systems (AREA)
- Navigation (AREA)
- Safety Devices In Control Systems (AREA)
- Control By Computers (AREA)
- Control Of Position, Course, Altitude, Or Attitude Of Moving Bodies (AREA)
Description
(54) DIGITAL FLIGHT GUIDANCE SYSTEM
(71) We, THE BENDIX CORPORATION, a corporation of the State of Delaware, United
States of America, of Executive Center,
Southfield, Michigan 48076, United States of
America, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement:- This invention relates generally to flight guidance systems and particularly to digital flight systems. More particularly, this invention relates to digital flight guidance systems including a dual processor arrangement for providing monitored guidance of an aircraft when the craft is in cruise modes or performing critical flight maneuvers.
Flight guidance systems must be certified in accordance with Referal Aviation Agency (FAA) or military flight safety requirements.
Prior art digital flight control systems have utilized single processor architecture which requires knowledge that certain system failures can exist and/or how the failures can be identified. In most instances, due to the nature of the digital processor involved, the required failure identification is not practical. The present invention overcomes this disadvantage by providing a configuration featuring a dual processor arrangement whereby the necessity for identifying the failure is obviated.
An object of this invention is to provide in an aircraft a digital flight guidance system which provides monitored guidance of the aircraft during cruise and when performing critical flight maneuvers.
Another object of this invention is to provide in an aircraft a digital flight guidance system of the type described including a pair of processors, each having its own memory means and utilizing common input and output means.
Another object of this invention is to provide in an aircraft a digital flight guidance system including a dual processor arrangement wherein each processor performs some of the functions of the other processor, but in a different manner, to provide the degree of redundancy required for a certifiable system.
According to one aspect of the invention there is provided an aircraft including a digital system which guides the flight of the aircraft, said system comprising: a pair of processors; a pair of memory means, each of which is associated with a corresponding processor; system input means and system output means commonly associated with the processors and their corresponding memory means; means adapted to sense flight guidance conditions and means adapted to sense stability conditions; and wherein the system input means is connected to the flight guidance condition sensing means and is responsive to the sensed conditions therefrom for providing a flight guidance condition output, and is connected to the stability condition sensing means and is responsive to the sensed conditions therefrom for providing a stability condition output; one of the processors and its associated memory means is connected to the input means, said associated memory means including means responsive to the flight guidance condition output and means responsive to the stability condition output for providing a first system output for guidance and stability of the flight of the aircraft; and the other of the processors and its associated memory means is connected to the input means. said associated memory means including means responsive to the stability condition output for providing a second system output for stability of the flight of the aircraft.
The invention will now be described by way of example with reference to the accompanying drawings, in which: Figure I is a block diagram showing generally a digital flight guidance system in accordance with the invention.
Figure 2 is a block diagram showing an embodiment of the invention wherein the digital flight guidance system of the invention guides an aircraft when the craft is in a cruise mode.
With reference first to Figure 1, a dual processor digital flight guidance system in accordance with the invention is shown as including input means 2 and output means 4.
For purposes of describing the invention, input means 2 is considered to be an analog to digital converter, while output means 4 is considered to be a digital to analog converter.
The arrangement shown in Figure I includes a processor 6 and its associated memory means 8, and a processor 10 and its associated memory means 12. The processors and their associated memory means communicate with input means 2 and output means 4 through a common address and data bus 14 and a common direct memory access (DMA) control bus 16. Direct memory access to processor 6 and its associated memory means 8 is controlled by a DMA controller 18 while direct memory access to processor 10 and its associated memory 12 is controlled by a
DMA controller 20.
It will be understood that DMA control as illustrated in Figure 1, reduces the real time utilization of both of the processors 6 and 10 to permit significantly less complex input means 2 and output means 4, as might otherwise be the case. The input and output means are arranged in essentially a single channel configuration, with continuous self testing by both processors. The self testing of the input and output means involves "wrap around" testing in which digital data generated by one of the processors is transmitted to output lines after a digital to analog conversion accomplished by output means 4.
These outputs are then fed back through input means 2, which performs an analog to digital conversion, to the one processor where the results are compared with the originally transmitted data. Most of the hardware involved in the input/output arrangement is continuously checked in this manner. Significantly, all of the hardware that is capable of generating multiple axis failures is thus monitored by both processors.
Similarly, the voltages generated by a single power supply (not shown) which powers all of the components of the system are monitored by both processors to ensure proper system operation.
It will therefore be seen from Figure 1, and as will be further described with reference to
Figure 2 that the digital flight guidance system of the invention utilizes a dual processor arrangement, with each of the processors having its own memory means and both of the processors using common input and output means.
Reference is now made to Figure 2, wherein the digital flight guidance system shown generally in Figure 1 is shown in an embodiment for guiding an aircraft when the craft is in a cruise mode.
Cruise sensing means designated generally by the numeral 22, and which may include an aircraft altitude sensor, a heading sensor, an attitude sensor and-such other flight condition sensors as may be necessary for guiding the craft about, for example, the roll axis, provides analog outputs corresponding to the sensed conditions at an output line 23.
Stability sensing means 21, which may include a roll rate gyro or a sensor coupled to the pilot-operated control stick of the craft, provides analog outputs corresponding to the sensed condition at an output line 25. The analog outputs at output lines 23 and 25 are converted to digital outputs by input means 2 and are applied therefrom through output lines 27 and 29, respectively, to memory means 8 and 12 driven by processors 6 and 10, through DMA controller 18, as shown in
Figure 1.
In this connection, it is noted that processor 6 (Figure 1) and memory means 8 perform all guidance cruise computations as well as stability computations and cross processor monitoring, that is processor monitoring by cross comparison. Processor 10 (Figure I) and memory means 12 perform only stability and cross processor monitoring computations. As will be hereinafter described, dual servo commands are generated which are jointly compared. Any significant discrepancy in the commands causes a system disconnect. Therefore, during cruise modes, rate and command limiting is achieved to limit maneuvers uncontrollable by the pilot due to internal failures of either of the processors and their associated active memory means. Thus, it is not important to know that such failures can exist or how they may be generated.This eliminates the need, as with single processor systems, to identify the failures and to provide self testing means to detect them, and hence provides a distinct advantage over such systems.
With continued reference to Figure 2, the output from input means 2 at output line 27 is applied to a cruise memory device 24 in memory means 8, which performs the appropriate cruise computations in accordance with the conditions sensed by cruise sensing means 22. Cruise memory device 24 drives a command limiting memory device 26 in memory means 8 and a command limiting memory device 28 in memory means 12.
Memory means 26 and 28 perform appropriate computations to provide required rate and displacement cruise command limiting.
Memory device 26 drives a stability memory device 30 in memory means 8 and memory device 28 drives a stability memory device 32 in memory means 12. The output from input means 2 at output line 29 is applied to memory devices 30 and 32.
Memory devices 30 and 32 perform the required computations for providing high bandwidth stability control and for providing system outputs. The system output from memory device 30 is applied through DMA
Controller 20 (Figure 1) to output means 4A which performs a digital to analog conver sion for providing a servo command output to drive a servo actuator 34 to control appropriate control surfaces of the aircraft as will be u, understood by those skilled in the art.
The system output from memory device 30 is applied to a comparator memory device 36 in memory means 8 and to a comparator memory device 38 in memory means 12, while the system output from memory device 32 in memory means 12 is applied to memory device 36 and to memory device 38. The outputs from memory devices 30 and 32 are compared by memory devices 36 and 38. The compared outputs from memory devices 36 and 38 are outputed through output means 4B and 4C, repectively, to provide analog monitoring outputs which are applied to suitable disconnect logic so that any difference in the computations performed by memory means 8 and 12 driven by processors 6 and 10, respectively, as heretofore described, will cause a system disconnect.
Although control of the craft about the roll axis has been described it is to be noted that similar configurations are adaptable for controlling the craft about the other flight axes in accordance with the conditions sensed by sensing means 21 and 22 as will now be understood by those skilled in the art.
The embodiment of Figure 2 may be modified with the memory means 8 and 12 including appropriate memory devices to perform the required computations for guiding the aircraft during a critical flight maneuver, for example for guiding the aircraft when landing.
It will now be seen from the aforenoted description of the invention that the heretofore stated objects have been met. A digital flight guidance system including dual processor/memory architecture has been described for guiding an aircraft during cruise modes and when performing critical flight maneuvers such as landing and the like. Each processor performs some of the same functions of the other processor, but in a different manner to provide the degree of redundancy required for a certifiable system. During the landing maneuver, any single or multiple axis failure is detected, including any internal failure of either of the processors and their associated active memory devices. During cruise modes, appropriate rate and displacement command limiting is achieved for the heretofore noted purposes.Thus, with the arrangement illustrated and described it is not important to know that failures can exist or how they may be generated. Identification of the failures themselves is thus unnecessary.
WHAT WE CLAIM IS:
1. An aircraft including a digital system which guides the flight of the aircraft, said system comprising: a pair of processors; a
pair of memory means, each of which is
associated with a corresponding processor;
system input means and system output
means commonly associated with the proces
sors and their corresponding memory means;
means adapted to sense flight guidance
conditions and means adapted to sense sta
bility conditions; and wherein the system
input means is connected to the flight guid
ance condition sensing means and is respon
sive to the sensed conditions therefrom for
providing a flight guidance condition output,
and is connected to the stability condition
sensing means and is responsive to the sensed
conditions therefrom for providing a stability
condition output; one of the processors and
its associated memory means is connected to
the input means, said associated memory
means including means responsive to the
flight guidance condition output and means
responsive to the stability condition output
for providing a first system output for guid
ance and stability of the flight of the aircraft;
and the other of the processors and its
associated memory means is connected to the
input means, said associated memory means
including means responsive to the stability
condition output for providing a second
system output for stability of the flight of the
aircraft.
2. An aircraft including a digital system
as claimed in claim 1, wherein: each of the
memory means includes means adapted to
compare the system output therefrom to the
system output from the other of the memory
means and to provide a compared system
output; and the system output means is
connected to one of the memory means and
responsive to the system output therefrom to
provide a command output, and connected
to the comparing means included in each of
the memory means and responsive to the
compared system output therefrom to pro
vide a corresponding monitoring output.
3. An aircraft including a digital system
as claimed in claim 1, wherein: the memory
means associated with the one processor
includes comparator means adapted to com
pare the first system output provided by said
memory means to the second system output
provided by the memory means associated
with the other of the processors and to
provide a first compared output; and the
memory means associated with the other of
the processors includes means adapted to
compare the second system output provided
by said memory means to the first system
output provided by the memory means
associated with the one processor and to
provide a second compared output.
4. An aircraft including a digital system
as claimed in claim 1, wherein: the system
output means includes means connected to vthe memory means associated with the one
processor and responsive to the first system
**WARNING** end of DESC field may overlap start of CLMS **.
Claims (6)
1. An aircraft including a digital system which guides the flight of the aircraft, said system comprising: a pair of processors; a
pair of memory means, each of which is
associated with a corresponding processor;
system input means and system output
means commonly associated with the proces
sors and their corresponding memory means;
means adapted to sense flight guidance
conditions and means adapted to sense sta
bility conditions; and wherein the system
input means is connected to the flight guid
ance condition sensing means and is respon
sive to the sensed conditions therefrom for
providing a flight guidance condition output,
and is connected to the stability condition
sensing means and is responsive to the sensed
conditions therefrom for providing a stability
condition output; one of the processors and
its associated memory means is connected to
the input means, said associated memory
means including means responsive to the
flight guidance condition output and means
responsive to the stability condition output
for providing a first system output for guid
ance and stability of the flight of the aircraft;
and the other of the processors and its
associated memory means is connected to the
input means, said associated memory means
including means responsive to the stability
condition output for providing a second
system output for stability of the flight of the
aircraft.
2. An aircraft including a digital system
as claimed in claim 1, wherein: each of the
memory means includes means adapted to
compare the system output therefrom to the
system output from the other of the memory
means and to provide a compared system
output; and the system output means is
connected to one of the memory means and
responsive to the system output therefrom to
provide a command output, and connected
to the comparing means included in each of
the memory means and responsive to the
compared system output therefrom to pro
vide a corresponding monitoring output.
3. An aircraft including a digital system
as claimed in claim 1, wherein: the memory
means associated with the one processor
includes comparator means adapted to com
pare the first system output provided by said
memory means to the second system output
provided by the memory means associated
with the other of the processors and to
provide a first compared output; and the
memory means associated with the other of
the processors includes means adapted to
compare the second system output provided
by said memory means to the first system
output provided by the memory means
associated with the one processor and to
provide a second compared output.
4. An aircraft including a digital system
as claimed in claim 1, wherein: the system
output means includes means connected to vthe memory means associated with the one
processor and responsive to the first system
output therefrom to provide a command output; and wherein there is provided aircraft control surface actuating means connected to the means included in the system output means connected to the memory means associated with the one processor and responsive to the command output therefrom to actuate an aircraft control surface for the guidance and stability of the flight of the aircraft.
5. An aircraft including a digital system as claimed in claim 3, wherein the system output means includes first means connected to the comparator means in the memory means associated with the one processor and responsive to the first compared output therefrom for providing a first logic output, and second means connected to the comparator means in the memory means associated with the other of the processors and responsive to the second compared output therefrom for providing a second logic output.
6. An aircraft including a digital system which guides the flight of the aircraft constructed and adapted to operate substantially as herein described with reference to and as illustrated in the accompanying drawings.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US80268577A | 1977-06-02 | 1977-06-02 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| GB1587792A true GB1587792A (en) | 1981-04-08 |
Family
ID=25184427
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB17528/78A Expired GB1587792A (en) | 1977-06-02 | 1978-05-03 | Digital flight guidance system |
Country Status (4)
| Country | Link |
|---|---|
| JP (1) | JPS543799A (en) |
| DE (1) | DE2824279A1 (en) |
| FR (1) | FR2393360A1 (en) |
| GB (1) | GB1587792A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5671103A (en) * | 1979-11-15 | 1981-06-13 | Toshiba Corp | Control device of power plant |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB1364625A (en) * | 1970-07-09 | 1974-08-21 | Secr Defence | Digital data processing system |
| US3688099A (en) * | 1971-04-28 | 1972-08-29 | Lear Siegler Inc | Automatic control system with a digital computer |
| CA1026850A (en) * | 1973-09-24 | 1978-02-21 | Smiths Industries Limited | Dual, simultaneously operating control system with fault detection |
-
1978
- 1978-05-03 GB GB17528/78A patent/GB1587792A/en not_active Expired
- 1978-05-09 FR FR7813630A patent/FR2393360A1/en active Granted
- 1978-05-31 JP JP6564678A patent/JPS543799A/en active Granted
- 1978-06-02 DE DE19782824279 patent/DE2824279A1/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| FR2393360B1 (en) | 1982-12-17 |
| DE2824279A1 (en) | 1978-12-14 |
| FR2393360A1 (en) | 1978-12-29 |
| JPS543799A (en) | 1979-01-12 |
| JPS6365961B2 (en) | 1988-12-19 |
| DE2824279C2 (en) | 1989-04-20 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PS | Patent sealed [section 19, patents act 1949] | ||
| PCNP | Patent ceased through non-payment of renewal fee |