GB1585892A

GB1585892A - Tdm switching networks

Info

Publication number: GB1585892A
Application number: GB2450/77A
Authority: GB
Original assignee: Siemens AG
Current assignee: Siemens AG
Priority date: 1976-01-23
Filing date: 1977-01-21
Publication date: 1981-03-11
Also published as: DE2602570B2; AT352791B; IT1076527B; FR2339309A1; CH613576A5; ATA984276A; DE2602570A1; DE2602570C3; FR2339309B1; BE850639A; SE7700672L

Abstract

A switching matrix design is to be found which can be applied uniformly for all switching matrix sizes and allows a switching matrix to be expanded in small steps. Having regard to the fact that the switching matrix units effecting the switching-through should be integrable, in addition, only a small number of line connections should be required for these. This is achieved by the fact that the time-division multiplex lines (1Zan to nZab and 1San to nSab) are arranged in the manner of a matrix and can be connected at their points of intersection by switching matrix units (KE) which exhibit a smaller traffic handling capacity than can be fully achieved. The larger the switching matrix, the smaller the traffic handling capacity of these switching matrix units. The switching matrix units (KE) are suitably constructed in the form of shift register rings. <IMAGE>

Description

(54) IMPROVEMENTS IN OR RELATING TO T.D.M. SWITCHING NETWORKS (71) We, SIEMENS AKTIENGESELLSCHAFT, a German Company, of Berlin and Munich, Federal Republic of Germany, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement: This invention relates to t.d.m. switching networks.

In our copending Patent Application No.

2448/77 (Serial No. 1585891) there is disclosed and claimed ea t.d.m. switching network in which groups of t.d.m. lines intersect to form a matrix arrangement and switching network units are provided at respective intersections between the groups and are able to interconnect any of the t.d.m. lines at the associated intersection.

T.d.m. switching network in which switching between time channels of the connected t.d.m. lines is effected simply by time slot conversion by means of appropriate time stages are known, for example from German Specifications Nos. 2025 102 and 2064202.

These known t.d.m. switching networks possess the structure of conventional spatial switching networks based on a three-stage concept. In the case of larger numbers of terminals for t.d.m. lines, switching networks are used which possess a larger number of for example five stages. However, this constitutes a considerable extension, changing the number of connections which are simultaneously possible for example 16,000 to 500,000.

If a smaller extension is to be effected it is known (see German Specification No.

2064 202) to retain the three-stage concept and to duplicate the switching network.

However, to this end it is necessary that the time stages located in the central switching network stage be designed for connection with more intermediate lines than are required for the non-extended switching network, in which case, in the interest of simple extendability, the increased number of intermediate line terminals is provided as an initial feature.

In view of the fact that switching network units used in the switching networks can be designed in the integrated technique it is of interest to be able to use switching network units of only one form and for these switching network units to have only a small number of line terminals. Furthermore, it is of general interest to have a common form of switching network for all sizes of switching network and for this to be able to be extended in small steps.

According to this invention there is provided a t.d.m. switching network comprising a plurality of bidirectional t.d.m. lines which intersect with one another to form a matrix and at each two line intersection a respective switching network unit connected to the t.d.m. lines defining the intersection, via which switching network unit connections can be established each between any pair of time channels on the t.d.m. lines, each switching network unit having a smaller traffic handling capacity than that of each of the t.d.m. lines.

The traffic handling capacity of each switching network unit is expediently dependent upon the size of the switching network in that the greater the number of switching network units in the switching network the smaller is the traffic handling capacity of each switching network unit.

Advantageously the number of connections which can be handled via each switching network unit and the number of time channels on each of the t.d.m. lines do not have a common integral factor greater than one.

Preferably the switching network units are all identical to one another.

Thus such a switching network can be of any size, large or small, and each switching network unit has only two t.d.m. line terminals. Furthermore, it is possible to extend the switch network in small steps by connecting further individual t.d.m. lines using further switching network units. Such switching networks can possess only a small number of switching network stages - even with a large number of t.d.m. line terminals.

The t.d.m. lines may form column lines and row lines of a rectangular - matrix, or each t.d.m. line may intersect each other t.d.m. line to form a triangular matrix. The invention also extends to a t.d.m. switching network comprising a plurality of similar such rectangular matrix switching networks and a plurality of similar such triangular matrix switching networks, the column or the row lines of each rectangular matrix each being connected to a respective t.d.m.

line of a respective one of the triangular matrices via a respective intermediate line.

For use in a PCM exchange each switching network unit preferably comprises as many information shift registers as simultaneous connections can be handled via the switching network unit, each information shift register having as many stages as there are bits in each PCM word, as many switching units as there are information shift registers, each switching unit having a first switching path via which the output of the last stage of an associated information shift register is connected to the input of the first stage of a following information shift register to form an information shift register ring, second switching paths via which said output and said input are connected respectively to the outgoing wire and the incoming wire of one of the t.d.m. lines to which the switching network unit is connected, and third switching paths via which said output and said input are connected respectively to the outgoing wire and the incoming wire of the other t.d.m. line to which the switching network unit is connected, and means for closing one of the switching paths in each switching unit in each time slot of each t.d.m. pulse frame in dependence upon connections to be established between time channels on the two t.d.m. lines.

Preferably the means for closing the switching paths comprises a first and a second address shift register ring each comprising the same number of address shift registers and the same number of stages in each shift register as in the information shift register ring, one shift register in each address shift register ring being assigned to a respective one of the switching units, and as many comparators as there are information shift registers, each comparator being assigned to a respective one of the switching units for the control of the switching paths thereof in dependence upon the results of comparisons effected in each time slot between a code word corresponding to an address of the time channel of the following time slot and an address, of a time channel on said one t.d.m. line of a connection to be established via the switching network unit, being transferred into that shift register of the first address shift register ring which is assigned to the same switching unit as the comparator, and between said code word and an address, of that time channel on said other t.d.m. line in respect of which said connection is to be established being transferred into that shift register of the second address shift register ring which is assigned to the same switching unit as the comparator.

The invention will be further understood from the following description by way of example of embodiments thereof with reference to the accompanying drawings, in which: Figs. 1 to 3 schematically illustrate alternative forms of PCM t.d.m. switching networks in accordance with embodiments of the invention; and Fig. 4 schematically illustrates a switching network unit which can be used in the switching networks of Figs. 1 to 3.

Fig. 1 illustrates a t.d.m. switching network for PCM t.d.m. lines each of which consists of two wires for the two directions of transmission. The t.d.m. lines form intersecting row lines 1Z to nZ and column lines 1S to mS (in Fig. 11 m=3) of a rectangular matrix, at each intersection of which is provided a switching unit KE which is connected to the wires of the row and column lines defining the intersection. The switching network units KE are identical and each is able merely by means of time slot conversion to produce a selective, mutual assignment of time channels on the connected t.d.m. lines.

The traffic handling capacity of each switching network unit is less than that, referred to as full availability, of each t.d.m.

line to which it is connected. For example if each t.d.m. line has 32 time channels then it is possible to handle simultaneously less than 32 connections via each switching network unit KE. In this respect the traffic handling capacity of each switching network unit is matched to the size of the switching network in that the larger the switching network the smaller is the traffic handling capacity of each switching network unit, and vice versa. As a result large switching networks, in which the traffic between intersecting t.d.m. lines is less than in small switching networks, do not become uneconomical.

In comparison to known switching networks in which a separate switching network unit is provided for each t.d.m. line, a switching network in accordance with the invention has the advantage that the breakdown of a switching network unit does not inevitably lead to loss of the entire traffic on a specific t.d.m. line.

It is possible to extend the switching network in a simple manner by providing further t.d.m. lines as further columns and/or rows of the matrix and connecting these to the existing lines in the same manner via further switching network unit KE.

If, as assumed, the t.d.m. lines are fourwire lines, with the arrangement illustrated in Fig. 1 it is not readily possible to establish connections between t.d.m. lines of the same type, such as between lines in different groups of row lines. Therefore, as is further explained below, this arrangement is particularly suitable to form part of a large switching network in which case lines of one type comprise t.d.m. lines which do not lead to other exchanges but instead establish connections to further matrix arrangements within the switching network. If instead the t.d.m. lines are two wire lines the above limitation does not exist, it being possible to establish a connection for example between two row t.d.m. lines via a first switching network unit, a column t.d.m. line, and a further switching network unit.

Fig. 2 illustrates an alternative switching network in the form of a triangular matrix having m(m--1)/2 intersections between m t.d.m. lines ZM, at which intersections respective identical switching network units KE are provided. Thus as illustrated in Fig.

2 a switching network unit is connected between every p!air of t.d.m. lines, so that it is possible to establish connections between any two t.d.m. lines via only one switching network unit. This switching network can also be readily extended by the provision of further switching network units for additional td.m. lines.

Fig. 3 illustrate s a switching network having two stages A and B, in which the A-stage consists of rectangular matrix arrangements as illustrated in Fig. 1 and the B-stage consists of triangular matrix arrangements as illustrated in Fig. 2. With z rectangular matrix arrangements M1 to Mz in the A-stage each having connected thereto, and forming for example the row lines, m t.d.m. lines and each having n output-end lines which form in this example the column lines, n triangular matrix arrangements D1 to Dn each for m t.d.m. lines are required.

Intermediate lines ZL connect each outputend line of the matrix arrangements of the A-stage to a respective t.d.m. line input of the triangular matrix arrangements of the B-stage. Connections which are established between t.d.m. row lines of the matrix arrangements of the A-stage will with this arrangement run via three switching network units KE, namely via two switching network units in the A-stage and via one switching network unit in the B-stage.

Fig. 4 illustrates a switching network unit which is particularly suitable for use as a switching network unit KE referred to above.

The switching network unit comprises a plurality of information shift registers W1 to Wk the number of which is equal to the number of connections which can be handled simultaneously via the switching network unit and hence determines the traffic handling capacity of the switching network unit. Each shift register consists of the same numebr of e.g. 8 stages as there are bits in each PCM word, and has the outputs of its least stage coupled to the input of the first stage of a following shift register via a respective one of switching units S1 to Sk thereby forming a shift register ring via a switching path SD in each switching unit.

In Fig. 4 for clarity only the switching unit S1 located between the shift registers W1 and W2 has been shown in detail, the switching paths of this unit being shown for simplicity merely as mechanical contacts. Via each switching unit the output of the last stage of the preceding shift register and the input of the first stage of the following shift register can alternatively be connected either respectively to the outgoing and incoming wires of a t.d.m. line B1 via switching paths SP1 or respectively to the outgoing and incoming wires of a t.d.m. line B2 via switching paths SP2, as shown for the switching unit S1.The t.d.m. lines B1 and B2 correspond to the two t.d.m. lines which in a switching network define the intersection at which the switching network unit is provided.

For controlling the switching units S1 to Sk the switching network unit comprises two address shift register rings each having the same number of shift registers lAl to lAk and 2A1 to 2Ak and the same number of stages in each shift register as the information shift register ring, which shift register rings serve to store switching addresses, and the same number of comparators V1 to Vk as there are information shift registers. Thus each information shift register a.g. W1 and the following switching unit e.g. Sl is assigned an address shift register e.g. lAl and 2A1 in each address shift register ring and a comparator e.g. V1.Each comparator has two inputs connected to the inputs of the associated address shift registers, a further input connected to a line T, and three outputs each of which serves for the control of a respective one of the switching paths SD, SP1, and SP2 of the switching unit to which the comparator is assigned, as illustrated schematically in Fig. 4. On the line T are produced in a cyclic sequence code words each of which characterises a respective time slot; the time slots characterised by these code words are in each case one time slot in advance of the current time slot of the PCM system. This means for example that during each time slot of the time channel 5 the code word which characterises time slots of the time channel 6 is present on the line T.

Each of the comparators V1 to Vk oper ates to control the switching paths of the switching unit to which it is assigned in such manner that in the event of the identity of a time channel address emitted from one address shift register ring with the current code word on the line T the switching paths e.g. SP1 are closed, in the event of the identity of a time channel address emitted from the other address shift register ring with this code word the switching paths e.g.

SP2 are closed, and in the event of no such identity the switching path SD is closed.

In the case of 32 time channels on each t.d.m. line, a code comprising only 5 bits is sufficient to represent each time channel address. Since, as mentioned above, each address shift register has in this example 8 stages 3 further bits not required for the address representation are input into each address shift register. One of these bits is used prior to the beginning of a bit comparison by the actual comparison component of the relevant comparator V, to set an integration element connected following this comparator component. Another of these bits serves to bring about a transfer of the contents of the integration element into a following holding element after the comparison has been completed, and the remaining one of these bits is used to reset the integration element. A comparator construction of this type is disclosed for example in U.K. Patent Specification No.

1,491,813.

In the following the mode of operation of the switching network unit illustrated in Fig.

4 will be explained by way of example for a connection between the time channel 10 on the t.d.m. line B1 and the time channel 20 on the t.d.m. line B2, it being assumed that the switching network unit can handle 15 simultaneous connections and accordingly that k= 15, i.e. for example there are 15 information shift registers W1 to W15.

For this connection it is initially assumed that the address of the time channel 10 and the address of the time channel 20 are entered into corresponding shift registers of the address shift register rings lAl to lA15 in respect of the t.d.m. line B1 and 2A1 to 2A15 in respect of the t.d.m. line B2. For example it is assumed that during a time slot of the time channel 9 these addresses are delivered respectively from the shift register lAl simultaneously to the shift register 1A2 and the comparator V2 and from the shift register 2A1 simultaneously to the shift register 2A2 and the comparator V2.Also during this time slot of the time channel 9 the code word of the time channel 10 occurs on the line T to that the comparator V2 establishes an identity and consequently at the end of the time slot of the time channel 9, causes an actuation signal for the switching paths SPl of the switching unit S2 to be transferred into its holding component. Thus at the beginning of the following time slot of the 10th time channel these switching paths SP1 of the switching unit S2 are closed, so that a PCM word on the inncoming wire of the t.d.m. line B1 in the time channel 10 is entered serially into the information shift register W3, and any PCM word contained in the information shift register W2 is read out serially to the outgoing wire of the t.d.m. line B1 again in the time channel 10.

Also during the time channel 10 the addresses of the time channels 10 and 20 are transferred into the shift registers 1A3 and 2A3 respectively and the code word of the time channel 11 occurs on the line T. Accordingly the comparator V3 establishes no identity, as a result of which in a similar manner to that described above the switching path SD of the switching unit S3 is closed throughout the following time slot of the time channel 11, so that the PCM word derived from the time channel 10 of the t.d.m. line B1 is forwarded from the shift register W3 to the following shift register W4.Similar processes occur in subsequent time slots until during the next time slot of the 19th time channel the comparator V12 establishes identity between the code word of the time channel 20 occurring on the line T and the address of the time channel 20 being transferred from the shift register 2All to the shift register 2A12, as a consequence of which during the following time slot of the time channel 20 the switching paths SP2 of the switching unit S13 are closed. Thus during this time slot of the time channel 20 the PCM word derived from the time channel 10 of the t.d.m.

line B1 is transferred from the information shift register W12 to the outgoing wire of the t.d.m. line B2, and a PCM word in the time channel 20 on the incoming wire of the t.d.m. line B2 is entered serially into the information shift register W13. The latter PCM word is advanced in the same manner as described above in successive time slots through the successive information shift registers, as are the addresses advanced through the address shift registers, until in the time slot of the time channel 10 of the next t.d.m.

pulse frame there is again a read out of the PCM word from an information shift register onto the outgoing wire of the t.d.m. line B1 and an entry of another PCM word from the incoming wire of the t.d.m. line B1 into an information shift register, this read out and entry being ast described above but involving different shift registers. These processes are repeated in a similar manner for successive t.d.m. pulse frames.

As in respect of each such connection, in each time slot only one information, shift register and the assigned comparator and address shift registers are used, in the same manner as described above it is possible to handle a further 14 connections simultane- ously via the switching network unit.

If as described above the number (32) of time channels on each t.d.m. line and the number (15) of information shift registers in the switching network unit do not have a common integral factor of more than one, then all the switching paths in. the switching network unit will be used for a single connection in successive t.d.m. pulse frames.

Accordingly the whole switching network unit can be tested by checking a single connection.

WHAT WE CLAIM IS:- 1. A t.d.m. switching network comprising a plurality of bidirectional t.d.m. lines which intersect with one another to form a matrix and at two-line Thtersection a respective switching network unit connected to the t.d.m. lines defining the intersection, via which switching network unit connections can be established each between any pair of time channels on the t.d.m. lines, each switching network unit having a smaller traffic handling capacity than that of each of the t.d.m. lines.

2. A switching network as claimed in Claim 1 wherein the traffic handling capacity of each switching network unit is dependent upon the size of the switching network in that the greater the number of switching network units in the switching network the smaller is the traffic handling capacity of each switching network unit.

3. A switching network as claimed in Claim 1 or Claim 2 wherein the number of connections which can be handled via each switching network unit and the number of time channels on each of the t.d.m. lines do not have a common integral factor greater than one.

4. A switching network as claimed in any of Claims 1 to 3 wherein the switching network units are all identical to one another.

5. A switching network as claimed in any one of Claims 1 to 4 wherein the t.d.m.

lines form column lines and row lines of a rectangular matrix.

6. A switching network as claimed in any one of Claims 1 to 4 wherein each t.d.m.

line intersects each other t.d.m. line to form a triangular matrix.

7. A t.d.m. switching network comprising a plurality of similar rectangular matrix switching networks each as claimed in Claim 5 and a plurality of similar triangular matrix switching networks each as claimed in Claim 6, wherein the column or the row lines of each rectangular matrix are each connected to a respective t.d.m. line of a respective one of the triangular matrices via a respective intermediate line.

8. A t.d.m. switching network substan tially as herein described with reference to Fig. 1 or Fig. 2 or Figs. 1 to 3 of the accom panying drawings.

9, A switching network, for a PCM exchange system, as claimed in any one of the preceding claims, wherein each switch ing network unit comprises as many information shift registers as simultaneous connections can be handled via the switching network unit, each information shift register having as many stages as there are bits in each PCM word, as many switching units as there are information shift regi sters; each switching unit having a first switching path via which the output of the last stage of an associated information shift register is connected to the input of the first stage of a following information shift regi ster to form an information shift register ring, second switching paths via which said output and said input are connected re spectively to the outgoing wire and the in coming wire of one of the t.d.m. lines to which the switching network unit is connected, and third switching paths via which said output and said input are connected respectively to the outgoing wire and tbe incoming wire of the other t.d.m. line to which the switching network unit, and means for closing one of the switching paths in each switching unit in each time slot of each t.d.m. pulse frame in dependence upon connections to be established between time channels on the two t.d.m. lines.

10. A switching network as claimed in Claim 9 wherein the means for closing the switching paths comprises a first and a second address shift register ring each comprising the same number of address shift registers and the same number of stages in each shift register as in the information shift register ring, one shift register in each ad dress shift register ring being assigned to a respective one of the switching units, and as many comparators as there are information shift registers, each comparator being as signed to la respective one of the switching units for the control of the switching paths thereof in dependence upon the results of comparisons effected in each time slot be tween a code word corresponding to an address of the time channel of the following time slot and an address, of a time channel on said one t.d.m. line of a connection to be established via the switching network unit, being transferred into that shift regi ster of the first address shift register ring which is assigned to the same switching unit as the comparator, and between said code word and an address, of that time channel on said other t.d.m. line in respect of which said connection is to be established being transferred into that shift register of the second address shift register ring which is

**WARNING** end of DESC field may overlap start of CLMS **.

Claims

**WARNING** start of CLMS field may overlap end of DESC **. address shift registers are used, in the same manner as described above it is possible to handle a further 14 connections simultane- ously via the switching network unit. If as described above the number (32) of time channels on each t.d.m. line and the number (15) of information shift registers in the switching network unit do not have a common integral factor of more than one, then all the switching paths in. the switching network unit will be used for a single connection in successive t.d.m. pulse frames. Accordingly the whole switching network unit can be tested by checking a single connection. WHAT WE CLAIM IS:-

1. A t.d.m. switching network comprising a plurality of bidirectional t.d.m. lines which intersect with one another to form a matrix and at two-line Thtersection a respective switching network unit connected to the t.d.m. lines defining the intersection, via which switching network unit connections can be established each between any pair of time channels on the t.d.m. lines, each switching network unit having a smaller traffic handling capacity than that of each of the t.d.m. lines.

lines form column lines and row lines of a rectangular matrix.

line intersects each other t.d.m. line to form a triangular matrix.

assigned to the same switching unit as the comparator.

11. A switching network as claimed in any one of Claims 1 to 8 wherein each switching network unit is substantially as herein described with reference to Fig. 4 of the accompanying drawings.

12. A PCM telecommunications exchange including a switching network according to any one of the preceding claims.

13. A PCM telecommunications system including an exchange according to Claim 12.

14. A system according to Claim 13 including a plurality of switching networks according to any one of Claims 1 to 11, the traffic handling capacity of each switching network unit being dependent on the size of the switching network in that the greater the number of switching network units in the switching network the smaller is the traffic handling capacity of each switching network unit.