GB1584557A

GB1584557A - Phase control circuit arrangement

Info

Publication number: GB1584557A
Application number: GB2343077A
Authority: GB
Original assignee: Pye Electronic Products Ltd
Current assignee: Pye Electronic Products Ltd
Priority date: 1977-06-02
Filing date: 1977-06-02
Publication date: 1981-02-11

Description

(54) PHASE CONTROL CIRCUIT ARRANGEMENT (71) We, PYE (ELECTRONIC PRO DUCTS) LIMITED, of St. Andrews Road, Cambridge CB4 1DP, a British Company, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement: The invention relates to a circuit arrangement for controlling the phase of an alternating signal.

A circuit arrangement comprising first and second balanced modulators, means for feeding the alternating signal to the first and second modulators such that the signal applied to the first modulator is 90" out of phase with that applied to the second modulator, means for generating first and second alternating control signals the first control signal being 90" out of phase with the second control signal, means for applying the first control signal to the first modulator, means for applying the second control signal to the second modulator, and means for summing the outputs of the first and second modulators, the output of the summing - means being the output of the circuit arrangement, which can be used, for example, as a phase modulator is described in an article by R. Thompson and D.R.

Clouting entitled Digital Angle Modulation in the December 1976 issue of Wireless World on pages 71 to 76. Figures 4 and 5 of this article show a modulator for producing a frequency shift keyed signal i.e. the carrier is switched in phase in discrete steps. The first and second control waveforms generated are in the form of a sine and cosine waveform. These waveforms are generated by means of a ring counter together with a weighting network for each function. In order to ensure that the output signal has a reasonably constant amplitude it is necessary to produce relatively pure sine and cosine waves for the control waveforms i.e.

the quantum steps produced by the weighting networks in response to the output of the ring counter must be small. Consequently the number of stages in the ring counter must be relatively large. Further the input alternating signals must be exactly 90" out of phase with respect to each other at the respective modulator inputs and in addition the transfer characteristics of the two modulators and the gains of the two paths for the alternating signal need to be ideal and accurately matched.

A similar circuit arrangement to that disclosed by Thompson and Clouting has been used for the adjustment of the phase of the colour subcarrier signal in colour television systems. When combining signals from several different sources it is necessary to synchronise the phase of the colour subcarrier signal with the horizontal synchronisation pulses. This requires an arrangement which is capable of varying the phase of the subcarrier signal by +180". In this application the sine/cosine wave generation has been by means of a special potentiometer which has a sine/cosine law relationship.

However such potentiometers are difficult to incorporate in automatic phase control arrangements and the necessity for ideal characteristics and matching between the two modulators and both signal paths still remains. Further the alternating signal applied to the modulators must still have a 90" phase difference which imposes stringent requirements on the phase shifting circuits.

It is an object of the invention to provide a circuit arrangement which will produce an output phase controlled signal having a substantially constant amplitude despite non-ideal control waveforms or modulator characteristics.

The invention provides a circuit arrangement for controlling the phase of an alternating signal applied to its input comprising first and second balanced modulators, means for feeding the alternating signal to the first and second balanced modulators such that the signal applied to the first modulator is out of phase but not in anti-phase with that applied to the second modulator, means for generating first and second alternating control signals the first control signal being out of phase but not in anti-phase with respect to the second control signal, means for applying the first control signal to the first modulator, means for applying the second control signal to the second modulator, means for summing the outputs of the first and second modulators, means for comparing the amplitude of the summed outputs of the first and second modulators with a reference value and for generating a third control signal dependent upon the result of the comparison, means for controlling the amplitude of the first and second control signals in response to the third control signal such that the summed amplitude of the outputs of the first and second modulators tends towards a constant value, the summed outputs of the first and second modulators being the phase controlled alternating signal.

Conveniently the signal applied to the first input of the first modulator is substantially 90" out of phase with that applied to the first input of the second modulator and the first control signal is substantially 90" out of phase with the second control signal. The first and second control signals may have triangular waveforms.

Conveniently means for generating the first and second control signals may comprise an oscillator, first and second up/down counters arranged to be clocked by the oscillator and initially set so that when one is at the minimum count the other is at half the difference between the minimum and maximum count, first and second digital to analogue converters to which respective outputs of the first and second counters are connected, and means for applying the third control signal to the first and second digital to analogue converters as their reference voltage, the outputs of the digital to analogue converters being the first and second control signals. Means may be provided for inhibiting the clocking of the first and second counters at a selected time.

The invention further provides a circuit arrangement for controlling the phase of an alternating signal applied to its input comprising first and second balanced modula tors, means for feeding the alternating signal to the first and second balanced modulators such that the signal applied to the first modulator is out of phase but not in antiphase with that applied to the second modulator, means for generating first and second control signals each control signal being a cyclically variable direct voltage, the cyclic variation for the first control signal being similar to that for the second control signal but being out of phase though not in antiphase therewith, means for applying the first control signal to the first modulator, means for applying the second control signal to the second modulator, means for summing the outputs of the first and second modulators, means for comparing the amplitude of the summed outputs of the first and second modulators with a reference value and for generating a third control signal dependent upon the result of the comparison, means for controlling the amplitude of the first and second control signals in response to the third control signal such that the summed amplitude of the outputs of the first and second modulators tends towards a constant value, the summed outputs of the first and second modulators being the controlled alternating signal. The phase relationship between the cyclic variations for the first and second control signals may be 90" and this may be achieved by means of a sine/cosine potentiometer.

The reference value may be the amplitude of the alternating signal at the input of the circuit arrangement. Alternatively in order that the controlled alternating signal amplitude may be held constant despite variations in amplitude of the input alternating signal within correction limits it may be integrated and compared with a direct potential to produce the third control signal.

Embodiments of the invention will now be described by way of example, with reference to the accompanying drawings, in which: Figure 1 shows in block schematic form a first embodiment of a circuit arrangement according to the invention Figure 2 shows the locus of the controlled alternating signal, Figure 3 shows a possible construction for part of the circuit arrangement shown in Figure 1 in greater detail; and Figure 4 shows in block schematic form an alternative embodiment of a circuit arrangement according to the invention.

As shown in Figure 1 the circuit arrangement has an input 1 to which a control signal may be applied and an input 2 to which the alternating signal is applied. The control input 1 and the output of an oscillator 3 are connected to inputs of a control logic circuit 4 in which they are processed. The outputs of the control logic circuit 4 are fed to first and second up/down counters 5 and 6 which count under the control of the control logic circuit 4. The outputs of the counters 5 and 6 are fed to inputs of the first and second digital to analogue converters 7 and 8 respectively.

The input 2 is connected to a first input of a first balanced modulator 9 via a first phase shifting circuit 10 which advances the phase of the input signal by 45" and to a first input of a second balanced modulator 11 via a second phase shifting circuit 12 which retards the phase of the input signal by 45".

The output of the digital to analogue converter 8 is connected to a further input of the modulator 9 while the output of the digital to analogue converter 7 is connected to a further input of the modulator 11. The outputs of modulators 9 and 11 are summed in amplifier 13 the output of which is connected to an output terminal 14 of the circuit arrangement. The output of amplifier 13 is also fed to a gain control circuit 15 in which the amplitude of the desired signal at terminal 14 is compared with a reference value. The gain control circuit 15 generates an output which is fed to the digital to analogue converters 7 and 8.

In operation the alternating signal whose phase is to be controlled is fed to input 2.

The control signal applied to terminal 1 which may be generated via switch contacts for manual control or may be a signal generated elsewhere in the system by a comparison of the phase of the controlled alternating signal with a desired signal, is fed to the control logic circuit 4. The control logic circuit 4 produces outputs which when fed to the up/down counters cause them to count in a desired direction. The control logic circuit 4 comprises interconnected logic elements which act on the information at the control input 1 and produce outputs which cause the counters 5 and 6 to count up or down, which determine whether clock pulses from the oscillator 3 are applied to the counters 5 and 6, and which cause the counters to reverse their direction of count when they reach both maximum and minimum counts.

The counters 5 and 6 are arranged to count up from a minimum (which may be zero) to a maximum count and then reverse direction and count back down to minimum.

The counters are arranged so that initially one is set to a minimum and the other to half the difference between the minimum and the maximum count. This is achieved by generating a reset pulse in the control logic circuit 4 and applying this pulse to the appropriate inputs of the counters. Thus when clock pulses are fed to counters 5 and 6 they count cyclically one being effectively a quarter of a cycle behind the other. The outputs of the counters are fed to digital to analogue converters (D.A.C.'s) 7 and 8 and the resultant outputs of the D.A.C.'s 7 and 8 are triangular waveforms which are 90" out of phase with respect to each other. These triangular waveforms are fed to further inputs of modulators 9 and 11 as first and second control signals.

Figure 2 illustrates the action of the modulators 9 and 11 when fed with the alternating signal and the control signals.

The vector of the amplitude of the output of the first modulator 9 when fed with the first control signal is indicated by the reference 200 while the vector of the amplitude of the output of the second modulator 11 when fed with the second control signal is indicated by the reference 201. If the first and second control signals were pure sine and cosine waves the locus of the vector of the sum of the outputs of the modulators 9 and 11 would follow the outer circle 202 showing that while the phase was changing the amplitude remained constant. However when control signals are applied that are not pure sine and cosine waveforms the locus of the sum of the outputs of the modulators does not lie on that circle and hence the amplitude of the output is changing. In particular if the control waveforms are triangular in form the locus of the summed outputs of the modulators is as indicated by reference 203. This can be shown as follows.

When the first control signal 200 is at zero the second control signal 201 is at +1 hence the output is 100% at zero phase. When the first control signal 200 is at +1 the second control signal 201 is at zero and hence the output is 100% at +900. However when the first control signa is at 0.5 the second control signal is also at 0.5 and hence the output is 70% at +45 and when the first control signal is at -0.4 and the second control signal is at -0.6 the output is 72% at +2140 (or - -146").

In order to reduce the fluctuation in the amplitude of the summed outputs of the modulators the output of amplifier 13 is fed to a gain control circuit 15 which compares the amplitude of controlled alternating signal at the output of amplifier 13 with a reference value. The reference value may be the amplitude of the alternating signal at terminal 2 but may alternatively be a direct potential. The alternative enables the output to be set to a desired value regardless of possible (limited) fluctuations of the amplitude of the signal at terminal 2. In order to compare the amplitude of the signal at the output of amplifier 13 with a direct potential it can be fed to an integrating circuit which may be a simple R/C integrator. The output of the gain control circuit is fed to the D.A.C.'s 7 and 8 as their reference poten tials and is arranged to increase the reference potential when the amplitude of the output of amplifier 13 is too low and to decrease the reference potential when the amplitude of the output of amplifier 13 is too high. By this means it can be arranged that the locus of the vectors of the summed outputs of modulators 9 and 11 follows that indicated by the inner circle 204. In practice the amplitude of the output signal is set to a lower value than that indicated by the inner circle 204 as this will only allow for variations in amplitude caused by the triangular control waveforms. If the amplitude is set to a lower value the feedback circuit including gain control circuit 15 will enable fluctuations of the amplitude of the input signal, non ideal characteristics of the modulators, and phase differences between the signals applied either to the signal or control inputs of other than 90" to be compensated for.

The number of stages of the up/down counters 5 and 6 and the resolution of the D.A.C.'s 7 and 8 are selected to provide the desired precision of setting the phase change. It should be noted that the phase change produced is not linear when this embodiment is used there being an approximately two to one change per counter step over different parts of the range 0 to 360".

Further non linearity of phase change will be produced by other non-ideal factors e.g.

phase differences of other than 90" between signals applied to each of the modulators.

The up/down counters 5 and 6 may be realised from standard integrated circuits, for example those sold by Mullard Limited under the reference number HEF4029. The -D.A.C.'s 7 and 8 may also be realised from standard integrated circuits, for example those sold by Analogue Devices Limited under the reference number AD7530. The modulators 9 and 11 may be those sold by National Semiconductors Inc. under the reference number LM1596 and the phase shifting circuits 10 and 12 simple R-C networks.

One possible form for the control logic circuit 4 is shown in Figure 3. The input from oscillator 3 is via a terminal 300 and is fed to one input of a two input AND gate 301 the output of which is connected to the clock inputs of the up/down counters 5 and 6 via a terminal 302. The control signal applied to terminal 1 is fed to two differential amplifiers 303 and 304. The amplifier 303 produces an output signal to open an OR gate 305 when the control signal is more negative than a first reference potential applied to the positive input of a differential amplifier 303 and the amplifier 304 producing an output signal to open OR gate 305 when the control signal is more positive than a second reference potential applied to the negative input of differential amplifier 304.

Thus clock pulses will be applied to the up/down counters 5 and 6 when the control signal is above one reference potential or below the other reference potential. In one example the reference potentials were +3.5 volts. Thus when the control signal was between -3.5 volts and +3.5 volts neither amplifier 303 nor 304 produced an output to open OR gate 305 and the clock pulses to the counters 5 and 6 were inhibited but when the control signal exceeded 3.5 volts in either direction the appropriate amplifier produced an output to open the OR gate .305 and remove the inhibit on the clock pulses.

The output of amplifier 303 is also connected to the set input of a set/reset bistable circuit 306 while the output of amplifier 304 is fed to the reset input. The outputs of bistable 306 are fed to pulse generators 307 and 308, which may conveniently be monostable multivibrators or may be simple resistor-capacitor differentiating networks, which produce a short pulse each time the bistable 306 changes state. The outputs of pulse generators 307 and 308 are connected to the inputs of an OR gate 309 the output of which is connected to one input of two OR gates 310 and 311. The output of OR gate 310 is connected to the clock input of a clocked bistable circuit 312 while the output of OR gate 311 is connected to the clock input of a further clocked bistable circuit 313. The output of bistable 312 is fed via a terminal 314 to the up/down counter 6 to determine its count direction and similarly the output of bistable 313 is fed via a terminal 315 to the up/down counter 5 to determine its count direction.

In order to reverse the direction of count of the up/down counters 5 and 6 at the maximum and minimum counts the appropriate signals are fed from the counters to terminals 316 and 317 respectively. These signals when applied through OR gate 311 and 310 respectively will cause bistable circuits 313 and 312 to change state thus changing the signals at terminals 315 and 314 and hence changing the direction of count of counters 5 and 6.

Two push buttons 320 and 321 are provided to enable manual control of phase.

When either push button is depressed OR gate 305 is opened to allow counters 5 and 6 to be clocked and depending on which push button is depressed bistable 306 will be set or reset to determine whether the phase is to be advanced or retarded. A third push button 322 is provided to enable the arrangement to be reset to a known state and the output from push button 322 is fed through a driver 323 to the reset inputs of bistables 306, 312 and 313 and to a terminal 324 from whence it is fed to counters 5 and 6 to set them to a desired initial count.

It will be apparent that after the reset button has been operated operation of push button 320 or the presence of a control signal more positive than +3.5 volts will cause bistable 306 to change state and hence bistables 312 and 313 to change state. This will cause counters 5 and 6 to change count direction. Thus if in the reset state the counters are set such that when applied to the modulators 9 and 11 they cause the phase of the alternating signal to be advanced then operation of push button 320 or the presence of the positive control signal will cause the phase of the alternating signal to be retarded. Conversely operation of the push button 321 or the presence of a control signal more negative than -3.5 volts will cause the phase of the alternating signal to be advanced.

Various modifications can be made to this embodiment without departing from the scope of the invention. For example the control waveforms need not be triangular in form and can have a phase difference of other than 90". A 90" phase difference gives the best performance but provided that the phase difference is not 1800 a phase controlled output will still be produced but the available amplitude will be decreased, i.e.

the comparator will have to vary the control voltages over a wider range for a given output amplitude, and the linearity of phase change per step of the up/down counters will be degraded.

A single up/down counter together with appropriate logic circuitry could be used to produce the two control signals. The two phase shifting networks 10 and 12 could be replaced by a single network giving a 90" phase shift or a phase shift of some other value not totalling 1800.

An alternative embodiment of a circuit arrangement according to the invention is shown in Figure 4. Blocks performing the same function as those shown in Figure 1 have been given the same reference numerals.

The circuit arrangement shown in Figure 4 is essentially that of Figure 1 with a different control signal generation system.

With this embodiment the control signals are generated by means of a sine/cosine potentiometer 40. The sine/cosine potentiometer is connected between a bias potential V and the output of gain control circuit 15.

The wipers are connected to the control inputs of modulators 9 and 11 and pick off sine/cosine related voltages from the potentiometer 40. The amplitude of these voltages is dependent on the output of the gain control circuit 15 and thus can be varied to compensate for varying input signal amplitude or for non-ideal characteristics of the modulators 9 and 11. Compensation will also be provided when the phase difference between the alernating signal inputs to modulators 9 and 11 are not 90" out of phase, for example due to temperature changes altering the characteristics of the phase shifting networks 10 and 12 or varying frequency of the input alternating signal since an R/C phase shifter is frequency dependent.

The arrangement according to Figure 4 is only suitable for manual control of the phase of the output signal but if automatic control is required this could be achieved by means of servo-control of the potentiometer 40 by the addition of a control loop controlled by a reference signal.

WHAT WE CLAIM IS: 1. A circuit arrangement for controlling the phase of an alternating signal applied to its input comprising first and second balanced modulators, means for feeding the alternating signal to the first and second balanced modulators such that the signal applied to the first modulator is out of phase but not in antiphase with that applied to the second modulator, means for generating first and second alternating control signals the first control signal being out of phase but not in antiphase with respect to the second control signal, means for applying the first control signal to the first modulator, means for applying the second control signal to the second modulator, means for summing the outputs of the first and second modulators, means for comparing the amplitude of the summed outputs of the first and second modulators with a reference value and for generating a third control signal dependent upon the result of the comparison, means for controlling the amplitude of the first and second control signals in response to the third control signal such that the summed amplitude of the outputs of the first and second modulators tends towards a constant value, the summed outputs of the first and second modulators being the controlled alternating signal.

2. A circuit arrangement for controlling the phase of an alternating signal applied to its input comprising first and second balanced modulators, means for feeding the alternating signal to the first and second balanced modulators such that the signal applied to the first modulator is out of phase but not in antiphase with that applied to the second modulator, means for generating first and second control signals each control signal being a cyclically variable direct voltage, the cyclic variation for the first control signal being similar to that for the second control signal but being out of phase though not in antiphase therewith, means for applying the first control signal to the first modulator, means for applying the second control signal to the second modulator, means for summing the outputs of the first and second modulators, means for comparing the amplitude of the summed outputs of the first and second modulators with a reference value and for generating a third control signal dependent upon the result of the comparison, means for controlling the amplitude of the first and second control signals in response to the third control signal such that the summed amplitude of the outputs of the first and second

**WARNING** end of DESC field may overlap start of CLMS **.

Claims

**WARNING** start of CLMS field may overlap end of DESC **. phase of the alternating signal to be advanced then operation of push button 320 or the presence of the positive control signal will cause the phase of the alternating signal to be retarded. Conversely operation of the push button 321 or the presence of a control signal more negative than -3.5 volts will cause the phase of the alternating signal to be advanced. Various modifications can be made to this embodiment without departing from the scope of the invention. For example the control waveforms need not be triangular in form and can have a phase difference of other than 90". A 90" phase difference gives the best performance but provided that the phase difference is not 1800 a phase controlled output will still be produced but the available amplitude will be decreased, i.e. the comparator will have to vary the control voltages over a wider range for a given output amplitude, and the linearity of phase change per step of the up/down counters will be degraded. A single up/down counter together with appropriate logic circuitry could be used to produce the two control signals. The two phase shifting networks 10 and 12 could be replaced by a single network giving a 90" phase shift or a phase shift of some other value not totalling 1800. An alternative embodiment of a circuit arrangement according to the invention is shown in Figure 4. Blocks performing the same function as those shown in Figure 1 have been given the same reference numerals. The circuit arrangement shown in Figure 4 is essentially that of Figure 1 with a different control signal generation system. With this embodiment the control signals are generated by means of a sine/cosine potentiometer 40. The sine/cosine potentiometer is connected between a bias potential V and the output of gain control circuit 15. The wipers are connected to the control inputs of modulators 9 and 11 and pick off sine/cosine related voltages from the potentiometer 40. The amplitude of these voltages is dependent on the output of the gain control circuit 15 and thus can be varied to compensate for varying input signal amplitude or for non-ideal characteristics of the modulators 9 and 11. Compensation will also be provided when the phase difference between the alernating signal inputs to modulators 9 and 11 are not 90" out of phase, for example due to temperature changes altering the characteristics of the phase shifting networks 10 and 12 or varying frequency of the input alternating signal since an R/C phase shifter is frequency dependent. The arrangement according to Figure 4 is only suitable for manual control of the phase of the output signal but if automatic control is required this could be achieved by means of servo-control of the potentiometer 40 by the addition of a control loop controlled by a reference signal. WHAT WE CLAIM IS:

1. A circuit arrangement for controlling the phase of an alternating signal applied to its input comprising first and second balanced modulators, means for feeding the alternating signal to the first and second balanced modulators such that the signal applied to the first modulator is out of phase but not in antiphase with that applied to the second modulator, means for generating first and second alternating control signals the first control signal being out of phase but not in antiphase with respect to the second control signal, means for applying the first control signal to the first modulator, means for applying the second control signal to the second modulator, means for summing the outputs of the first and second modulators, means for comparing the amplitude of the summed outputs of the first and second modulators with a reference value and for generating a third control signal dependent upon the result of the comparison, means for controlling the amplitude of the first and second control signals in response to the third control signal such that the summed amplitude of the outputs of the first and second modulators tends towards a constant value, the summed outputs of the first and second modulators being the controlled alternating signal.

modulators tends towards a constant value, the summed outputs of the first and second modulators being the controlled alternating signal.

3. A circuit arrangement as claimed in Claim 2 in which the phase relation between the cyclic variations for the first and second control signals is 90".

4. A circuit arrangement as claimed in Claims 1, 2 or 3 in which the signal applied to the first input of the first modulator is substantially 90" out of phase with that applied to the first input of the second modulator.

5. A circuit arrangement as claimed in Claim 1 or Claim 4 when dependent on Claim 1 in which the first control signal is substantially 90" out of phase with the second control signal.

6. A circuit arrangement as claimed in Claim 1, Claim 4 when dependent on Claim 1, or Claim 5 in which the first and second control signals have triangular waveforms.

7. A circuit arrangement as claimed in Claim 1, Claim 4 when dependent on Claim 1, Claims 5, or Claim 6 in which the means for generating the first and second control signals comprises an oscillator, first and second up/down counters arranged to be clocked by the oscillator and initially set so that when one is at the minimum count the other is at half the difference between the minimum and the maximum count, first and second digital to analogue converters to which respective outputs of the first and second counters are connected, and means for applying the third control signal to the first and second digital to analogue converters as their reference voltage, the outputs of the digital to analogue converters being the first and second control signals.

8. A circuit arrangement as claimed in Claim 7 comprising means for inhibiting the clocking of the first and second counters at a selected time.

9. A circuit arrangement as claimed in Claim 2 or 3 in which the means for generating the first and second control signals comprises a sine/cosine potentiometer.

10. A circuit arrangement as claimed in any preceding claim in which the reference value is the amplitude of the alternating signal at the input of the circuit arrangement.

11. A circuit arrangement as claimed in any one of Claims 1 to 9 in which the controlled alternating signal is integrated and compared with a direct potential to produce the third control signal.

12. A circuit arrangement for controlling the phase of an alternating signal substantially as described herein with reference to Figures 1, 2 and 3 or to Figures 2 and 4 of the accompanying drawings.