GB1582125A

GB1582125A - Telecommunication systems

Info

Publication number: GB1582125A
Application number: GB1532476A
Authority: GB
Original assignee: General Electric Co PLC
Current assignee: General Electric Co PLC
Priority date: 1977-07-14
Filing date: 1977-07-14
Publication date: 1980-12-31

Description

(54) IMPROVEMENTS IN OR RELATING TO TELECOMMUNICATION SYSTEMS (71) We, THE GENERAL ELECTRIC COMPANY LIMITED, of 1 Stanhope Gate, London W1A 1EH., a British Company, do hereby declare the invention for which we pray that a patent may be granted to us, and the method by which it is to be performed to be particularly described in and by the following statement: The present invention relates to telecommunication systems and more particularly to time division multiplex telecommunication switching exchanges.

In the present invention all the signals transmitted between the subscribers and the switching exchange are digital and include signalling and synchronisation signals.

It is an object of the present invention to identify the signalling and synchronisation signals from the digital speech signals and to synchronously lock the switching exchange to each incoming signal.

According to the present invention there is provided a time division multiplex telecommunication switching exchange including storage means for storing a sequence of digital signals of a call, means for detecting a predetermined synchronisation code from said stored digital signals, recording means for recording the bit position in the time slot at which said predetermined synchronisation code is detected for each call, and interrogation means, responsive to said recording means for checking the validity of the digital signal relating to synchronisation and signalling in each call.

For the purposes of the present invention a call signal includes the signals received from and sent out to calling subscriber and called subscribers.

The storage means for storing a sequence of digital signals of a call preferably comprises a serial shift register tapped at digit intervals corresponding to the digit intervals of said synchronisation code, the coincidence of said code and predetermined ones of said tappings being arranged to produce a synchronisation reference signal. The recording means may include, in respect of each direction of transmission through the exchange, a cyclic register containing, in respect of each channel on the multiplex path a record of the identity of the current time slot in that channel with respect to the position of said synchronisation reference signal for that channel, the cyclic register being clocked at the multiplex channel rate so that said record of the identity of the current time slot is output from the register once in each time slot of the particular channel.

The record of the identity of the current time slot may consist of a count which is initiated by said synchronisation reference signal and which is increased by unity each time it is output from the register.

The exchange may include a cyclic register in respect of each of two directions of transmission through the exchange, each such cyclic register being clocked at the multiplex rate and containing a number of stages equal to the number of multiplex time slots so that the cycle time is equal to the bit period of each channel, each cyclic register being loaded with one bit value when a said synchronization reference signal arises in respect of the associated channel and being loaded with the other bit value when the synchronisation condition fails or is not sought.

Channel framing is preferably synchronised in the two directions of transmission, coincidence of said one bit-values at the outputs of the two cyclic registers being arranged to store a record of the multiplex channel time slot in which said coincidence occurs and to produce an enabling pulse at each occurrence of said coincidence, said enabling pulse constituting a clock input for said serial shift register.

The exchange may include a cyclic register arranged to store in respect of each channel a record of the required supervisory condition for that channel, the cyclic register being clocked at the channel multiplex rate so that each said record is output from the register at the individual channel bit-rate, any record of a required supervisory scan condition being loaded into a further cyclic register which is clocked at the channel multiplex rate, any such loading of this further register being effective to lock out any further input until the required supervisory scan is completed or aborted, the output of this further cyclic register being a supervisory enable signal in synchronism with the particular multiplex channel for which synchronism is required.

The exchange preferably includes a scanning circuit in respect of each direction of transmission, the scanning circuit including an input connected to the associated multiplex highway, gating means arranged to select, by means of said register containing a record of the identity of the current time slot in each individual channel, and said supervisory enable signal, signalling time slot associated with a particular channel, means for checking for the presence of signalling patterns associated with inoperable conditions and indicating a genuine signalling situation in the absence of said conditions.

The exchange also preferably includes a scanning circuit in respect of each direction of transmission, said scanning circuit including an input connected to the associated multiplex highway, gating means arranged to select, by means of said register containing a record of the identity of the current time slot in each individual channel and said supervisory enable signal, synchronisation time slots associated with a particular channel, means for checking for the presence of a valid synchronisation pattern and inhibiting communication on this channel in the absence of the synchronisation pattern.

In such a switching exchange for a system in which each channel in operation comprises a sequence of data words, each data word comprising a plurality of intelligence bits and a single signalling or synchronizing bit, each frame of the individual channel signal preferably comprises at least one synchronisation pattern, the synchronization patterns and invalid signalling patterns are generated continuously and, by means of said cyclic registers containing a record of the identity of the current time slot in each channel, in synchronism with the channel signal on the multiplex highway, the data words are counted and decisions on the validity of the signalling and the synchronization pattern are made when a count of the number of words in a frame has been made, irrespective of the starting point of the count in a frame.

One embodiment of the present invention will now be described, by way of example, with reference to the accompanying drawings in which: Figure 1 shows block diagrammatically a time division multiplex switching exchange according to the present invention; Figure 2 shows the sequence of transmission of speech, synchronising and signalling bits in the exchange of Figure 1; Figure 3 shows the synchroniser circuit for the exchange of Figure 1; Figure 4 shows the synchronisation plane control associated with the synchronizing circuit of Figure 3; Figure 5 shows the synchronizing memories associated with Figures 3 and 4; Figure 6 shows the supervisory connection memory of the exchange of Figure 1; and Figure 7 shows the forward supervisory scanner of the exchanger of Figure 1 associated with the supervisory connection memory of Figure 6.

The basic principles of the signals sent and received by each subscriber connected to the exchange of figure 1 are described in our U.K. Patent No. 1,535,169. In brief the signals are all digital in form, incoming analogue speech being converted into digital signals at each subscribers handset for transmission to the exchange, and outgoing digital signals being reconverted to audio speech signals at each subscribers handset.

Each subscriber has a four-wire connection to the exchange. For forward transmission, i.e. from a calling to a called subscriber, his transmitter is connected to one input of a multiplexing forward switching stage FSS by one pair and his receiver is connected to one output of a demultiplexing forward switching stage FSS' by the other pair. All other subscribers, of which there may be a total of 64 or more, are similarly connected. The multiplexing and demultiplexin switching stages are then connected by a 32 time-slot highway FH so that 32 one-way (forward) communications can be conducted simultaneously. A similar path through the exchange is provided for the backward communication, i.e.

from a called to a calling subscriber, by a multiplexing backward switching stage BSS, a demultiplexing backward switching stage BSS' and a backward highway BH. In order that each subscriber may be both a called and a calling party at different times the corresponding line terminals on the multiplexing stages FSS and BSS are commoned and similarly the corresponding line terminals on the de-multiplexing stages FSS' and BSS'. The commoning of line terminals cause no confusion because the connection memories FCM and BCM select only the calling pair at one end and only the called pair at the other end in the relevant time slot.

When a subscriber wishes to initiate a call he lifts the handset and this, in a preferred embodiment, results in a series of marks ("1" digits) being sent to the exchange. The exchange has line scanning means and the call connections are set up as described in the above-mentioned Patent No. 1,535,167. In a preferred embodiment the users bit rate is 64 Kbits/sec and a further 8 Kbits/sec of signalling and synchronising bits are added giving a total bit rate per subscriber of 72 Kbits/sec. The arrangement of the users data and signalling and synchronising bits on the individual line pairs is shown in Figure 2.

Referring now to Figure 2a, when a call is in progress a first eight bits 1 to 8 comprise speech or users data and each ninth bit is a signalling or synchronising bit.

Referring to Figure 2b, these ninth bits are divided into alternate groups of eight signalling bits S1-S8 and eight synchronising bits S9-S16. The average pulse repetition frequency of the signalling and the synchronizing bits is thus 4 KHz each.

In order to be able to process the speech signals and the signalling and synchronizing signals it is necessary to identify, in respect of every call, the position of the signalling and synchronising signals for the particular call and to remember this position for the duration of the call. This is accomplished by feeding the signal from a selected call into a 64 bit shift register which is tapped every ninth bit, and searching in a known manner for the synchronizing pattern by means of a pattern recognition circuit.

Since the speech or data can imitate the synchronizing pattern, the chance of false synchronization recognition is reduced by checking for two successive patterns. The recognition of these is recorded by means of a suitable counter. When two successive patterns are recorded the main exchange system clock records the position of the eighth synchronizing bt within a frame of 144 time slots at the individual subscriber, i.e. low speed, bit rate (144 time slots = 16 x 9 bit periods). The position of this reference time slot is recorded in a central sync memory.

Having recorded the position of the synchronizing signals for a call on the forward highway occupying one of the 32 highway time slots the synchronizing system is used in a similar manner to record the position of the synchronizing signals for the same call on the backward highway. (The synchronizing system is then ready to be stepped on to any further time slot that requires synchronising).

The synchronising system described can be used to synchronise a large number of calls. In the present invention the maximum possible number of calls is thirty-one since the switches FSS, FSS1 and BSS, BSS1 are capable of handling up to thirty-one calls on thirty-one separate highway time slots (thirty-second time slot being used as described in the above Patent for line scanning).

The present invention will now be described in greater detal with reference to Figure 1, in which up to thirty-one calling subscribers, detcrmined by a forward connection memory F.C.M., are connected to called subscribers determined by a backward connection memory B.C.M.

To each highway is connected a respective supervisory scan circuit FSSC and BSSC and a common synchronising circuit S. Each supervisory scan circuit and the synchronising circuit is connected to a plane control circuit P.C. in a bi-directional manner.

The plane control circuit P.C. is connected to three separate memory circuits; a synchronizer memory SM, a supervisory connection memory SCM and a plane control memory P.C.M.

The supervisory scanning circuits FSSC and BSSC are necessary in order to monitor the time slot, in which a call is being transmitted, both in the forward and backward signalling direction to sense whether either the called or calling subscriber is sending signalling and also to check that valid synchronism is still present.

In the system of the present invention a considerable saving in hardware is achieved by having only one pair of scanners to monitor thirty-one available time slots and operating these scanners to monitor the time slots in rotation.

Referring now to Figure 3a the synchronizer S includes a 64 bit register 30, a synchronisation pattern recognition circuit 31, an 8 bit counter 32 which is clocked at the subscribers bit rate, an 8 bit latch 33, a magnitude comparator 34 and an AND gate 35.

In operation, data is selected from the particular one of the 32 time-slots in the highway under supervision, and is fed in to the register 30 under the control of a sync-enable pulse (SE) at the subscribers bit rate but which is present only at the required highway time slot (see Figure 4). When, after a minimum of 64 bits have been entered into the shift register, a correct synchronising pattern is recognised, the synchronisation pattern recognition circuit emits a pulse which causes the 8 bit latch 33 to store the count present in the 8 bit counter 32. The counter 32 is arranged to have a cyclic count of 144 bits so that the stored count is an arbitrary figure for comparison with the subsequent check. The count in the counter 32 is continuously compared by comparator 34 with the staticised count in the latch 33.When the next synchronisation pattern is recognised (which, if the first pattern was a correct synchronisation pattern, will be after a further 144 bits), the magnitude comparator 34 will produce an output pulse which will combine with the pulse from synchronisation pattern recognition circuit 31 is AND gate 35 to produce the synchronisation reference pulse S.R.

A slight delay in the operation of latch 33 will ensure that the current 'sync' count is compared with the preceding 'sync' count rather than with itself. The register 30 will be reset, for example by the pulse S.R., to enable it to be ready to receive the data from the next time slot on the forward highway or the same time slot in the backward highway.

Figure 3b shows a time-out circuit for the synchroniser which aborts the synchronising operation on any particular highway time slot if synchronisation is not recorded within a predetermined period. The operation of the circuit is that the sync-enable pulse SE triggers a monostable device 36 which monostable includes a registor capacitor network R.C. The network R.C. determines the period of the unstable state and in a preferred embodiment is approximately 50msecs. Thus after triggering, and unless independently reset within this period, the monostable will reset after 50 msecs producing an output pulse to set a latch 37.

The latch 37 provides when set an ABORT signal which is used in the common control (not shown) of the exchange to indicate that the synchronisation on the call has not been obtained and also to move the synchronisation scan circuit to the next call requiring synchronisation. If synchronisation is obtained before the 50 msec period has expired the synchronisation reference pulse S.R. resets the monostable and resets the latch via an OR gate 38. The latch 37 may also be reset via OR gate 38 by a pulse from the plane control.

Referring now to Figure 4, the synchronisation plane control, which is part of the plane control circuitry P.C. of Figure 1, includes three 32 x 1 bit recirculating registers or memories 400, 401, 402 which are respectively the forward and backward synchronisation registers and the sync enable register. These registers are clocked at the highway bit-rate i.e. at 32 x the subscribers bit-rate, and operate continuously.

The two registers 400 and 40 are required to store a '0' for each of the highway time slots whose sync condition has been recognised, and a '1' for any time slot which is not under supervision, that is, in which there is no call, or in which a failure of synchronisation has been detected. The register inputs consist of a load '0' input, a load '1' input and a load/recirculate control input. A '1' on the latter enables the other two inputs which both require a '1' to load their respective bits. A '0' on the control input prevents any loading but allows circulation of the register contents.

If there is no call in a particular time slot there will be no supervisory pulse and a '1' must be loaded into the corresponding register position. The supervisory pulse input is therefore applied to an inverter and then through OR-gate 403 and 404 to the control input and the load '1' input. Similarly, if a sync failure is detected (Figure 7), a '1' must be entered. A 'sync-fail-forward' input is therefore applied to the two OR-gates 403 and 404.

Finally, when a sync condition is recognised a '0' must be entered. The SR pulse is therefore applied by way of an OR-gate 409 and an AND-gate 405 to the control input and the load '0' input. The AND-gate 405 is enabled by the output of the register for the same time slot, which prior to this loading will be a '1' (see Figure 4a).

An abort signal (figure 3) is also effective via OR-gate 409 in loading a '0'. Although this is a false indication in the register 400 it does allow the sync check to proceed to the backward highway or the next highway time slot requiring a check. The abort signal is effective elsewhere for security purposes.

Memory 401 operates in similar manner by way of OR-gates 406 and 407, and AND-gate 408.

Gate 405 and corresponding gate 408 for memory 401 effect sequencing of the sync checks on the forward and backward highways in that order. The enabling signals A' and B' for these gates are derived from Figure 4a from which it can be seen that A' = A but B' = B.A. Thus gate 408 is not enabled until A is '0', which occurs when synchronisation has been recognised on the forward highway and a '0' loaded into the memory 400 in the time-slot in question. Failure to find a sync pattern within a specified period produces an 'abort' signal, which is similarly effective to load a '0' into memory 400.

Once a '0' has been loaded into memory 400 and has appeared at the output A, gate 405 is disabled by the '0' and gate 408 is enabled by B' when the output at B is a '1'. Cycling of the memory 401 continues as for memory 400 until the sync pattern is recognised, SR becomes a '1' and a '0' is loaded into memory 401.

The same time slot in both memories will then contain a '0' so that OR gate 414 is enabled by the two '0's to produce a '0' output.

There will be a similar pair of 0's in the two memories for each time slot that has been checked for a sync pattern on both forward and backward highways. Apart from such pairs of '0's the memories will contain all 'l's.

In addition to controlling the memories 400 and 401, the circuit of Figure 4a also controls the selection of the forward or backward highway for the checking of synchronisation. The two functions do, of course, required to go hand in hand. Thus, while memory 400 is being processed, and before a sync condition has been detected, the A output will be a succession of '1's. This will enable the gate 411 of Figure 4a so that its output will be the inverse of the data input from the forward highway. At the same time gate 410 will be disabled, producing a '0' output which, in turn, will disable NAND-gate 412 so that it produces a permanent '1' output. Data from the backward highway is thus ignored while the forward highway is being checked. Gate 413 then acts simply as an inverter and reproduces the forward highway data for supply to the synchroniser.

When A' and B' become '0' and '1' respectively, the position is reversed and data from the backward highway is passed to the synchroniser for sync checking.

When a new call arises and a sync check has to be made, a 'sync enable' pulse is required at every highway time slot alotted to that call, to select the sync data in Figure 3a. It is therefore necessary to store and produce this pulse throughout the period of the sync check.

This is the function of the recirculating register 402. This register has thirty-two stages one-bit wide and normally contains all '0's which are circulated by clock pulses at the highway bit rate. When a sync check has to be made, a '1' is entered into this register in the appropriate time slot and recirculated for the duration of the check. Only a single '1' must be stored at a time to prevent confusion in the synchroniser.

When a new call arises, a supervisory pulse arises with it on every highway time slot allotted to it. Initially the synchronisation will not have been checked and the outputs of registers 400 and 401 will be '1'. These outputs, via OR gate 414 will, with the accompanying supervisory pulse, enable a NAND-gate 415. The third input to this gate will normally be a '1' from the Q output of a bistable latch 416.

Gate 415 therefore produces a '0' output which is applied by way of an inverter 421 and an OR-gate 417 to the control input of register 402 to enable loading. The inverted output is also applied to the load '1' input so that a '1' is loaded into the particular time slot. This '1' is then recirculated through the register 402, producing a sync enable pulse SE each time it arrives at the output. The appropriate highway time slot is thus identified repeatedly.

In addition to loading register 402, the '0' output of gate 415 is used to latch a D-type bistable 416 and so disable the gate 415 against any further inputs. The '0' output of gate 415 is effective at the D input at the next clock pulse so changing the Q output to '0'.

When the synchronization condition is finally established and a '0' appears at the output of gate 414, this '0' is inverted and together with the '1' content of register 402, enables gate 418 and by way of the load '0' intput, replaces the circulating '1' with a '0' thus re-setting the register 402 to a quescent state. The '1' output of the gate 418 is also applied after inversion, to the 'preset' input of latch 416, so setting the Q output to '1' in readiness for the next sync check. The Q output was prevented from reverting to a '1' during the sync check process by feeding the '0' Q output to the 'clear' input. This is only over-ridden when the present input finally arises.

In addition to clearing theregister 402 and unlatching the latch 416, the '1' output of gate 418 is applied to reset the abort latch 37 of Figure 3(b), if it had in fact been triggered.

Referring now to Figure 5 the synchronisation memory SM includes two shift registers 50, 51, for the forward and backward highway synchronisation respectively. Since they are similar in operation only one will be described in detail. Register 50 is a recirculating 32 x 8 bit wide register, clocked at the highway bit rate, which effectively stores for each of the 32 time slots on the highway the position of the last synchronisation bit if any, in a 144 subscriber-bit frame as will be explained. The count in each word of register 50 is incremented by +1 each time the word appears at the register output, by means of the addition circuit 52. A decoder 53 decodes each output of the shift register 50 and indicates the type of bit which should be present on each time slot on the forward highway.

The operation of the circuit is as follows: When the synchroniser S recognises a synchronisation pattern on one of the highways it produces the sync reference signal SR. This signal is produced on the last bit of a complete frame,i.e. the one hundred and forty-fourth bit, and in respect of a particular subscriber and corresponding particular one of the thirty-two highway time slots.

The signal SR is fed as one input to both AND gate 54 and AND gate 55. A further output from the synchroniser S derived from signal A' is fed directly to the other input of AND gate 54 and via an inverter 56 to the other input of AND gate 55. This other output from synchroniser S channels the sync reference pulse SR to either the forward or backward synchronisation register. Assuming the synchronisation operation is being performed by the synchroniser S in respect of the forward highway the signal A' will be a logic "1" and combined with the logic "1" of the sync reference signal SR the AND gate 54 will emit a logic "1" output to the register input circuit 57.The sync reference pulse SR occurs during the last bit of a complete frame of 144 speech, signalling and synchronising bits because the last bit (the one hundred and forty-fourth) corresponds to the last synchronising bit. This bit is identified by the binary number 100()1111, which is equal to 143, since the numbering sequence is from 0 to 143.During the first bit interval of the next frame the input circuit 57 load 00000001 in to the bottom of the shift register. '1' rather than '0' is loaded in to the shift register at the beginning of the frame to obtain the correct phasing of the cycle in view of the various time delays in the circuit. this value '1', which identifies the second subscriber-time slot, is progressively shifted towards the top of the shift register and is decoded as the second bit of the next frame which indicates that it is the second speech bit which is present on the forward higway at that time.

The number 00000001 is applied to the adder 52 where it is incremented by 00000001 to form 00000010, which binary number is fed in to the bottom of the shift register via input circuit 57. This process is repeated until the number circulating in the shift register in respect of the particular subscriber reaches 10001111 (binary 143). The circuit 61 detects this number, for example by performing a magnitude comparison, and sets the count for that time slot to a count of zero (00000000) from which the cycle then proceeds.

Each subscriber on the forward highway whose synchronisation has been successfully checked will have had '1' loaded in to the register 50 at the appropriate time in its 32 slot cycle. Thus, at any time, the register 50 will contain among its 32 stages a selection of 8-bit words, in no particular sequence, each indicating the current bit number in a sequence of 144, of the corresponding subscriber. The decoder 53 therefore indicates, for each subscriber on the forward highway in turn, its position in its own 144-slot frame and thus its identity, i.e. speech, signalling or synchronisation bit.

The backward register operates in the same way as the forward register, being triggered into operation by the inverter 56 when the A' pulse becomes a logic "0". Gate 54 is simultaneously disabled.

Referring now to Figure 6, the supervisory plane control determines the connection of line-scanner, receiver/sender and supervisory scanner in each of the thirty-two time slots.

The requirements for each time slot are stored in a supervisory connection memory by means of a date bus from central control. The memory is a 32-stage 4-bit wide recirculating shift register 600 which is clocked at the highway bit rate. According to the requirements of each particular time slot it contains a selection from the following table of 4-bit code words.

D C B A 0 0 0 0 Disable Supervisory/T/D/Sync/Line Scan.

0 0 0 1 ) 0 0 1 0 ) 4 Receiver/senders forwards 0 0 1 1 ) O 1 0 0 ) O 1 0 1 ) 0 1 1 0 ) Spare 0 1 1 1 ) 1 0 0 0 Line Scan only 1 0 0 1 ) 1 0 1 0 ) 4 Receiver/senders backwards 1 1 1 1 4 1 1 0 0 ) 1 1 o 1 ) 1 1 1 0 Spare 1 1 1 1 Supervisory only These codes are supplied from the common control.

To ensure that each code is loaded in to the correct time slot of the shift register 600 an enable pulse EN is supplied to AND gate 601 together with a load pulse LCC from the common control. The enable pulse EN is produced as shown in Figure 6a, where the count in a five-bit counter 611 is compared in a magnitude comparator 612 with the time slot number given by the common contrl and stored in latch 613. The number in the five-bit counter 611 is always equal to the time slot which is at the bottom of registers 600 and therefore when the number in the counter 611 equals the desired time slot number in latch 613 an enable pulse EN is produced which loads the data present at the input "CC data" into the correct time slot in register 600. The output of the supervisory connection memory 600 is in a 4 bit parallel form which is decoded by a decoder 602.The decoding produces an output pulse on selected output lines to initiate line scanning, (LS) the receiver sender (RS), and/or a supervisory pulse (SU).

It should be noted that this supervisory pulse (SU) merely indicates that supervision of the particular time slot is required.

The pulse SU is supplied to a lock out latch and register circuit which is similar in operation to the lock out latch 416 and register circuit 402 of Figure 4. The lockout latch and register circuit includes a NAND gate 603, a D type flip-flop 604 operating as the latch by feeding its Q output as one input of the NAND gate 603. The other input to NAND gate 603 is from the output of inverter 422 (Figure 4) and is therefore the inverse of the output of gate 414. Thus a pulse SY is present only when synchronism has been obtained on both forward and backward highways for the particular time slot being considered. This is to ensure that no supervisory scanning is permitted of time slots on the forward or backward highway which still require synchronising.The necessity for this is that if synchronism has not been obtained for a particular time slot the supervisory scanners have no means of selecting the signalling and synchronising bit from the data stream and meaningful supervision is therefore not possible.

A recirculating shift register 607, similar to the register 402 of Figure 4, is loaded with a '1' corresponding to the supervisory pulse SU. The latch 604 disables the gate 603 and locks out any subsequent supervisory pulse. The stored '1' is thus the only '1' in the register and it emerges at the output as a supervisory enable pulse SUP-EN once in each low-speed time slot to enable the supervisory scanners (see Figure 7). Supervisory scanning of a call is required to cover 144 such time slots and the single '1' recycles accordingly.

When the particular call has been supervised, a supervisory scanner reset pulse SS is applied to the gate 609 to load a '0' into the register 607, replacing the '1'. Alternative inputs for clearing the register 607 are a reset pulse CC from the common control and the '1' output of a gate 60 which is enabled by the coincidence of a '1' output from the register 607 and the absence of a supervisory pulse SU.

The forward and backward supervisory scanners FSSC and BSSC are identical, Figure 7 showing one embodiment of the common arrangement.

The purpose of the supervisory scanner is to check the signalling and synchronisation situation on (say) the forward highway. It has to check, over a period of 144 subscriber's time-slots, whether, in the particular highway time-slot seized by the supervisory plane control, signalling and synchronization is being properly received. It has therefore to distinguish between all '0's, all 'l's and idle patterns on the one hand and genuine signalling on the other.

To this purpose the highway signal is applied to the input I/P and to four non-equivalence gates 700, 701, 702 and 703. The second input of gate 700 is a permanent '1' so that the output of this gate is the highway signal but inverted. Gate 701 has a permanent '0' input so that the input data is simply repeated. The second input of gate 702 is the idle pattern derived serially from a generator 704, and the second input of gate 703 is the sync pattern derived serially from a generator 705. The bits of the idle and sync patterns are presented at the appropriate times by the generators 704 and 705. If there is a match with the idle pattern then there is a '0' output of gate 702 for every bit of the pattern. Similarly, if there is a match with the sync pattern there is a '0' output of gate 703 for every bit of the pattern.

The outputs of gates 700-703 are applied as inputs to respective AND-gates 722-725. The other input to gates 722, 723 and 724 is a '1' pulse for every signal bit of the particular time-slot (i.e. subscriber) that the supervisory plane control circuit (Figure 6) has latched on to. This signal is derived from an AND-gate 717 to which the SUP EN pulse from Figure 6 is applied together with a signal derived from the sync memories of Figure 5 giving a '1' pulse for all signalling bits in all time slots.

The output of gate 703 is similarly applied to an AND-gate 725 having a second input which is a '1' pulse for every sync bit of the particular time-slot that the supervisory plane control circuit has latched on to. This latter signal is similarly derived from an AND-gate718 to which the SUP EN signal and an 'all-sync' signal is applied.

A '1' output from each of the gates 722-725 will set a respective latch 706-709 to give a '1' output. The three 'signalling' latches 706, 707 and 708 have their outputs applied to a NAND-gate 710 so that only when all three have been set will the output of gate 710 be a '0'. Gate 710 output is applied to an inhibit input of a latch 711 so that this latch can only be set to a '1' output when the inhibit input is '0' and thus when all three latches 706, 707 and 708 have been set.

The '1' output of latch 711 constitutes a 'signalling flag' indicating that genuine signalling has been received, and is referenced SUP FLAG (F) in the drawing (i.e. supervisory flag-forward).

During the eight signalling bit periods, any disparity between the highway signal bit and the permanent '1' into gate 700 will set the latch 706. Any such disparity means that an "all 'l's" signal has not been received.

Similarly, an absence of "all '0's" will set the latch 707, and an absence of a match with the idle pattern will set the latch 708. In the absence of these three conditions it can be assumed that genuine signalling is present and the signalling flag pulse will arise.

The sync pattern, on the otherhand, is required to be present. When it is not present any mismatch will set the latch 709 to produce a '1' output which is applied to the 'D' input of a latch 712. Thus, when this latch is triggered at the end of the scan period a 'sync fail' flag arises as a '1' output from latch 712.

The derivation of the idle and sync patterns by the generators 704 and 705 is illustrated in Figure 7a. The 8-bit sync pattern is wired in a store 720 the output of which is permanently applied to a selector circuit 721. The current sync bit identity is derived from the sync memories of Figure 5 and this identity is de-coded to select the appropriate wired-in sync bit, which is then applied to the gate 703.

The idle pattern is generated serially in similar manner. The two latches 711 and 712, providing signalling or 'SUP.' and 'sync fail' flags, are clocked in the following manner.

The combined sync and signalling bits are applied to a latch 714 which is switched at each bit. The output transitions, and thus the sync and signalling bits, are applied to a counter 713 which effectively makes a single count of sixteen, i.e. one frame period, before locking out further input data. The single frame pulse is then applied to the latches 711 and 712 to record their input signals at that time.

The frame pulse is also applied to a gate 716 to sense the 'SUP flag' condition. The latter signal is applied to the gate 716 by way of an inverter 715 so that if no genuine signalling has been recognised at this time a '1' output is produced from the gate 716 as a supervisory scan reset signal SS. This is applied to gate 609 in Figure 6 to clear the register 607 and allow the supervisory plane control to latch on to another time slot requiring supervision.

The period of the scan is chosen to be such that a complete frame (144 bits from one subscriber) of speech, synchronisation bits and signalling bits can be received. At the bit rates being considered, this period is 2 m secs. It should be noted that the scanning sequence may be commenced at any time during a frame since the signalling and synchronising bits are applied to the latch 714 irrespective of identity in a frame and are merely counted by the counter 713 until sixteen have been received. Thus no time is lost or wasted in waiting for a particular point in the frame.

The 'sync fail' indication is applied to register 400 or 401 as explained with reference to Figure 4.

All latches will be reset by a 'SUP RESET' from the plane control at the end of the 2 m sec period, which period is sufficiently long to allow a complete frame of information to be received by the supervisory scanner and to allow the output pulses of the supervisory scanner to be processed.

A buffer store 720 provides an interface between the supervisory scanner and the common control. This buffer is an 8-bit parallel fed store of which one bit, 'A', a records an 'abort' state, a second bit 'B' records a signalling condition on the backward highway, a third bit, 'F', a signalling condition on the forward highway, A and B together an abort state on the backward highway and A and F together an abort state on the forward highway. The remaining five bits provide a count of the particular highway slot on which these conditions prevail.

The signalling indications are required to remain in the buffer until read by the common control, after which the buffer is cleared by a clear pulse from the common control. A latch 721 is therefore provided to supply a single clock pulse to the buffer 720. The SUP.FLAG signals are applied to the respective stages by way of OR-gates 722 and 723 and also, by way of NOR gates 724 and 725, to the clear input of the latch 721. Normally therefore, both of these signals will be '0', so enabling gate 725 and applying a '0' to the clear input of latch 721. It is thus held in a Q=O state and clock pulses (at highway bit rate) applied to it have no effect.

If either scanner detects signalling and produces a SUP.FLAG signal, this is applied to the appropriate stage of the buffer. It also produces a '0' from gate 724 and a '1' from gate 725. The clear input is consequently removed and the next clock pulse triggers the Q output to 1. The SUP FLAG bit is consequently written in to the buffer but directly it is it clears the latch again, so disabling any further clock inputs.

At the same time a running count of the highway slot number is applied to the last five stages of the buffer and the count coincident with the SUP.FLAG signal is written in by the single clock pulse. The buffer will retain this information until it is read out by the common control and cleared.

If an abort pulse arises from the synchronser of Figure 3 this is gated with the forward/backward signal A' from Figure 4a to provide a '1' input to gate 722 or 723 accordingly, in addition to being applied directly to the abort stage of the buffer. The latch 721 is again latched momentarily to produce a write-in pulse and immediately cleared.

The buffer 720 thus provides signalling and abort information, together with the appropriate slot number for read-out by the common control.

WHAT WE CLAIM IS: 1. A time-division-multiplex telecommunication switching exchange including storage means for storing a sequence of digital of a call, means for detecting a predetermined synchronisation code from said stored digital signals, recording means for recording the bit position in the time slot at which said predetermined synchronisation code is detected for each call, and interrogation means, responsive to said recording means for checking the validity of the digital signals relating to synchronisation and signalling in each call.

2. A switching exchange according to Claim 1, wherein said storage means for storing a sequence of digital signals of a call comprises a serial shift register tapped at digit intervals corresponding to the digit intervals of said synchronisation code, the coincidence of said code and predetermined ones of said tappings being arranged to produce a synchronisation reference signal.

3. A switching exchange according to Claim 2, wherein said recording means includes, in respect of each direction of transmission through the exchange, a cyclic register containing, in respect of each channel on the multiplex path a record of the identity of the current time slot in that channel with respect to the position of said synchronisation reference signal for that channel, the cyclic register being clocked at the multiplex channel rate so that said record of the identity of the current time slot is output from the register once in each time slot of the particular channel.

4. A switching exchange according to Claim 3, wherein said record of the identity of the current time slot consists of a count which is initiated by said synchronisation reference signal and is increased by unity each time it is output from the register.

5. A switching exchange according to Claim 2, 3 or 4, including a cyclic register in respect of each of two directions of transmission through the exchange, each such cyclic register being clocked at the channel multiplex rate and containing a number of stages equal to the number of multiplex time slots so that the cycle time is equal to the bit period of each channel, each cyclic register being loaded with one bit value when a said synchronisation reference signal arises in respect of the associated channel and being loaded with the other bit value when the synchronisation condition fails or is not sought.

6. A switching exchange according to Claim 4, wherein channel framing is synchronised in the two directions of transmission, and coincidence of said one bit values at the outputs of the two cyclic registers is arranged to store a record of the multiplex channel time slot in which said coincidence occurs and to produce an enabling pulse at each occurrence of said coincidence, said enabling pulse constituting a clock input for said serial shift register.

7. A switching exchange according to any of Claims 2 to 6 including a cyclic register arranged to store in respect of each channel a record of the required supervisory condition for that channel, the cyclic register being clocked at the channel multiplex rate so that each said record is output from the register at the individual channel bit-rate, any record of a required supervisory scan condition being loaded into a further cyclic register which is clocked at the channel multiplex rate, any such loading of this further register being effective to lock out any further input until the required supervisory scan is completed or aborted, the output of this further cyclic register being a supervisory enable signal in synchronism with the particular multiplex channel for which synchronism is required.

8. A switching exchange according to Claim 7, as appendent to Claim 3, including a scanning circuit in respect of each direction of transmission, an input connected to the associated multiplex highway, gating means arranged to select, by means of said register containing a record of the identity of the current time slot in each individual channel and said supervisory enable signal, signalling time slots associated with a particular channel, means for checking for the presence of signalling patterns associated with inoperable conditions and indicating a genuine signalling situation in the absence of said conditions.

9. A switching exchange according to Claim 7 as appendent to Claim 3, including a scanning circuit in respect of each direction of transmission, an input connected to the associated multiplex highway, gating means arranged to select, by means of said register containing a record of the identity of the current time slot in each individual channel and said supervisory enable signal, synchronization time slots associated with a particular channel, means for checking for the presence of a valid synchronisation pattern and inhibiting communication on this channel in the absence of the synchronisation pattern.

10. A switching exchange according to Claim 8 and Claim 9 for a system in which each

**WARNING** end of DESC field may overlap start of CLMS **.

Claims

**WARNING** start of CLMS field may overlap end of DESC **. control and cleared. If an abort pulse arises from the synchronser of Figure 3 this is gated with the forward/backward signal A' from Figure 4a to provide a '1' input to gate 722 or 723 accordingly, in addition to being applied directly to the abort stage of the buffer. The latch 721 is again latched momentarily to produce a write-in pulse and immediately cleared. The buffer 720 thus provides signalling and abort information, together with the appropriate slot number for read-out by the common control. WHAT WE CLAIM IS:

1. A time-division-multiplex telecommunication switching exchange including storage means for storing a sequence of digital of a call, means for detecting a predetermined synchronisation code from said stored digital signals, recording means for recording the bit position in the time slot at which said predetermined synchronisation code is detected for each call, and interrogation means, responsive to said recording means for checking the validity of the digital signals relating to synchronisation and signalling in each call.

channel in operation comprises a sequence of data words, each data word comprising a plurality of intelligence bits and a single signalling or synchronising bit, wherein each frame of the individual channel signal comprises at least one synchronisation pattern, synchronisation patterns and invalid signalling patterns are generated continuously and, by means of said cyclic registers containing a record of the identity of the current time slot in each channel, in synchronism with the channel signal on the multiplex highway, the data words are counted and decisions on the validity of the signalling and the synchronisation pattern are made when a count of the number of words in a frame has been made, irrespective of the starting point of the count in a frame.

11. A time-division-multiplex telecommunication switching exchange substantially as hereinbefore described with reference to the accompanying drawings.