GB1580173A - Memory addressing apparatus - Google Patents

Description

(54) IMPROVEMENTS IN MEMORY ADDRESSING APPARATUS (71) We, SPERRY RAND CORPORATION, A Corporation organised under the laws of the State of Delaware, United States of America, of 1290 Avenue of The Americas, New York, New York 10019, United States of America, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement:- The present invention relates to memory addressing apparatus, and in particular it relates to a memory address translator, and to apparatus including memory address translators.

The present invention provides a memory address translator which may in certain circumstances by used to reduce the physical size of memory that is required for a particular application.

In some applications, such as cathode ray tube display memories, it is necessary to address a single memory concurrently by way of two separate sources. In the case of a cathode ray tube display memory, it is desirable to store character information in a memory which can be addressed by row and by column corresponding to a particular screen position. The row number and the column number of a particular character location may be concatenated to form a single memory address. However, neither the number of rows nor the number of columns may be a power of two. In this case, the amount of hardware memory required, as determined by the number of address lines from the combined row and column addressing, may be at least twice the amount of memory required by the number of character locations on the display screen. Thus, direct addressing of the memory by row and by column would result in a waste of memory locations by a factor of two.

A typical cathode ray tube display screen may comprise 25 rows and 80 columns. This represents 2,000 character locations on the display screen. In order to store the character which is to be displayed at each location on the display screen, it is necessary to have a 2,000-word memory.

However, the simplest way to address the memory would be by row and by column.

With a display screen of 25 rows and 80 columns, a total of five binary bits would be required to address the memory by row and seven binary bits would be required to address the memory by column. This would result in a total of 12 addressing bits which could uniquely select 4,096 memory locations. As we have previously seen, however, the maximum amount of memory needed is 2,000 words. This results in a memory waste of 2,096 words. Direct addressing of the display memory in this manner would result in a memory of more than twice the size which is actually required by the number of screen locations.

Application of the present invention, as will be explained, enables the 12 bits of the row and the column address to be translated into a single 1 l-bit address, and applied to a memory of 2,048-word locations, thus reducing the memory waste to only 48 words.

According to the present invention a memory address translator for translating a two-part binary input address comprises a first part of a digits defining between 2"-' and 2" part-addresses, and a second part of b digits defining between 2b-' and 2b partaddresses, where b is greater than a, in which the translated address contains a+b-l digits and has a plurality of its least significant digits identical with the corresponding digits of the second part of the input address and its remaining digits formed by applying the first part and the remainder of the second part of the input address to a read-only memory array to be decoded into numerically consecutive binary numbers.

The invention will be further described by way of example with reference to the accompanying drawings, in which Figure 1 is a block diagram representing a method of addressing a memory as known in the prior art.

Figure 2 is a block diagram of the method of addressing a memory utilising the present invention, and Figure 3 is a flow chart showing the steps in computing the size of the read-only memory required in applying the present invention.

Referring first to Figure 1, a memory address consists of two portions represented as 10 and 12 in Figure 1, and consisting respectively of a and b binary digits which are to be applied to a random access memory 14; the address portions 10 and 12 may be row and column addresses, for example, of a character in a cathode ray tube display. In the example mentioned above there may be 25 rows and 80 columns. In order to address any one of 25 rows a 5-digit binary address is required, and in order to address any one of 80 columns a 7-digit binary address is required so that in this example a and b are respectively 5 and 7. The total number of address lines must therefore be 12, and a 12-digit binary address is capable of addressing 4096 address locations. The arrangement depicted in Figure 1 as would have been used in the prior art therefore uses a random access memory 14 of 4096 locations in an application in which the maximum number of addresses which will actually be utilized is only 2,000.

Figure 2 shows the situation in the present invention. As before, the address portions 10 and 12 consist respectively of a and b digits, in the example given these being respectively 5 and 7. Of the larger address portion 12, a number X of the least significant digits form the corresponding least significant digits of the address to be applied to the random access memory 14.

The remaining digits from the address portion 12, and all the digits from the address portion 10, which taken together do not form a series of numerically consecutive binary numbers, are applied to a read-only memory 16 where they are translated into a series of numerically consecutive binary numbers to form the remaining more significant digits of the random access memory address. In the example considered above, this reduces the total number of digits required for addressing the memory 14 from 12 to 11, correspondingly reducing the size of the memory 14 from 4,096 locations to only 2,048 locations.

In the above example, the total number of input lines is N=a+b, and, of these, X lines address the memory 14 directly, while the remaining N-X lines address the readonly memory 16, and the signals thereon are converted to signals on N-X-1 lines to form the remainder of the memory address.

It is necessary in carrying out the invention to be able to determine the value of X, and the method of doing this will now be explained with reference to the flow chart shown in Figure 3.

In this Figure the letters N, X, "a" and "b" still represent the same quantities as previously referred to in Figure 1 and Figure 2; i.e., a represents the number of bits in addressing source 10; b represents the number of bits in addressing source 12; N represents the total number of bits in the concatenated address and X represents the number of binary address lines which should be selected to address the memory 14 directly. In addition, the following initials will be used for the quantities indicated: LRVU, largest row value used (24); LRVP, largest row value possible (31); LCVU, largest column value used (79); LCVP, largest column value possible (128); and LMAP, largest memory address possible; the numbers in parenthesis denote the numbers resulting from use of 25 rows and 80 columns.

Start the flow chart, in Figure 3, in block 18, labelled START. First, referring to block 20, let N-X represent the number of address lines to be translated, i.e., the number of binary address lines to connect to the ROM translator 16 instead of directly to the memory 14, as illustrated in Figure 2.

In the flow chart, the quantity LRVU represents the upper limit of the first addressing means, and LCVU represents the upper limit of the second addressing means. Next, in Block 22, select the value for a such that 2(a-') is less than LRVU is less than or equal to 2 where a is an integer. As previously explained, a is the number of bits required to represent the upper limit of the first addressing means.

Moving to block 24 in Figure 3, the same operation is performed for the upper limit of the second addressing means. Select the value for b such that 2(b-') is less than LCVU is less than or equal to 2b where b is an integer. As previously explained, b is the number of bits required to represent the upper limit of the second addressing means.

Moving to block 26 in Figure 3, it is next necessary to calculate the value for N. N is equal to a+b. Then, in block 28, start the iterative process by setting a trial value for X equal to 0 and, in block 30, calculate the value of LRVP by using the formula LRVP2a1.

Note that all of the steps involved in blocks 20 through 30 performed thus far represent basic initialization procedures and as such need not be performed in any particular order. Any order of the above steps will represent in a proper procedure; however, hereafter, many of the steps must be performed in the specific order listed in order to perform the iterative process properly.

Next, in block 32, calculate the value of LCVP by using the formula LCVP2(b-X) 1.

Note that at this point in the iterative process we have set X equal to zero. Thus, the value of LCVP on the first iteration will be 2b-'; however, the value of LCVP will be recalculated at each iterative step.

Next, calculate the value of LMAP as shown in block 34 by using the formula LMAP=2fN-X) and calculate the value of WASTE as shown in block 36 by using the formula WASTE=(LRVP-LRVU) . (LCVP+1) + (LCVP-LCVU) . (LRVU+1).

It is then necessary to make a comparison in order to determine whether by using the value of X at this point, the amount of memory wasted is larger than half of the largest memory address possible.

Thus, make the comparison and answer the question: "Is WASTE greater than LMAP divided by two?" This is represented by block 38 in Figure 3. If the answer to this comparison is "no" proceed to block 40 and stop. The value of X used in this iteration will then be utilized in the address translation mechanism illustrated in Figure 2. If the answer is "yes", proceed to block 42 and increment the quantity X by one.

It is then necessary to make the comparison and answer the question in block 44: "Is LCVU an odd or an even number?" If the answer is "even", proceed to block 46 and recalculate a new value of LCVU by dividing the old value of LCVU by two. If the answer is "odd", proceed to block 48 instead and recalculate a new value of LCVU by using the formula old LCVU+1 new LCVU= -1 2 where the new value of LCVU to the left of the equality sign signifies the new value of LCVU and the value of LCVU to the right of the equality sign indicates the old value of LCVU. After completing this step, return to block 32 where the next iteration is commenced by recalculating LCVP and LMAP.

Proper operation and use of the means for determining which bits to translate may be better illustrated by an actual example.

Utilizing the previous example given in a typical cathode ray tube display screen comprising 25 rows and 80 columns, the proper operation of the flow chart will be illustrated.

Starting at block 18 and moving to block 20 in Figure 3, we shall let N-X represent the number of address lines to translate.

Here both N and X will be determined at a later step in this process. Since there are 25 rows in the display screen, we will let LRVU represent the upper limit for addressing from this source. Thus, in order to uniquely select 25 rows, the upper limit of the first addressing source, or LRVU, is 24. Since the display screen contains 80 columns, the upper limit of the second addressing source, or LRVU, is 79.

In block 22, we select the quantity a to be equal to 5 so that 25-' equals 24 equals 16 is less than 24 (LRVU), is less than or equal to 25, i.e., 32. A similar calculation is performed with b and LCVU as in block 24 using the value of 7 for b; thus, in block 26, we can readily calculate that N=a+b=5+7=12.

Setting X equal to 0 in block 28, we start the iterative process by calculating LRVP in block 30 as 2-1=32-1=31 and in block 32 calculating LCVP=27- 1=128-1=127.

Proceeding to block 34 in Figure 3, we calculate LMAP which at this point is just 2N=212=4,096. In block 36 we perform our first waste calculation.

WASTE=(31-24) . (127+1)+(127-79) .

(24+ 1)=2,096.

Making the comparison in block 38, we note that WASTE (2,096) is greater than LMAP divided by 2 (4,096+2=2,048) so that we continue the iterative process by incrementing X by one in block 42 and observing that old LCVU (79) is an odd number so we proceed next to block 48.

In block 48 in Figure 3, we start the second iterative process by recalculating a new value of LCVU: (79+1) new LCVU--( )-l=39.

2 Proceeding then to block 32 and subsequent blocks, we will find in this iterative process that LMAP=2,048; LRVP=31; LRVU=24; and LCVP=63.

Calculating WASTE we will find that WASTE=1,048, which is still greater than LMAP divided by 2=1,024. Incrementing X another time and returning to block 32, via block 48, we repeat this iterative process.

In the present example, when X=4, LCVP=7; LCVU=4; LMAP=5l2. Then, calculating WASTE, WASTE=131, which is less than LMAP divided by 2=256. Thus, we proceed from block 38 to block 40 in Figure 3 and stop the iterative process with X=4.

Thus, referring back to Figure 2, N=12 and X=4; thus four of the address lines from the combined concatenated address resulting from address source 10 and address source 12 are utilized directly to address the memory 14 while the remaining eight address lines (N-X address lines) are utilized to address the ROM translator 16.

A 256-word (28) X 7-bit ROM translator 16 is required to make the appropriate address conversion. The 7-bit address output of the ROM translator 16 is then utilized in conjunction with the four bits coming directly from the address sources to form an ll-bit address for the memory 14. Thus, with 11 bits of address, a 2,048-word memory 14 is required. In this example, this results in a saving of 2,048 words of memory at a cost of only 256 7-bit ROM words.

The actual encoding of the ROM translator 16 is quite simple. The first address source 10 and the second address source 12 values are started at 0, corresponding to a ROM address equal to 0. The ROM output at this address is also set to 0. This corresponds to screen location 0 (row 0, column 0). The column value is then incremented by 1. The ROM input address=0 and so is the ROM output at this row address (0). The column count is continually incremented until it reaches its maximum value, in this example, 79. At this point, the ROM input address is 1002 and the ROM output is 1002. The column value now returns to 0 while the row value is incremented by 1. Thus, the ROM input address becomes 10002 and the ROM output at this address is set to 1012 which is the next consecutive RAM address. It is to be noted that ROM input address 1012 through 1112 have been skipped. Thus the ROM input addresses will have gaps, but the RAM input addresses will count.

consecutively. This process is continued until all memory location values have been exhausted.

Thus, it can be seen that there has been shown and described a novel apparatus for conserving memory when that memory is to be addressed concurrently from separate address sources. It is to be understood, however, that various changes, modifications and substitutions in the form and details of the described apparatus can be made by those skilled in the art without departing from the scope of the invention as defined by the following claims.

WHAT WE CLAIM IS: 1. A memory address translator for translating a two-part binary input address comprising a first part of a digits defining between 2a-1 and 2" part-addresses, and a second part of b digits defining between 2b-l and 2b part-addresses, where b is greater than a, in which the translated address contains a+b-l digits and has a plurality of its least significant digits identical with the corresponding digits of the second part of the input address and its remaining digits formed by applying the first part and the remainder of the second part of the input address to a read-only memory array to be decoded into numerically consecutive binary numbers.

2. A memory address translator designed and arranged to operate substantially as shown in and as herein described with reference to Figures 2 and 3 of the accompanying drawings.

3. Cathode ray tube display apparatus in which a translator according to claim 1 or claim 2 is arranged to translate an address in the display in the form of a row-address together with a column-address and to apply the translated address to a randomaccess memory.

**WARNING** end of DESC field may overlap start of CLMS **.

Claims (3)

**WARNING** start of CLMS field may overlap end of DESC **. is less than LMAP divided by 2=256. Thus, we proceed from block 38 to block 40 in Figure 3 and stop the iterative process with X=4. Thus, referring back to Figure 2, N=12 and X=4; thus four of the address lines from the combined concatenated address resulting from address source 10 and address source 12 are utilized directly to address the memory 14 while the remaining eight address lines (N-X address lines) are utilized to address the ROM translator 16. A 256-word (28) X 7-bit ROM translator 16 is required to make the appropriate address conversion. The 7-bit address output of the ROM translator 16 is then utilized in conjunction with the four bits coming directly from the address sources to form an ll-bit address for the memory 14. Thus, with 11 bits of address, a 2,048-word memory 14 is required. In this example, this results in a saving of 2,048 words of memory at a cost of only 256 7-bit ROM words. The actual encoding of the ROM translator 16 is quite simple. The first address source 10 and the second address source 12 values are started at 0, corresponding to a ROM address equal to 0. The ROM output at this address is also set to 0. This corresponds to screen location 0 (row 0, column 0). The column value is then incremented by 1. The ROM input address=0 and so is the ROM output at this row address (0). The column count is continually incremented until it reaches its maximum value, in this example, 79. At this point, the ROM input address is 1002 and the ROM output is 1002. The column value now returns to 0 while the row value is incremented by 1. Thus, the ROM input address becomes 10002 and the ROM output at this address is set to 1012 which is the next consecutive RAM address. It is to be noted that ROM input address 1012 through 1112 have been skipped. Thus the ROM input addresses will have gaps, but the RAM input addresses will count. consecutively. This process is continued until all memory location values have been exhausted. Thus, it can be seen that there has been shown and described a novel apparatus for conserving memory when that memory is to be addressed concurrently from separate address sources. It is to be understood, however, that various changes, modifications and substitutions in the form and details of the described apparatus can be made by those skilled in the art without departing from the scope of the invention as defined by the following claims. WHAT WE CLAIM IS:

1. A memory address translator for translating a two-part binary input address comprising a first part of a digits defining between 2a-1 and 2" part-addresses, and a second part of b digits defining between 2b-l and 2b part-addresses, where b is greater than a, in which the translated address contains a+b-l digits and has a plurality of its least significant digits identical with the corresponding digits of the second part of the input address and its remaining digits formed by applying the first part and the remainder of the second part of the input address to a read-only memory array to be decoded into numerically consecutive binary numbers.

2. A memory address translator designed and arranged to operate substantially as shown in and as herein described with reference to Figures 2 and 3 of the accompanying drawings.

3. Cathode ray tube display apparatus in which a translator according to claim 1 or claim 2 is arranged to translate an address in the display in the form of a row-address together with a column-address and to apply the translated address to a randomaccess memory.