GB1576970A - Sense and refresh amplifier - Google Patents
Sense and refresh amplifier Download PDFInfo
- Publication number
- GB1576970A GB1576970A GB5345877A GB5345877A GB1576970A GB 1576970 A GB1576970 A GB 1576970A GB 5345877 A GB5345877 A GB 5345877A GB 5345877 A GB5345877 A GB 5345877A GB 1576970 A GB1576970 A GB 1576970A
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- United Kingdom
- Prior art keywords
- node
- voltage
- devices
- transistor
- low
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
- G11C11/404—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Dram (AREA)
Description
(54) SENSE AND REFRESH AMPLIFIER
(71) We, SIGNETICS CORPORATION of 811 East Arques Avenue, Sunnyvale, California 94086, United States of America, a Corporation organized and existing under the laws of the State of California, United States of
America, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement :
The present invention relates to a sense and refresh amplifier circuit.
Sense and refresh circuits have long been known in the art. Optimization of the circuits for operation has been disclosed in "Optimiza tion of the Latching Pulse for Dynamic Flip
Flop Sensors" by W.T. Lynch and H.J. Boll,
IEEE Journal of Solid State Circuits; Vol.
SC-9 and "Storage Array and Sense/Refresh
Circuit for Single Transistor Memory Cells" by
K.U. Stein, A. Sihling and E. Doering, IEEE
JSSC, Vol. SC-7, Oct. '72.
However, sense and refresh circuits have long suffered from excessive power consumption and design constraints. Thus there is a need for a sense and refresh circuit having low power consumption and improved design for use in high density integrated circuits.
According to one aspect of the present invention there is provided a sense and refresh amplifier circuit comprising an amplifier of the type that is capable of assuming first and second conditions in response to signals at first and second input nodes, the amplifier being in the form of first and second cross coupled active devices coupled to said first and second input nodes, the first and second devices having control, common and output elements, the control element of the first device being coupled to the output elenlent of the second device and the second device and the control element of the second device being coupled to the output element of the first device, each device being capable of assuming a high and a low conduction state, and restore circuitry means connected between the first and second input nodes and a terminal for connection to a voltage supply for selectively connecting the voltage supply at the terminal solely to the active device assuming a low conduction state, wherein said restore circuitry means includes third and fourth active devices having control elements coupled respectively to said first and second input nodes through fifth and sixth active devices and having corresponding electrodes coupled respectively to the first and second input nodes; said fifth and sixth active devices in use being alternately in a low and a high conduction state in correspondance with the low and high conduction state of said first and second active devices and capacitive means for supplying a restoring voltage to said control elements of said third and fourth active devices whereby the first and second conductors are restored to the amplifier.
Means may be provided for alternately precharging said nodes to a predetermined state and applying stored information to the input nodes to cause the amplifier to assume first and second conditions in response to stored information.
According to a second aspect of the present invention there is provided a method of minimizing the power consumption of a sense and refresh amplifier circuit of the type having first and second cross coupled active devices with respective signal input nodes which assume high and low conduction states and restore circuitry interposed between the devices and a voltage supply terminal, the method including the step of sensing by said restore circuitry solely the signals at the input nodes and selectively connecting the voltage at the supply terminal solely to that one of the first and second devices assuming a low conduction state.
The present invention will now be explained and described, by way of example, with reference to the accompanying drawings, wherein
Figure 1 is a schematic diagram showing a sense and refresh amplifier circuit as is known in the prior art,
Figure 2 is a schematic diagram of a sense and refresh amplifier circuit in accordance with the present invention, and
Figure 3 is a timing diagram showing the operational sequence of the amplifier circuit shown in Figure 2.
Referring to Figure 1, a prior art sense and refresh amplifier of the type conventionally used in dynamic random access memories is shown. In brief, and so that the present invention may be more readily appreciated, the conventional circuit illustrated includes cross coupled MOS devices 11 and 1 2 having respective gate elements tied to first and second input nodes A and B with conunon electrodes connected to a node C. Node C is selectively connected to ground by device 14 when a clock signal s is applied to the gate of device 14.
Additional devices 16 and 18 are utilized as active loads and are connected between the voltage supply and nodes A and B respectively.
Devices 16 and 18 are also controlled by clock signal . Devices 20, 22 and 24 are utilized for precharging the circuit. Bit lines extend from nodes A and B, in a physical circuit to exhibit respective parasitic capacitances 28 representative of the actual circuit distributed capacity.
When single transistor, single capacitor stored information cells are accessed, particular storage locations represented by devices 30 and 32 are connected to the bit lines. When x is energized the storage capacitors C1/2 and C1, which may be of the variable MOS type, are connected to the respective amplifier nodes.
The differences in the capacitors C1 and C1/2 provide a differential voltage at the nodes when the signal x is enabled. Next when signal s is enabled the differential voltage is amplified and the amplifier latches in a stable state wherein one of the nodes is high and the other node is discharged toward ground potential. However, as is discussed in the first above cited reference, the shape and fall time of the node C critically determines how much charge is removed from whichever node A or B stays high and thus results in a voltage drop on the precharged node which, by design, was to remain in a charged or high condition.
Transistors 16 and 18 are provided to restore the charge with the voltage drop and tune required for restoraion dependent on the effective resistance of the transistor. A low resistance transistor 16 or 18 more quickly restores the charge but, since the transistors are of like construction and geometry, results in increased direct current in the node that goes low. In turn the devices consume excessive power which must be dissipated in a physical circuit structure. That is, there are tradeoffs in the use of the devices 16 and 18, a low resistance device being desirable for restoring charge to a high or off side, but at the same time the same low resistance transistor providing excessive current dissipation when that side assumes a low state.
By way of operative example if node A goes low and node B stays high then a current path is provided from voltage supply V to ground via transistors 16, 11 and 14. On the other hand if node B goes low and A stays high then the high current path is via transistors 18,12 and 14. This current path does not contribute to needed operation and is wasteful. The node to be restored need only be provided with a transient current just sufficient in magnitude to restore the voltage drop on the node staying high. Moreover the effective series resistance of transistors 11 and 14, in practice, when node A is low, must be of a resistance many times lower than that of transistor 16 to maintain a voltage level at node A that approximates ground potential. Thus it can be seen at best that the prior art circuitry for the proper operation provides wasteful power consumption and thus correspondingly limits the density of a circuit structure.
Referring now to Figure 2, an embodiment of the sense and refresh amplifier circuit in accordance with the present invention is shown.
First and second cross coupled devices 35 and 37 are provided having the respective source or common terminals connected to node C. The drain terminals of devices 35 and 37 are con nected respectively to nodes A and B with the gate electrode of device 37 connected to node
A and the gate electrode of device 35 connected to node B. An additional device 39 is provided connected between the node C and a ground or common terminal, with the control gate of the device further connected to be enabled by an external clock signal s. Devices 35, 37 and 39 may be optimumly designed to perform switching operations and need not have the further restraint of carrying a given amount of current as was required of the analogous devices 11,12 and 14 of the prior art.
An additional device 22 has its source and drain elements connected between nodes A and B with the gate element connected to be enabled by gate signal ;J The sense refresh amplifier circuit further includes transistor 42 connected between node
A and node E and having a control gate connected to a VR signal terminal. A further transistor 44 is connected between node A and the voltage supply and has a control element connected to node E. A variable MOS capacitor 46 is connected between node E and an additional clock signal terminal $ R. In symmetrical manner transistor 48 is provided connected between node B and node D and has a control gate connected to terminal VR. An additional device 50 is provided connected between node
B and voltage supply means V and has a control electrode connected to node D. A variable
MOS capacitor 52 is provided connected between node D and clock signal R. Although variable MOS capacitors are shown, it is to be understood that conventional capacitors may likewise be used.
Turning then to the timing diagram Figure 3, the operation of the Figure 2 circuit may now be observed. At tl the nodes A and B are precharged to a high level with P high via transistors 20 and 24. Further nodes A and B are at equal potential by virtue of transistor 22. At time t2 the precharge clock signal p goes to an off or low state. At time t3 voltage Vr precharged to a high value is lowered by a magnitude that is more than the maximum voltage drop expected on the eventual off side node (the node A or B that remains high) during the subsequent latchup when signal s is energized. The magnitude of voltage
Vr should not be lowered to less than one threshold voltage above ground potential and should preferably be positioned near the relatively high end of its range in order to optimize speed characteristics. At some predetermined time later at time t4 the x clock goes high. Devices 30 and 32 thus conduct and charge sharing occurs on respective nodes A and B. At node A storage cell capacitor 29 shares charge with parasitic capacitor 28. At node B capacitor 31 shares charge with parasitic capacitor 28. Capacitors 29 and 31, as before, provide ratios of C1/2 and C1 respectively. As a result, a differential voltage having a magnitude of approximately 200 to 400 millivolts is provided between node A and node
B. If capacitor 31 had a relatively high voltage stored there across, then node B will be at a higher potential than node A and vice versa.
Next at t6, s goes high, transistor 39 begins to conduct and the amplifier circuit latches in a condition predetermined by the differential voltage polarity that exists between nodes A and B. At the same time the shape of the falling edge of the wave fornl at node C determines the amount of charge lost from the off side node during latchup. The first mentioned above cited reference describes this phenomena. If the charge lost is not restored before the circuit goes back into the precharge portion of the cycle a poorer or deteriorated high level is refreshed onto capacitor 31 since node B is now the illustrated off side node of Figure 3.
In this case node A discharges to full ground potential through transistors 35 and 39 and causes node E to discharge to ground through transistor 42. This in turn causes switched capacitor 46 to assume a low capacity state.
Node B, even with a voltage drop, stays sufficiently high to maintain transistor 48 in an off state because of the lowered voltage on Vr, and node D will remain at a high precharged value.
Next at time t8, when the r goes high, the capacity coupling through capacitor 52 causes the node D potential to further increase and causes transistor 50 to assume the triode region of conduction. The triode region is that conduction between the completely on or saturated, and completely off states. The result is a charge restoration at node B to its absolute maximum voltage by a transient current supplied via transistor 50. On the node A side, since node E was discharged to ground, the r clock has no coupling effect and transistor 44 remains off. The result is no direct current flows from the source potential V to ground. A ground potential then results at node A and provides an absolute minimum voltage storage in the storage cell connected to the node A bit line. At time tl0, x falls, at tl 1 s and r fall and at time t14 the p signal is again provided for the precharge cycle.
Thus, it is apparent that an improved sense and refresh amplifier circuit has been provided.
In particular, the circuit has restore circuitry means for selectively connecting the supply solely to the device assuming a low conduction state and in eliminating a path for high DC current to flow for the device in a high conduction state. Further, the effective size of the respective transistors in the circuit can be chosen to be as low or as high as desirable without constraints as to the low voltage at the one side node, power dissipation or the effective series resistance of the transistor as is presently known.
WHAT WE CLAIM IS:- 1. A sense and refresh amplifier circuit comprising an amplifier of the type that is capable of assuming first and second conditions in response to signals at first and second input nodes, the amplifier being in the form of first and second cross coupled active devices coupled to said first and second input nodes, the first and second devices having control, common and output elements, the control element of the first device being coupled to the output element of the second device and the control element of the second device being coupled to the output element of the first device, each device being capable of assuming a high and a low conduction state, and restore circuitry means connected between the first and second input nodes and a terminal for connection to a voltage supply for selectively connecting the voltage supply at the terminal solely to the active device assuming a low conduction state, wherein said restore circuitry means includes third and fourth active devices having control elements coupled respectively to said first and second input nodes through fifth and sixth active devices and having corresponding electrodes coupled respectively to the first and second input nodes; said fifth and sixth active devices in use being alternately in a low and a high conduction state in correspondance with the low and high conduction state of said first and second active devices and capacitive means for supplying a restoring voltage to said control elements of said third and fourth active devices whereby the first and second conditions are restored to the amplifier.
2. A circuit as claimed in Claim 1 , wherein said restore circuitry means and means for alternately precharging and applying stored information are controlled by predetermined clock signals.
3. A circuit as claimed in Claim 1, wherein said restore circuitry means is connected to the cross coupled devices, wherein the third, fourth, fifth and sixth active devices having
**WARNING** end of DESC field may overlap start of CLMS **.
Claims (7)
1. A sense and refresh amplifier circuit comprising an amplifier of the type that is capable of assuming first and second conditions in response to signals at first and second input nodes, the amplifier being in the form of first and second cross coupled active devices coupled to said first and second input nodes, the first and second devices having control, common and output elements, the control element of the first device being coupled to the output element of the second device and the control element of the second device being coupled to the output element of the first device, each device being capable of assuming a high and a low conduction state, and restore circuitry means connected between the first and second input nodes and a terminal for connection to a voltage supply for selectively connecting the voltage supply at the terminal solely to the active device assuming a low conduction state, wherein said restore circuitry means includes third and fourth active devices having control elements coupled respectively to said first and second input nodes through fifth and sixth active devices and having corresponding electrodes coupled respectively to the first and second input nodes; said fifth and sixth active devices in use being alternately in a low and a high conduction state in correspondance with the low and high conduction state of said first and second active devices and capacitive means for supplying a restoring voltage to said control elements of said third and fourth active devices whereby the first and second conditions are restored to the amplifier.
2. A circuit as claimed in Claim 1 , wherein said restore circuitry means and means for alternately precharging and applying stored information are controlled by predetermined clock signals.
3. A circuit as claimed in Claim 1, wherein said restore circuitry means is connected to the cross coupled devices, wherein the third, fourth, fifth and sixth active devices having
control, common and output elements, the common elements of the third and fifth devices are together connected to a first input node, the common elements of the fourth and sixth devices are together connected to a second input node, the output element of the fifth device is connected to the control element of the third device and the output element of the sixth device is connected to the control element of the fourth device, the output elements of the third and fourth devices are connected to the voltage supply means, the control elements of the fifth and sixth devices are connected to additional voltage supply means, a first coupling means is provided for coupling control signals to the control element of the third device, and a second coupling means is provided for coupling signals to the control element of the fourth device.
4. A circuit as claimed in Claim 3, wherein the first to sixth active devices are field effect transistors and said additional supply has a value of not less than one field effect transistor threshold magnitude from ground potential.
5. A method of minimizing the power consumption of a sense and refresh amplifier circuit of the type having first and second cross coupled active devices with respective signal input nodes which assume high and low conduction states and restore circuitry interposed between the devices and a voltage supply terminal, the method including the step of sensing by said restore circuitry solely the signals at the input nodes and selectively connecting the voltage at the supply terminal solely to that one of the first and second devices assuming a low conduction state.
6. A sense and refresh amplifier circuit constructed and arranged to operate substantially as hereinbefore described with reference to and as illustrated in Figures 2 and 3 of the accompanying drawings.
7. A method of minimizing the power consumption of a sense and refresh amplifier, substantially as hereinbefore described with reference to Figures 2 and 3 of the accompanying drawings.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB5345877A GB1576970A (en) | 1977-12-22 | 1977-12-22 | Sense and refresh amplifier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB5345877A GB1576970A (en) | 1977-12-22 | 1977-12-22 | Sense and refresh amplifier |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| GB1576970A true GB1576970A (en) | 1980-10-15 |
Family
ID=10467890
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB5345877A Expired GB1576970A (en) | 1977-12-22 | 1977-12-22 | Sense and refresh amplifier |
Country Status (1)
| Country | Link |
|---|---|
| GB (1) | GB1576970A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0080936A2 (en) * | 1981-11-27 | 1983-06-08 | Fujitsu Limited | Dynamic semiconductor memory device |
-
1977
- 1977-12-22 GB GB5345877A patent/GB1576970A/en not_active Expired
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0080936A2 (en) * | 1981-11-27 | 1983-06-08 | Fujitsu Limited | Dynamic semiconductor memory device |
| EP0080936A3 (en) * | 1981-11-27 | 1985-11-06 | Fujitsu Ltd | Dynamic semiconductor memory device |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PS | Patent sealed | ||
| 732 | Registration of transactions, instruments or events in the register (sect. 32/1977) | ||
| PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 19961222 |