GB1576439A - Serial/parallel conversion device for a digital system - Google Patents

Description

(54) SERIAL/PARALLEL CONVERSION DEV1CE FOR A DIGITAL SYSTEM (71) We, INTERNATIONAL STANDARD ELECTRIC CORPORATION, a Corporation organised and existing under the Laws of the State of Delaware, United States of America, of 320 Park Avenue, New York 22, State of New York, United States of America, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following state ment : - This invention relates to a converter for serial-to-parallel conversion of binary elements arriving at each of the inputs.

Serial-to-parallel conversion is widely used in numerical systems. Furthermore, in PCM (pulse code modulation) systems, data received serially at several inputs and then placed in parallel form are then processed at different channel times; i.e. the serial-to-parallel conversion is followed by multiplexing. A conversion matrix using discrete elements for serial-to-parallel conversion followed by a multiplexer is described, for instance, in an article by F.

Melindo and G. Perucca in the- Technical Report No. 2 of CSELT in December 1973.

Another type of converter, using an MOS integrated circuit, is described in our British Patent Specification No. 1,468,486.

In the latter device, a first plane is provided consisting of as many :shift registers as there are groups of binary elements to be converted, and each shift register has as many cells as binary elements in a group.

A second plane is also provided which contains as many cells as the first one and to which all the binary elements, previously stored in the first plane, have been transferred while maintaining the same respective locations. The function to be performed is then obtained by a serial reading of the binary elements stored in parallel in the first plane and by a parallel reading of the binary elements stored serially in the second plane. These arrangements need many cells and friese cells are never all used at any given mo- ment. Actually, as the second plane is being read, new groups of binary elements are stored in the.first plane so that at any moment half the number of cells is unused.

So, one object of this invention is a conversion device for a numerical system eliminating the above-mentioned problem.

According to the invention - there is provided an electrical serial/parallel conversion circuit having N inputs over each of which may be received serially an -N-bit code combination, and N outputs, in which each said N-bit code-combination is so converted as to appear in parallel form on said N outputs, in which the circuit includes N shift registers each having N cells, in which each said shift register is connected to one of said N inputs so that it can receive and store an N-bit code combination arriving serially on its said input, in which the outputs of the last stages of the shift registers provide the N outputs of the conversion circuit, in which switching devices are provided each interconnecting two cells in different ones of said shift registers, the arrangement being such that with the N shift registers considered electrically as forming N columns each of N cells of a matrix the interconnections via said switches each extend diagonally with re specs to said columns and said interconnections form parallel diagonals of the matrix, and in which when a set of -N code combinations each consisting of N code bits have been received affd stored in said shift registers, the operation of said -switch- ing devices followed by the application of clock pulses two the cells causes the combinations to appear successively in parallel form on said outputs.

An embodiment of -the invention will now be described in connection with the attached drawings in which: Figure 1 is a block diagram of a oonver- ter embodying the invention; Figure 2 shows figure 1 re-drawn to present a special application and in a foldedback form; Figure 3 is a timing diagram of the signals involved in the operation of the device in figure 2; Figure 4a and 4b show the interconnection of two cells symmetrical with respect to the diagonal;- and Figures 5a and 5b show a cell of the diagonal.

Figure 1 demonstrates the principle of the converter which consists of N2 cells arranged to form N shift registers, each having N cells. Such a device is used to convert N groups of N binary elements.

Any register 1 contains N cells Cli to ClN, an input El and an output Si.

Means are also. provided for a bidirectional data transfer between each group- of two cells, hereafter called symmetrical cells, arranged symmetrically with respect to the cells of the diagonal. Thus all the symmetrical cells such as C12 and C21 can be connected together by a switch K. Ti data transfer between symmetrical cells occurs only after N binary elements have been stored in each register, i.e. once for every N shift. This last point as well as the detailed operation is explained more fully below.

Figure 2 shows a converter with four inputs and four outputs, and in folded form. Actually, a device such as the one shown in Figure 1 is not well suited to produce an integrated circuit because of the interconnections to be made between the cells arranged symmetrically with respect to the cells of the diagonal. This drawback can be eleminated by using the am rangement of Figure 2, in which all the cells which are to communicate with each other are contiguous, which elimates the interconnection problem. In the following description, we assume that the cells are MOS type circuits such as described in the above-mentioned Patent Specification.

Binary elements pass from one cell to the next following the order indicated by the arrows.

Figure 3 shows the various signals involved in the operation of the device of Figure 2. Each cell has input and output devices. Thus in the shift register if, at a given instant, the information in the output device of a cell is transferred to the input device of the next cell, on the next clock signal the information in the input device of each cell is transferred to the output device of the same cell. For the set of cells, data are transferred from the out- put device of one to the input device of the next at time signals tl. For the individual symmetrical cells of the diagonal, i.e. the cells of type Cmn, the information in the input device of a cell of type Cmn is transferred to the output device of the same cell Cmn at time signals t2 or to the output device of the symmetrical cell Cnm at time signals t'2.For cells of the diagonal, information in the input device of a cell is transferred at time signals t2 or t'2 to the output device of the same cell.

Figures 4a and 4b show two corresponding cells Cmn and Cnm (figure 4a) and the interconnections between their input devices Cmnl and Cnml and their output devices Cmn2 and Cnm2 (figure 4b).

Figures 5a and 5b show a cell of the diagonal Cii (figure 5a) and the interconnection between its input device Ciil and its output -device Cii2 (figure 5b). As mentioned above, information is entered into an input unit of any cell at time tl. At time t2, the information of any cell is transferred to the output device of the same cell. Time signals t'2 have the same effect as time signals t2 for all cells of the diagonal as shown in figure 5b, whereas for other cells the transfer between the input device of one cell and the output device of the symmetrical cell occurs as shown in figure 4b.This data transfer between symmetrical cells only occurs once every four clock signals, see figure 3 and it should also be noted that, for proper operation of the device, this transfer should occur only when all the binary elements of each group have been stored in the said device. In other words, the first binary element of each group must be entered into that device on the first time signal following a signal t'2.

In addition, the number of binary elements in each group must equal four in the example shown in figure 2 or, speaking more generally, must equal N for a device having N inputs and N outputs.

Thus we find, at outputs S4 to Si, in the first place the four binary elements received at input E4, then those received at input E3, E2 and El. Therefore we find, in parallel at the outputs, the binary elements received serially at the inputs. The binary elements received at input E4 are the first available at the outputs, while those received at input El are the last.

The various cells can be of the M type, as in the above-mentioned Patent Specification, but other technologies may be used to produce the device. The invention herein described is particularly practical when designed as an integrated circuit in which the number of cells can be greatly reduced. It could be used especially in PCM switching centers in which a large number of converters are found.

WHAT WE CLAIM TS: - 1. An electrical serial/parallel conversion circuit having N inputs over each of

**WARNING** end of DESC field may overlap start of CLMS **.

Claims (3)

**WARNING** start of CLMS field may overlap end of DESC **. Figure 2 shows figure 1 re-drawn to present a special application and in a foldedback form; Figure 3 is a timing diagram of the signals involved in the operation of the device in figure 2; Figure 4a and 4b show the interconnection of two cells symmetrical with respect to the diagonal;- and Figures 5a and 5b show a cell of the diagonal. Figure 1 demonstrates the principle of the converter which consists of N2 cells arranged to form N shift registers, each having N cells. Such a device is used to convert N groups of N binary elements. Any register 1 contains N cells Cli to ClN, an input El and an output Si. Means are also. provided for a bidirectional data transfer between each group- of two cells, hereafter called symmetrical cells, arranged symmetrically with respect to the cells of the diagonal. Thus all the symmetrical cells such as C12 and C21 can be connected together by a switch K. Ti data transfer between symmetrical cells occurs only after N binary elements have been stored in each register, i.e. once for every N shift. This last point as well as the detailed operation is explained more fully below. Figure 2 shows a converter with four inputs and four outputs, and in folded form. Actually, a device such as the one shown in Figure 1 is not well suited to produce an integrated circuit because of the interconnections to be made between the cells arranged symmetrically with respect to the cells of the diagonal. This drawback can be eleminated by using the am rangement of Figure 2, in which all the cells which are to communicate with each other are contiguous, which elimates the interconnection problem. In the following description, we assume that the cells are MOS type circuits such as described in the above-mentioned Patent Specification. Binary elements pass from one cell to the next following the order indicated by the arrows. Figure 3 shows the various signals involved in the operation of the device of Figure 2. Each cell has input and output devices. Thus in the shift register if, at a given instant, the information in the output device of a cell is transferred to the input device of the next cell, on the next clock signal the information in the input device of each cell is transferred to the output device of the same cell. For the set of cells, data are transferred from the out- put device of one to the input device of the next at time signals tl. For the individual symmetrical cells of the diagonal, i.e. the cells of type Cmn, the information in the input device of a cell of type Cmn is transferred to the output device of the same cell Cmn at time signals t2 or to the output device of the symmetrical cell Cnm at time signals t'2.For cells of the diagonal, information in the input device of a cell is transferred at time signals t2 or t'2 to the output device of the same cell. Figures 4a and 4b show two corresponding cells Cmn and Cnm (figure 4a) and the interconnections between their input devices Cmnl and Cnml and their output devices Cmn2 and Cnm2 (figure 4b). Figures 5a and 5b show a cell of the diagonal Cii (figure 5a) and the interconnection between its input device Ciil and its output -device Cii2 (figure 5b). As mentioned above, information is entered into an input unit of any cell at time tl. At time t2, the information of any cell is transferred to the output device of the same cell. Time signals t'2 have the same effect as time signals t2 for all cells of the diagonal as shown in figure 5b, whereas for other cells the transfer between the input device of one cell and the output device of the symmetrical cell occurs as shown in figure 4b.This data transfer between symmetrical cells only occurs once every four clock signals, see figure 3 and it should also be noted that, for proper operation of the device, this transfer should occur only when all the binary elements of each group have been stored in the said device. In other words, the first binary element of each group must be entered into that device on the first time signal following a signal t'2. In addition, the number of binary elements in each group must equal four in the example shown in figure 2 or, speaking more generally, must equal N for a device having N inputs and N outputs. Thus we find, at outputs S4 to Si, in the first place the four binary elements received at input E4, then those received at input E3, E2 and El. Therefore we find, in parallel at the outputs, the binary elements received serially at the inputs. The binary elements received at input E4 are the first available at the outputs, while those received at input El are the last. The various cells can be of the M type, as in the above-mentioned Patent Specification, but other technologies may be used to produce the device. The invention herein described is particularly practical when designed as an integrated circuit in which the number of cells can be greatly reduced. It could be used especially in PCM switching centers in which a large number of converters are found. WHAT WE CLAIM TS: -

1. An electrical serial/parallel conversion circuit having N inputs over each of

which may be received serially an N-bit code combination, and N outputs, in which each said N-bit code combination is so converted as to appear in parallel form on said N outputs, in which the circuit includes N shift registers each having N cells, in which each said shift register is connected to one of said N inputs so that it can receive and store an N-bit code combination arriving serially on its said input, in which the outputs of the last stages of the shift registers provide the N outputs of the conversion circuit, in which switching devices are provided each interconnecting two cells in different ones of said shift registers, the arrangement being such that with the N shift registers considered electrically as forming N columns each of N cells of a matrix the interconnections via said switches each extend diagonally with respect to said columns and said interconnections form parallel diagonals of the matrix, and in which when a set of N code combinations each consisting of N code bits have been received and stored in said shift registers, the operation of said switching devices followed by the application of clock pulses to the cells causes the combinations to appear successively in parallel form on said outputs.

2. A circuit according to claim 1, in which the circuit is formed as an integrated circuit, and in which the assembly considered as a matrix of N2 cells is folded back and around the cells of the diagonal so that the cells between which the diagonal interconnections are physicalls contiguous.

3. An electrical serial/parallel conversion circuit substantially as described with reference to the accompanying drawings.