GB1575254A

GB1575254A - Speed limiting apparatus for internal combustion engines

Info

Publication number: GB1575254A
Application number: GB8078A
Authority: GB
Original assignee: Robert Bosch GmbH
Current assignee: Robert Bosch GmbH
Priority date: 1977-02-25
Filing date: 1978-01-03
Publication date: 1980-09-17
Also published as: FR2381916A1; DE2708114A1; FR2381916B1; DE2708114C2

Description

(54) SPEED LIMITING APPARATUS FOR INTERNAL COMBUSTION ENGINES (71) We, ROBERT BOSCH GmbH, a German company of 50 Postfach, Stuttgart, Germany, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement:- The present invention relates to speed limiting apparatus for internal combustion engines.

Speed limiting apparatus has already been proposed in German OS 1 906 883 in which on reaching the limit speed the ignition is interrupted. Thus, the vehicle in which this speed limited combustion engine is incorporated, experiences a jerk which is unpleasant for the driver and can lead to dangerous situations, for example on wet roads. If the speed drops once again, then a sudden reinstatement of the ignition takes place and in so doing, an hysteresis occurs which results in an uneven operation of the engine. More over, this known circuit requires a special inductuve generator since the increase in the generator amplitude is brought into play for triggering the speed limiting apparatus. This circuit would not, for example, be controll able by a Hall-generator.

The present invention provides speed limiting apparatus for an internal combustion engine comprising at least one speed recog nition stage through which signals can be generated on reaching a limit speed for the suppression of control pulses for the ignition system of the internal combustion engine, and a frequency reducing stage connected to the speed recognition stage through which, on reaching the limit speed, ignition pulses are suppressed at regular intervals correspond ing to the frequency reduction ratio by means of a logic gating circuit.

Apparatus in accordance with a preferred embodiment of the invention has the advan tage that due to the freedom from hysteresis gentle and jerk-free speed limiting can take place. The speed limiting apparatus can be made to suit engines of different power by the choice of the frequency reduction ratio of the frequency reducing stage. With engines of low power, inhibiting every fourth ignition pulse, for example, can be sufficient for limiting, whilst with engines of higher power output, inhibiting two ignition sparks after each single ignition spark may be necessary.

In addition, it may be advantageous to set a further, higher speed limit beyond which all ignition sparks are inhibited. It is of particular advantage to construct the electronic circuit arrangement for recognition of the limit speed from an integrating stage in series with an edge discriminator, through which a triggering stage can be actuated, which re-sets periodically, and to connect the input to the said electronic circuit arrangement with the output from the frequency reducing stage.

This solution provides hysterisis-free and thus gentle and jerk-free speed limiting Further, a very accurate setting for the limit speed is possible.

Moreover, it is of special advantage tö provide a further speed recognition stage for a further high limit speed by means of which all ignition pulses are suppressed when the said further limit speed is exceeded. Above all, with high power engines, the blanking out of individual ignition sparks can no longer be sufficient, especially when the vehicle including the combustion engine is running downhill. Nevertheless, gentle and jerk-free limiting is achieved when at a first limit speed individual ignition pulses are first of all inhibited and then at a further higher limit speed all ignition impulses are inhibited.

In order that the present invention be more readily understood, embodiments thereof will now be described by way of example with reference to the accompanying drawings, in which :- Figure 1 is a block diagram of a first em bodiment; Figure 2 is a detailed arrangement of an integrating stage with an edge discriminator connected in series; Figure 3 is a signal diagram for explaining the method of operation of the first embodiment; Figure 4 is a block diagram of a second embodiment comprising two speed recogni- tion stages; and Figure 5 is a signal diagram for explaining the method of operation of the second embodiment.

In the embodiment illustrated in Figure 1, a terminal 10 is connected to the input to a frequency reducing stage 11 and to one input to an AND-gate 12. Moreover, this terminal 10 is connected in a manner not shown in any dtesired electronic ignition system for an internal combustion engine and indeed in the manner that speed proportional signals, preferably signals for controlling the electrical switch in the primary circuit of the ignition coil, are conducted to the terminal 10. If a frequency reduction ratio of 2:1 is desired, then the frequency reducing stage 11 can be constructed as a bistable triggering stage.

The output from the frequency reducing stage 11 is connected to the setting input to a bistable triggering stage 14 through a terminal 23 and an edge discriminator 13 for generating a signal on the occurrence of positive signal edges and a terminal 24. This triggering stage 14 can, for example, be made as an SR-flipflop or as a JK-flipflop. Moreover, the terminal 23 is connected, through the circuit of an integrating stage 15 connected in series, to a further edge discriminator 16 for generating a signal on the occurrence of positive signal edges having a terminal 17 which is connected to the resetting input of the triggering stage 4. The output from the triggering stage 14 is connected to a further input to the AND-gate 12. The output from the ANDgate 12 is connected to the control input to an electric switch 18 of an electronic ignition system 19.The switching path of the transistor 18 connected in series with the primary winding of an ignition coil 20, is connected between earth and a terminal 21 which is connected to the positive pole of a supply voltage source. The connecting point between the primary winding of the ignition coil 20 and the transistor 18 is likewise connected to earth through the secondary winding of said ignition coil and a sparking plug 22. If a number of sparking plugs are provided for a multi-cylinder internal combustion engine, then a high tension distributor can be included in known manner. In known manner, the transistor 18 can be formed as a Darlington-transistor and be provided with driving stages.

Figure 2 shows a preferred arrangement of the integrating stage 15 and of the edge discriminator 16 connected in series between the terminals 23 and 17. Moreover, the integrat ing stage consists of the series circuit of two resistors 30, 31 of which the latter is made adjustable for setting the limit speed, with a capacitor 32 the second terminal of which is connected to earth. The edge discriminator which is formed as a differentiating stage, consists of the series circuit of a capacitor 33 with a diode 34 and a resistor 35 which is connected between the terminal 17 and the connecting point between the two resistors 30, 31. Furthermore, a diode 36 is connected in parallel with the resistor 31. The connecting point of the resistor 31 to the capacitor 32 is connected through a resistor 37 to the connecting point between the capacitor 33 and the diode 34.

In the following, the signal diagram illustrated in Figure 3 serves to explain the method of operation of the circuit illustrated in Figures 1 and 2. The signal sequence A applied to the terminal 10 can, for example, be the output signal sequence from an ignition generator, for example a Hall-generator.

Moreover, the electric switch 18 in the primary current circuit of the ignition coil 20 must be closed during such a signal A for storing magnetic energy so that, at the end of such a signal A, an ignition spark is generated.

Such an ignition generator can, in known manner, be connected to an ignition timing point adjusting device of a mechanical or an electronic form and/or to a closing angle controlling device for the electrical switch 18.

In such cases, the terminal 10 must be suitably connected to these devices and indeed so that the corresponding control signal A for the electrical switch 18 is applied to the terminal 10.

A bistable switching stage can be set up by the frequency reduction stage 11 for generating the illustrated signal B at half frequency, so that the said signal B is applied to the terminal 23. Further frequency reduction ratios from such a frequency reduction stage can be selected within the scope of the invention. During a signal B, an integrating procedure takes place in the integrating stage 15, that is to say the capacitor 32 is charged through the resistors 30, 31. A voltage curve C is produced which occurs at the point illustrated in Figure 2. The level of the charging voltage is dependent on the speed. The capacity of the capacitor 33 is small with respect to the capacity of the capacitor 32 and does not influence its charging markedly.

Thus, the voltage C substantially follows the voltage at the capacitor 32. At the end of the signal B, the potential at the terminal 23 changes rapidly by - Uc in the negative direction. Up to this point, the capacitor 32 has been charged to the positive voltage Uk and the capacitor 33 also has substantially the said potential. The point at which the signal sequence C occurs is not completely followed by the rapid change in potential Uc but only by a rapid change Uc - Uk in the negative direction since, with a further drop in the potential below the said value the diode 36 becomes conductive and the capacitor 32 is discharged through the resistor 30.

The rapid change in potential Uc - Uk is transmitted by the capacitor 33 to the point to which the signal sequence C is applied. At this point, the voltage Uk is present before the change in potential. Immediately thereafter the potential is then Uk- (Uc-Uk) = 2Uk - Uc. This potential must be negative so that a resetting signal for the flip-flop 14 can be generated at the terminal 17 through the diode 34 and the resistor 35. It becomes negative when Uk is less than 1/2 Uc, thus at higher pulse sequence frequencies when there is only a short time interval available for charging the capacitor 32. Thus, from a fully determined speed, a signal appears at the terminal 17 with sufficient amplitude to set the flip-flop 14 into the other stable state.In the diagram, this signal is referenced E and only occurs in the second and third illustrated cycles since during the first illustrated cycle the speed is still too low.

Due to the edge discriminator 13, which can likewise be formed as a differentiating stage, a signal D is present at each rising edge of signal B. By means of this signal D, the flip-flop 14 is permanently set below the limit speed, that is to say a signal F is permanently present at its output. Only when the limit speed is exceeded does a signal E occur by which the flip-flop 14 is reset so as to be set once again during the next signal D. These relationships are likewise illustrated in the second and third cycles. Below the limit speed, thus with the flip-flop 14 permanently set, the signals A arrive unaltered through the AND-gate 12 to the transistor 18 and control the ignition system 19 accordingly. If the limit speed is reached and if the flip-flop 14 is reset thereby then every second signal A is blocked by the AND-gate 12.This means that every second ignition pulse fails to occur.

With another frequency reduction ratio, the sequence of conducting or blocking ignition signals A is varied in accordance with the reduction ratio.

Figure 4 shows a detailed diagram of a second embodiment the basic construction of which corresponds to the first embodiment.

In this case, the series circuit of an inverter 40 with a further speed recognition stage 41-48 is connected between the terminals 23 and 24, which recognition stage corresponds substantially to the first speed recognition stage 15, 16, that is to say likewise includes an integrating stage followed by an edge discriminator. Moreover, the output from the inverter 40 is connected to earth through the series circuit of a capacitor 41, a diode 42 and a resistor 43 made adjustable for setting the limit speed. The further series circuit of a diode 44 and a resistor 45 is connected in parallel with the diode 42 and the resistor 43.

The diodes 42, 44 are poled oppositely to one another. The point of connection between the diode 42 and the resistor 43 is connected through a capacitor 46 to the connecting point between the diode 44 and the resistor 45. Moreover, the connecting point between the diode 42 and the resistor 43 is connected to the terminal 24 through a further diode 47 and a resistor 48. Moreover, the two cathodes of the two diodes 42, 47 are connected to each other.

The method of operation of the detailed diagram of a second embodiment illustrated in Figure 4 will be explained in the following with the aid of the signal diagram illustrated in Figure 5. The signal sequences A, B, C, E correspond to the first embodiment in the case where the first speed threshold effective therein is reached or exceeded. Exceeding the speed threshold is represented in the signal sequence C when the speed is below the threshold value S1. Every time the speed falls below the threshold, a signal E is generated in the edge discriminator as already described. Through the inverter 40, the arrangement 41-48 operates during a pause in the signal sequence B. The method of operation of the integrating stage is reversed that is to say it is not integrated upwards but downwards.This occurs due to the fact that at the end of a signal B the capacitor 46 is charged by a positive edge at the output from the inverter 40 through the capacitor 41, the diode 42 and the resistor 45, so that the signal H makes a sudden positive voltage change.

Consequently, the capacitor 46 is charged through the variable resistor 43. At the start of a new sigual B, a sudden negative change in potential appears at the output from the inverter 40. This negative change in potential is transmitted through the diode 44 to the capacitor 46. At low speeds, the discharging of the capacitor 46 is already well advanced at this point with the result that, due to the said sudden change in potential, the potential falls below the threshold S2. This is represented in the illustrated signal sequence H for the first two edges. At a higher speed, the capacitor 46 is discharged to a lesser extent at the instant of the change in potential so that the potential can no longer fall below the threshold S2 due to the sudden change in potential.The negative voltage peak is transmitted to the terminal 24 through the diode 47 and the resistor 48 and sets the flip-flop 14 provided the amplitude of the said negative voltage peak is sufficient. This must be the case when the potential has fallen below the threshold S2. At a higher speed, as is represented by the third sudden change in potential of the signal sequence H, the voltage no longer falls below the threshold S2 and the flip-tlop 14 is not set. The AND-gate 12 is then blocked for all signals A. Only when the potential falls below the said higher speed threshold, is every second ignition pulse reinstated and when the potential falls below the first speed threshold, every ignition signal becomes effective once again. A smooth speed limiting even with combustion engines of high power, is guaranteed by the said steplike blanking off of the ignition.

Instead of the ignition system 19 being controlled by the speed limiting apparatus through a logic switching device 12 in the form of an AND-gate, the said ignition system can also be blocked directly through another logic circuit arrangement in which the base potential of the transistor 18 or of a corresponding transistor, is brought down to a lower potential. In this case, the speed limiting apparatus must deliver complementary signals thus, not signals for making the transistor 18 current conductive, but for blocking it. In this case, the signals illustrated in dotted lines must be generated instead of the control signals G since during the latter the base potential of the transistor 18 must be lowered.

The principle of suppressing ignition pulses at regular intervals by a frequency reduction stage, can also be achieved by another arrangement of the said frequency reduction stage 11.

Moreover, within the scope of the invention, the triggering stage 14 for the first embodiment can be made monostable instead of bistable. In this case, the edge discriminator 13 can be omitted. In such a case, the dwell time must be so arranged that it includes one Qr possibly even a plurality of signals A.

The timing members included in the speed stages 15, 16 or 41-48 can, for example also be replaced by monostable triggering stages, monostable multivibrators and other forms of timing members without altering the principle of the invention. A comparison between the output signals from such timing members and the signals A or B, leads to a corresponding establishment of the speed or recognition of the limit speed. A corresponding logic gating must be provided in each case.

WHAT WE CLAIM IS:- 1. Speed limiting apparatus for an internal combustion engine comprising at least one speed recognition stage through which signals can be generated on reaching a limit speed for the suppression of control pulses for the ignition system of the internal combustion engine, and a frequency reducing stage connected to the speed recognition stage through which, on reaching the limit speed, ignition pulses are suppressed at regular intervals corresponding to the frequency reduction ratio by means of a logic gating circuit.

2. Apparatus according to claim 1; wherein the frequency reducing stage comprises a triggering stage, arranged to periodically switch back, and actuable by the speed recognition stage and wherein the input to the said speed recognition stage is connected to the output from the frequency reduction stage.

3. Apparatus according to claim 1 or 2, wherein the frequency reducing stage comprises a bistable triggering stage arranged to suppress every second ignition pulse.

4. Apparatus according to claim 2 or 3 and comprising a further speed recognition stage for a further higher limit speed, whereby all ignition pulses are suppressed on exceeding the said further limit speed.

5. Apparatus according to claim 4, wherein both speed recognition stages are arranged to act on a bistable switching stage which, on exceeding the first limit speed, is displaced into its second stable switching condition and if the second higher limit speed is not reached, is displaced into its first stable condition and wherein the inputs to the speed recognition stages are connected to the output from the frequency reduction stage.

6. Apparatus according to any one of the preceding claims, wherein at least one of the speed recognition stages comprises an integrating stage comprising a series connected subsequent edge discriminator.

7. Apparatus according to any one of the preceding claims, wherein the logic gating circuit includes a gating stage through which signals for controlling the ignition system can be inhibited in accordance with the output signal from the triggering stage.

8. Speed limiting apparatus for an internal combustion engine comprising a speed recognition stage through which, on attaining a limit speed, signals can be generated for suppression of the control pulses for the ignition system of the engine, and a triggering stage which is periodically switched back, and is actuable by the speed recognition stage, one output from the triggering stage being connected to a gating stage through which signals from the ignition system can be inhibited in accordance with the output signal from the triggering stage.

9. Speed limiting apparatus substantially as hereinbefore described with reference to the accompanying drawings.

**WARNING** end of DESC field may overlap start of CLMS **.

Claims

**WARNING** start of CLMS field may overlap end of DESC **.

threshold, is every second ignition pulse reinstated and when the potential falls below the first speed threshold, every ignition signal becomes effective once again. A smooth speed limiting even with combustion engines of high power, is guaranteed by the said steplike blanking off of the ignition.

Instead of the ignition system 19 being controlled by the speed limiting apparatus through a logic switching device 12 in the form of an AND-gate, the said ignition system can also be blocked directly through another logic circuit arrangement in which the base potential of the transistor 18 or of a corresponding transistor, is brought down to a lower potential. In this case, the speed limiting apparatus must deliver complementary signals thus, not signals for making the transistor 18 current conductive, but for blocking it. In this case, the signals illustrated in dotted lines must be generated instead of the control signals G since during the latter the base potential of the transistor 18 must be lowered.

The principle of suppressing ignition pulses at regular intervals by a frequency reduction stage, can also be achieved by another arrangement of the said frequency reduction stage 11.

Moreover, within the scope of the invention, the triggering stage 14 for the first embodiment can be made monostable instead of bistable. In this case, the edge discriminator

13 can be omitted. In such a case, the dwell time must be so arranged that it includes one Qr possibly even a plurality of signals A.

The timing members included in the speed stages 15, 16 or 41-48 can, for example also be replaced by monostable triggering stages, monostable multivibrators and other forms of timing members without altering the principle of the invention. A comparison between the output signals from such timing members and the signals A or B, leads to a corresponding establishment of the speed or recognition of the limit speed. A corresponding logic gating must be provided in each case.

WHAT WE CLAIM IS:- 1. Speed limiting apparatus for an internal combustion engine comprising at least one speed recognition stage through which signals can be generated on reaching a limit speed for the suppression of control pulses for the ignition system of the internal combustion engine, and a frequency reducing stage connected to the speed recognition stage through which, on reaching the limit speed, ignition pulses are suppressed at regular intervals corresponding to the frequency reduction ratio by means of a logic gating circuit.
2. Apparatus according to claim 1; wherein the frequency reducing stage comprises a triggering stage, arranged to periodically switch back, and actuable by the speed recognition stage and wherein the input to the said speed recognition stage is connected to the output from the frequency reduction stage.
3. Apparatus according to claim 1 or 2, wherein the frequency reducing stage comprises a bistable triggering stage arranged to suppress every second ignition pulse.
4. Apparatus according to claim 2 or 3 and comprising a further speed recognition stage for a further higher limit speed, whereby all ignition pulses are suppressed on exceeding the said further limit speed.
5. Apparatus according to claim 4, wherein both speed recognition stages are arranged to act on a bistable switching stage which, on exceeding the first limit speed, is displaced into its second stable switching condition and if the second higher limit speed is not reached, is displaced into its first stable condition and wherein the inputs to the speed recognition stages are connected to the output from the frequency reduction stage.
6. Apparatus according to any one of the preceding claims, wherein at least one of the speed recognition stages comprises an integrating stage comprising a series connected subsequent edge discriminator.
7. Apparatus according to any one of the preceding claims, wherein the logic gating circuit includes a gating stage through which signals for controlling the ignition system can be inhibited in accordance with the output signal from the triggering stage.
8. Speed limiting apparatus for an internal combustion engine comprising a speed recognition stage through which, on attaining a limit speed, signals can be generated for suppression of the control pulses for the ignition system of the engine, and a triggering stage which is periodically switched back, and is actuable by the speed recognition stage, one output from the triggering stage being connected to a gating stage through which signals from the ignition system can be inhibited in accordance with the output signal from the triggering stage.
9. Speed limiting apparatus substantially as hereinbefore described with reference to the accompanying drawings.