GB1574173A - Character generating circuit - Google Patents

Description

PATENT SPECIFICATION

( 11) ( 21) Application No 8698/77 ( 22) Filed 2 March 1977 ( 19) ( 31) Convention Application No 663 427 ( 32) Filed 3 March 1976 in ( 33) United States of America (US) ( 44) Complete Specification published 3 Sept 1980 ( 51) INT CL 3 G 09 G 1/16 ( 52) Index at acceptance H 4 T 4 R BSX ( 72) Inventors MAURITZ LELAND GRANBERG, DAVID GORDON HANSON and ROBERT LAURI RAJALA ( 54) CHARACTER GENERATING CIRCUIT ( 71) We, SPERRY RAND CORPORATION, a Corporation organised under the laws of the State of Delaware, United States of America, of 1290 Avenue of the Americas, New York, New York 10019, United States of America, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement: The present invention relates to a character generating circuit for use with a television raster scan circuit and cathode ray tube to produce a visual display terminal (VDT).

Heretofore, VD Ts were well known and had been produced employing stripped down commercially available television chassis.

Commercial entertainment television chassis employed for VD Ts suffer several deficiencies If less than all the scan lines are employed to complete a frame or picture, the characters displayed on the CRT are not well defined and/or suffered from noticeable decay of brightness, or flicker.

When all of the scan lines are employed to produce a dot-matrix character and the dots are tightly spaced, the character generator and the associated circuitry become large and expensive When a standard commercial television raster scan circuit is modified to increase the frequency or the number of scan lines, the cost of the CRT controls is greatly increased Whenever a more dense dot matrix character generator is employed with a greater number of raster scan lines, the dot-matrix character generator and associated circuitry is made more expensive.

It is an object of the present invention to provide a circuit suitable for use in combination with a commercial television display to provide a simple, relatively cheap VDT of good resolution and intensity, and substantially flicker-free.

The present invention therefore provides a circuit for use with cathode ray tube display apparatus having interlaced scanning for displaying characters composed of a matrix of dots, the circuit comprising a memory, a dot character generator, temporary storage means arranged to store four patterns of dots generated by the dot character generator and representing one row of dots of the character, the next succeeding row, and the said row and the said succeeding row each displaced by one dot position, and a logic circuit connected to the temporary storage means and arranged to supply to the cathode ray tube display apparatus on each line of a first scan the dot pattern generated by the dot character generator and on each line of a second, interlaced, scan a dot pattern comprising a dot interpolated between each pair of vertically and each pair of diagonally adjacent dots of the first scan pattern.

Optionally the invention further provides means for detecting a lower-case character and for re-aligning it in the display relative to upper-case characters.

The invention will be further described by way of example, with reference to the accompanying drawings, in which Figure 1 is an illustration of a 5 X 7 dot-matrix display for an upper case "A" generated according to a preferred embodiment of the present invention; Figure 2 is an illustration of a 5 X 7 dot-matrix display for a lower case "y" generated according to a preferred embodiment of the present invention; Figures 3 a and 3 b are a logic block diagram of the preferred embodiment timing circuit; Figures 4 a and 4 b are a logic block diagram of a preferred embodiment circuit employed to modify the output of a standard dot-matrix character generator; and Figures 5 a and 5 b are a logic block diagram of a modification of the circuit of 1 574 173 1,574,173 Figures 4 a and 4 b showing a circuit for generating a modified dot-matrix pattern employing a single dot-matrix generator.

Figure 1 is a schematic illustration of an upper-case "A" There are seven horizontal rows and five vertical columns numbered to show the relative position of the dark squares or dots which are generated by a dot-matrix character generator conforming to the ASCII code For purposes of this description, the columns are numbered in the X axis direction and the rows are numbered in Y axis direction; thus, the uppermost dark square is located at dot-matrix coordinate address X 3, Y 1 and the two hollow squares directly below are located at dot-matrix coordinate addresses X 2 5, YL.5 and X 2 5, Y 3 5 respectively The dark squares represent the character which would be generated by a 5 X 7 dot-matrix character generator and the hollow squares represent the enhancement which will be displayed on the CRT as a result of the additional dots generated by logical circuitry employing the output of the 5 x 7 dot-matrix character generator Figure lillustrates that the output of a 5 x 7 dot-matrix can be expanded to a 9 x 13 dot-matrix pattern, thus increasing 'the definition and resolution as well as the brightness of the character presented.

Figure 2 is a schematic illustration of a lower-case "y" showing in dark squares the manner in which the character would be stored and generated by a dot-matrix character generator if no modification was made in the logical circuit system The coordinate locations of the squares or dots are numbered in the same manner as the squares and dots in Figure 1 so that the dark square at the left and top of character is located at coordinate address XI, Y 1 As will be explained in greater detail hereinafter, the hollow squares show where dots will be inserted by the circuits of the invention The preferred embodiment logic system to be described hereinafter further modifies the location of characters such as y, g, j, p and q by moving the character downward relative to the bottom line (i e row 7) of the character being presented on the CRT display In effect the character y shown in Figure 2 will be presented on the CRT display so that row 5 will be displaced until it is level with the bottom line or row 7 of the upper-case characters being displayed.

In the preferred embodiment of the present invention the dot-matrix characters are five columns wide and have a separation of one column between characters There is provision for eighty characters, requiring 480 dot columns along the X axis By providing dot time separation of approximately nanoseconds, the 480 dot columns can easily be displaced on the CRT within the horizontal scan time of Sfty-two microseconds and still allow for approximately fourteen microseconds horizontal retrace time The preferred embodiment characters to be described are seven rows deep and 70 have a row separation of three even scan lines between characters There is provision for twenty-five lines of full characters requiring 250 dot rows Entertainment television raster scan circuits are made to provide 262 75 horizontal scan lines on the first or even scan, thus it will be understood that the 250 dot rows or horizontal even scan lines can easily be displaced on the face of the CRT.

Refer now to Figures 3 a and 3 b, which 80 show the timing circuits for synchronizing the logic ciruits and'the raster scan circuits of an entertainment type television set employed in the preferred embodiment Timing means 10 has an input line 11 from a 85 crystal oscillator providing a 9 7344 M Hz signal This frequency of oscillation occurs each 102 72847 nanoseconds and by amplifying and shaping the oscillation pulses, they may be used to synchronize the counters 90 and registers in the timing means 10 Line 11 is shown connected to a delay 12 which comprises a plurality of amplifiers and waveshaping elements The output of delay 12 on line 13 is connected to the set or up 95 count side of binary counter 15 When binary counter 15 is cleared, it is set to 000 at the output of lines 16, 17 and 18 When the count reaches five or binary 101, the next pulse applied at input 14 will change 100 the output binary count to 110 on lines 18, 17 and 16 respectively, thus, lines 17 and 18 are high and line 16 is low when the binary counter changes from a binary five to a binary six The low signal on line 16 105 is inverted in an inverter 21 and applied as a high signal to NAND gate 22 along with the high signals on lines 17 and 18 producing a low output or clear signal on line 23 which is inverted at inverter 24 and applied 110 to the clear side of binary counter 15 at input 25 The binary inputs, which last for approximately 103 nanoseconds, are applied on lines 16, 17 and 18 to phase generator 20 creating an output on one of the phase 1 115 ( 01) to phase 7 (o 7) lines) It will be understood that a binary 000 starts when the binary counter 15 is cleared and lasts until the next timing pulse is applied 103 nanoseconds later at input 14 of binary counter 120 Each successive input pulse at input 14 steps the phase generator to the next phase output line until the count attempts to step the phase generator to the phase 7 ( 07) count output The same input to phase 125 generator 20 that would ordinarily generate a phase 7 output is gated in NAND gate 22 and applied as a clear signal pulse at terminal 25 of binary counter 15 to clear or reset the counter, thus, it is understood 130 that the phase 7 output has no duration of 103 nanoseconds similar to the phase 1 to phase 6 outputs.

The output of NAND gate 22 on line 23 is also applied to the set or count-up input 26 of character counter 27 Modulo sixteen binary counter 27 is cleared to start at the binary count of 000 and counts up to binary fifteen, then produces a carry pulse when it resets to zero on the count of sixteen Line 28 represents the binary one character or one output Line 29 represents the binary two or character two output Line 31 represents the character four or binary four output and line 32 represents the character eight or binary eight output These lines present a high output at their binary count.

After the binary count of fifteen, the next count pulse arriving at input 26 produces a carry-out on line 33 which is applied to the set or input terminal 34 of character counter 35 Character counter 35 in its clear condition has a binary 000 output The first carry-in at terminal 34 causes line 36, representative of character sixteen, to go high as the lowest order binary one is set in character counter 35 The second carry-in causes the binary two line 37 which is representative of character thirty-two to go high and the fourth carry-in causes line 38 which is representative of character sixty-four, to go high It will be understood that character counters 27 and 35 act in combination and are thus capable of counting 128 characters.

Line 39 is connected to the character sixteen count Line 41 is connected to the character sixty-four count and line 42 is connected to the character thirty-two count The low signal on line 41 is applied to inverter 43 and produces a high output on line 44 to NAND gate 45 when character sixty-four is not high Column two produces a high output on line 29 which is applied to the input of NAND gate 45 and produces a low output on line 46 to the set side of intensity control flip-flop 47 At the character count of two the intensity control output at terminal Q goes high on line 48 This output may be applied through logic to the intensity grid of the cathode to produce the desired intensity of the electron beam of the cathode ray tube The character two output on line 29 is applied as an input to NAND gate 49.

The character sixteen output on line 39 and the character sixty-four output on line 41 are also applied to the input of the NAND gate 49 The logic highs on lines 40 and 51 are stabilizing inputs and do not change.

When all three character counts representative of a character count of eighty-two are present at the input of NAND gate 49, a low clear signal is produced on line 52 which is applied to the clear side of intensity control flip-flop 47, thus it will be understood that the condition on output line 48 of intensity control flip-flop 47 is high at character two and goes low at character eighty-two.

Line 32 from character eight, line 42 from character thirty-two and line 41 from 70 character sixty-four are connected as inputs to NAND gate 53 When all three inputs are present indicating a character 104 count condition, a low output from NAND gate 53 is produced on line 54 at the input of inverter 75 The high output on line 56, indicative of character 104, is applied as a clear signal to input terminal 57 of character counter 27 and to input terminal 58 of character counter 35 80 Phase counter 20 is continuously running and is producing an output on the phase count lines The phase count is synchronized with the presentation of the X columns of each individual character The phase one 85 count occurs during the space between characters and is employed to lead the registers supplying the intensity control logic.

The first character to be generated at the start of a line of characters represents the 90 start of character count of two When' character counter 35 reaches the count of eighty-two, no more characters will be produced because intensity control logic is turned off The output on line 48 may also 95be used to trigger or start the refresh and horizontal synchronization of the electron beam At the character count of 104, the electron beam has retraced and is at character position 0 ready to start another 100 horizontal trace At this time the character counters 27 and 35 are reset to zero and the next row of the character may be scanned starting with a character count of two and ending with the start of character count 105 eighty-two.

The low active signal on line 61 from NAND gate 53 is applied to the set or count-up side 62 of row counter 63, which provides a binary output on lines 64, 65, 66 110 and 67 representative of the binary counts of one, two four and eight The high output on line 65 from row two, a high output from row eight on line 67 and a low output on line 64 inverted in inverter 68 and applied 115 to the input of NAND gate 69 provides a low output on the count of ten on line 71.

The low output on line 71 is inverted in inverter 72 providing a high output on line 73 indicative of a row ten condition The 120 high signal on line 73 is applied to the clear input 75 of row counter 63 to return the row counter to 000 It will be understood that each time the electron beam scans the horizontal line and the count reaches 104, the 125 row counter will receive a set input, and each time the row counter reaches ten representative of the rows of the individual character, and three spaces therebetween, the row counter will be reset The low active 130 1,574,173 1,574,173 condition on line 71, representing a row ten count, is applied to the set or count-up input terminal 76 of character row counter 77 Character row counter 77 is a binary counter and provides a one, two, four and eight binary output on lines 78, 79, 81, 82 representative of rows After the count of fifteen, when character row counter 77 counts to zero, a carry is produced at carry terminal 83 on line 84 which is connected to the set or count-up side 85 of character row counter 86 which produces an output at the Q terminal on line 87 at the count of sixteen The high active row count conditions from rows two, eight and sixteen on lines 79, 82 and 87 are applied as inputs to NAND gate 88 generating a low active signal on line 89 at the character row count of twenty-six The low active signal on line 89 is inverted in inverter 91 and provides a high active signal at the character row count of twenty-six on line 92 The high active signal on line 92, representative of the start of the horizontal scan of the line 260 (start of character row twenty-six) is applied to the clear input terminal 93 and 94 of character row counters 77 and 86 respectively At the start of a line count of 260, the character row counters will be reset to zero and start to repeat the character line count and character row count.

Lines 82 and 87 indicative of row eight and row sixteen, are applied to NAND gate to produce a row twenty-four output.

Line 73 is applied to NAND gate 95 to hold the row count of twenty-four until the last or tenth line count of row twenty-four Line 52 is applied to NAND gate 95 to hold the line count of 250 (twenty-four rows plus ten lines) to the end of the eighty-second column count before starting the vertical retrace signal on line 96.

Line 96 is applied to the input logic card 97 to produce a reshaped output signal on line 98 which is applied to the clear side 99 of flip-flop 100 The clear side input signal produces a low or reset vertical sync signal on line 101 which is employed to start the vertical retrace Line 101 is also connected as an input to flip-flop 102.

The Q terminal of flip-flop 102 is connected to the data input terminal D via line 104 to provide alternate positive and negative data inputs to the flip-flop 102 The output on line 103 from terminal Q indicates whether the odd or even set of 260 lines of raster scanning are in progress.

The row two count on line 79 from row counter 77 is applied to inverter 105 The lbw input on line 106 is applied to the set side 107 of flip-flop 100 The row count on ine 106 occurs two rows after the active input on line 98 so that the set side input prod ices the clear signal every other row and continues to hold the flip-flop in the clear or set state Flip-flop 100 has its active input 98 connected to the clear side and the inactive input 106 applied to the set side to produce the necessary low active signal at 70 the Q terminal The low active signal on line 98 is also applied to the clear input side 108 of flip-flop 109 to produce a low active signal starting at row twenty-four time on line 110 The low active signal on line 75 89, occurring at row twenty-six time is applied to the set side 111 of flip-flop 109 to reset or clear the Q terminal output on line 110 The vertical retrace time which occurs between row twenty-four and row 80 twenty-six time on line 110 is employed to shut off the cathode ray tube intensity grid or the cathode to prevent a bright retrace line on the tube.

The basic timing signal of the crystal 85 oscillator (not shown) has been amplified and shaped on line 11 and is applied to amplifier 112 to provide a low active clock shift register signal on line 113 The pulses appearing on line 113 are slightly ahead of 90 the basic timing signals being applied to the binary counter 15 due to the delay in delay 12 The basic timing signals on line 113 occur every basic pulse time and may be employed to clock the shift registers to be 95 explained hereinafter.

Refer now to Figures 4 a and 4 b showing the character dot-matrix generation system.

The first three row counts, Rl, R 2 and R 4 of row counter 63 are applied on input lines 100 64, 65 and 66 to a multiplexer 115 to produce the identical row counts on output lines 116, 117 and 118 The row count on R 1, R 2 and R 4 is capable of defining the first through the seventh row of a dot matrix 105 character in a 5 X 7 dot-matrix This row address is supplied to row input 119 of dotmatrix character generator 128.

Memory system 114 defines one of the 128 characters stored in the character gen 110 erator 128 on address output lines 120 to 126 at input terminals 127 The address presented on lines 120 to 126 is loaded into dot-matrix character generator 128 with a phase two pulse generated at phase generator 115 When the row address input is at row input terminals 119 and the character address input is at input terminals 127, the dot-matrix generator 128 produces a parallel output of five signals on lines 127 to 131 120 indicative of dots to be generated to define a row of the character being addressed.

The dot-matrix signals indicative of a row of the character are applied to the DEFG and H input terminals 133 of shift register 125 The phase one pulse on line 136, which follows the phase two pulse employed to load memory 114, is applied to the load terminal of shift register 135 causing the dotmatrix signal pattern on lines 127 to 131 130 1,574,173 to set into shift register 135 The phase one load pulse on line 136 is inverted in inverter 137 and applied via line 138 to the inhibit terminals of the shift registers so that the shift registers cannot be loaded except during the phase one time following the previous loading of the memory 114 during a phase two time.

After shift register 135 is loaded with the dot-matrix pattern to be displayed on the cathode ray tube, a clock shift register signal on line 113 is applied every 103 nanoseconds to shift the dots of the dot-matrix pattern to the left, causing each of the dots stored in the shift register to be presented at the output terminal 139 The dot signal on line 139 is applied directly to multiplexer 141.

During the first, or odd scan, line 103 will select the direct through connection and the dot-matrix signal is connected to line 142 and applied to the intensity grid of the CRT causing the dots being shifted out of shift register 135 to be displayed sequentially 103 nanoseconds apart.

For purposes of this invention, the character generator 128 may be used to generate the dot signals for the next character which follows in the same horizontal row by maintaining the same row address at input 119 and changing the character address at input 127 at each phase two time The series of dots on lines 127 to 131 are set in register at the next following phase one time permitting the clock pulses on line 113 to shift the dot signals out The phase one load time occurs during the time representative of the space between characters, thus, shift register 135 is loaded after being read out and before the next character is presented.

After the electron beam has completed the first or even scan of all of the characters to be presented on the full screen, the electron beam retraces vertically back to the top of the screen and starts the scan of the even lines The even scan signal on line 103 to multiplexer 141 will select the path to only permit the even scan to be passed through multiplexer 141 to the control line 142.

During the second or odd scan, the address of each character to be displayed is sequentially supplied from memory 114 to dot-matrix character generators 128 and 143.

The row counter 63 supplied the row of the characters to be scanned on lines 64 to 66.

The same row address that was supplied during the first or odd scan is provided to the input terminals 119 of dot-matrix character generator 128 via lines 116 to 118 The row address on lines 116 to 118 is also supplied to decoder 144 which adds one row count to the row address being supplied by row counter 63 This row count address plus one added is supplied to the row count input terminals 140 of dot-matrix character generator 143.

The dot-matrix pattern for a single romr of a single character is transferred to shift register 135 as was performed previously with the odd scan The dot-matrix pattern for the next following row of the same 70 single character is simultaneously transferred to shift register 144 via dot matrix linees 145 to 149.

As an example of the dot-matrix signals representative of rows which are stored in 75 reigsters 135 and 144, reference may be made to Figure 1 When row four ( 4) of the dot-matrix for the character A is stored in register 135, row five ( 5) of the character is stored in register 144 A direct comparison 80 of the dots being shifted out of these registers is being sequentially made at NAND) gate 151 When two dots such as X 1, Y 4 and XI, Y 5 occur simultaneously on lines 139 and 152, a single dot signal is produced 85 on line 153 The signal passes via OR gate 154, inverter 155, line 156, multiplexer 141 to line 142 which produces the single signal for inserting dot X 1, Y 4 5 during the real time scanning of the even scan lines in 90 similar manner, when the column 5 dots are compared, the dot X 5, Y 4 5 will be inserted.

The row five ( 5) pattern of dots on lines to 148 will also be set into shift register 95 157 at input terminals 158 The row five ( 5) dot-matrix pattern referred to above is shifted to the left one column so that the column one ( 1) dot is lost At the same time NAND gate 151 is making a real time comn 100 parison of the vertically disposed dots, NAND gate 159 will be making a comparison of diagonally disposed dots As an example, the Xl, Y 4 dot is being compared in NAND gate 159 with the X 2, Y 5 dot so 105 as to produce the signal for inserting the dot shown at X 1 5, Y 4 5 The signal indicative of the row four ( 4) dots is presented on line 139 and the signals indicative of the dots being presented on row five ( 5) 110 shifted to the left one column position, is being presented on line 161 and the comparison output is generated from NAND gate 159 on line 162 The comparison signal passes through OR gate 163 to delay 165 115 Delay 165 is designed to delay the presentation of dot X 1 5, Y 4 5 by one half of 103 nanoseconds so that it will appear on the visual display diagonally between dots XI, Y 4 and X 2, Y 5 The real time signal from 120 delay 165 on line 166 passes-through OR gate 154, inverter 155 to line 156 and through multiplexer 141 to intensity control line 142.

In similar manner, the dot pattern on lines 125 127 to 130 is presented at input terminal 167 of shift register 168 in a manner which shifts row four ( 4) to the left one column position The left shifted output on line 169 is compared in NAND gate 171 with the row 130 1,574,173 five ( 5) input being presented on line 152.

When the dot shown at X 5, Y 4 is compared with the dot shown at X 4, Y 5, and when comparison is made, the output on line 172 is passed through OR gate 163 to line 142 in the manner previously explained The delayed output will cause the dot shown at X 4.5, Y 4 5 to be inserted in the dot position shown in Figure 1.

The generation of the characters shown in Figures 1 and 2 require two raster scan passes which have hereinbefore been referred to as the even scan or first raster scan and the odd scan or the second raster scan The second scan is interlaced between the rows of the first scan During the first scan, dotmatrix character generator 128 produces a standard ASCII 5 X 7 dot-matrix pattern such as that shown by the dark dots in the 5 x 7 matrix of Figure 1 During the even scan, the dot-matrix character generators 128 and 143 both produce standard ASCII 5 X 7 dot-matrix patterns; however, the dotmatrix patterns are processed in the logic gates 151, 159 and 171 to produce the dots, shown as hollow dots, between the dark dots in Figure 1 The addition of the inserted hollow dots on the second scan effectively produces a 9 x 13 dot matrix employing only a 5 X 7 dot-matrix character generator.

Since the dots being generated are the result of turning on the cathode or controlling the intensity grid of the CRT, the dots are easily elongated in the horizontal or X direction It has not been found necessary to insert dots between horizontally adjacent dots of the 5 X 7 matrix Should it be desirable to insert dots between horizontally adjacent dots of the 5 X 7 matrix, the output from register 135 can be compared with the output from register 168 in AND gate 173 The comparison signal on line 174 from AND gate 173 may be delayed one-half of one phase time in delay 175 before being buffered in OR gate 176 and applied to the multiplexer 141 via line 139.

To prevent insertion of dots between characters, the sixth column is left blank A phase six signal is applied on line 177 to delay 178, and the output therefrom on line 179 is employed as an inhibit signal applied to the logic gates 159, 171 and 173.

Refer now to Figure 2 and Figure 4 b.

Figure 2 shows in dark dots an ASCII 5 X 7 dot matrix pattern for a lower case "y" The numbered rows 1 to 7 are scanned on the first scan producing the dark dots. The interlaced unnumbered rows Y 1 5, Y 2 5

etc are scanned on the second scan and the logic circuits comprising gates 151, 159 and 171 vroduce the inserted hollow dots such as those shown at Xl, Y 35; X 1 5, X 4 5 and X 4 5, Y 4 5 in the manner described hereinbefore.

It will be noted that the "lower case y" if displayed in the time sequence in which it is generated by the dot-matrix generators 128 and 143 will appear to be two full rows of the 5 x 7 matrix above the line on which it should appear The address from 70 memory 114 on lines 120 to 126 is applied to decoder 181 and every lower case letter such as g, j, p, q and y having a descender, and other characters such as, or; and subnumbers may be detected to provide a 75 select-out signal on line 182 The select-out signal on line 182 is applied to multiplexer so that the row address on lines 183 to are selected as the active input lines instead of lines 64 to 66 The row count 80 on lines 64 to 66 is applied to decoder 186 and a count of two rows is subtracted from the normal row count The effect of subtracting a count of two from the row count being applied to the matrix character 85 generators 128 and 143 is to cause row one ( 1) of Figure 2 to be presented during the row three ( 3) scan time and to cause row seven ( 7) to be presented during the row nine ( 9) scan time, thus effectively lowering 90 the lower case y two rows of the 5 X 7 dot-matrix pattern spacing without modification of the logic circuits or the character generation circuits.

It will be understood that the 5 X 7 95 dot-matrix pattern is being enhanced to an effective 9 x 13 dot-matrix pattern There is one vertical column separating the characters and there are three horizontal rows separating each character, thus, the lower 100 case y shown in Figure 2 may be lowered two rows and still have one row separation between characters.

Refer now to Figures 5 a and 5 b showing a modification of Figures 4 a and 4 b Dot 105 matrix character generators are much more expensive than other electronic hardware such as shift registers In the preferred embodiment a 5 x 7 dot matrix has been described which cost about twenty times 110 more than a shift register When dot-matrix generators having greater density are employed, the cost ratio will increase exponentially The modification shown in Figures Sa and Sb describes a system which 115 will employ a single dot-matrix character generator to achieve the same result as that described hereinbefore with two character generators.

Memory 114, character generator 128, 120 shift registers 135, 144, 157, 168 and the logic circuits comprising NAND gates 151.

159 and 171 etc employ the same numbers and are structurally identical to those shown in Figures 4 a and 4 b The modified mode 125 of operation to be employed in the Figures a and 5 b generates the address of the character to the character generator on lines to 126 as previously described; however, the row counts supplied on lines 116 130 6 _ 1,574,173 to 188 applied to character generator 128 have been modified to provide two sets of dot-matrix row patterns on output lines 127 to 131 during each six phase times (one character row time).

At phase two time the address in memory 114 is supplied via lines 120 to 126 to address terminals 127 of character generator 128 and remain present until the next following phase two when the next character address is loaded into the dot-matrix character generator 128.

At phase three time a signal is applied on line 190 to the clear side 191 of flip-flop 189 to produce a low active output on line 192 Multiplexer 193 selects the row count input lines 194 to 196 from decoder 1441.

As explained hereinbefore decoder 144 ' will add one row count to the input row count being produced on lines 64 to 66 The row count on lines 194 to 196 will indicate the next row down of the character which is being addressed by row counter 63 The next row dot-matrix pattern is presented on lines 127 to 131 at phase three time and is loaded into dot-matrix bit register 197 at phase four by the load signal on line 198.

At phase five time, a signal on line 199 sets flip-flop 189 producing a select signal on line 192 which causes multiplexer 193 to select input lines 1161 to 118 ' The row count signal on lines 1161 to, 1181 are connected via lines 116 to 118 to terminals 119 and are the same row count signals which are being generated on lines 64 to 66 by row counter 63 At the next following phase one time, the phase one load signal on line 136 will load shift registers 135, 144, 157 and 168 It will be understood that the real time row dot-matrix pattern in dot-matrix character generator 128 will be loaded in shift register 135 and the same dot-matrix pattern shifted left one column will be loaded in shift register 168 In similar manner the next row dot-matrix pattern which was stored in bit register 197 during phase four time will be transferred to and stored in shift register 144 The same next row dot-matrix pattern shifted one column to the left will be stored in shift register 157.

The dot-matrix patterns stored in shift registers 135, 144, 157 and 158 are shifted out by the clock pulses on line 113 and processed in the logic circuits during real time to produce output signals on line 142.

Line 142 is connected to the intensity grid to produce the pattern of 9 x 13 matrix dots and inserted dots shown in Figures 1 and 2 and described hereinbefore with regard to Figures 4 a and 4 b.

The modification explained with regard to Figures 5 a and 5 b reduces the amount of electronic circuitry and electronic hardware, thus, reduces the cost of the visual display system and at the same time increases the reliability and precision of the display.

Any dot-matrix character generator of the type described with regard to dot-matrix character generator 128 may be increased from an X X Y dot-matrix character generator to a ( 2 X-1) X ( 2 Y-1) dot-matrix character generator with a negligible increase in cost of hardware and electronic circuitry.

Claims (4)

WHAT WE CLAIM IS: 75

1 A circuit for use with cathode ray tube display apparatus having interlaced scanning for displaying characters composed of a matrix of dots, the circuit comprising a memory, a dot character generator, term 80 proary storage means arranged to store four patterns of dots generated by the dot character generator and representing one row of dots of the character, the next succeeding row, and the said row and the said succeeding 85 row each displaced by one dot position, and a logic ciruit connected to the temporary storage means and arranged to supply to the cathode ray tube display apparatus on each line of a first scan the dot pattern generated 90 by the dot character generator and on each line of a second, interlaced, scan a dot pattern comprising a dot interpolated between each pair of vertically, and each pair of diagonally adjacent dots of the first scan 95 pattern.

2 A circuit according to claim 1 in which the temporary storage means comprises four shift registers, each arranged to store a different one of the said dot patterns 100

3 A circuit according to claim 1 or claim 2 including a row counter arranged to hold a count of a row of dots generated by the dot character generator, and a decoder arranged to derive therefrom a 105 count of the next succeeding row.

4 A circuit according to claim 3 including a detector for detecting the occurrence of a lower-case character with a descender, and a decoder responsive to 110 the detector for reducing the row count so as to re-align the character relative to the other characters.

A circuit for use with cathode ray tube display apparatus having interlaced 115 scanning for displaying characters composed of a matrix of dots, organised and arranged to operate substantially as shown in and as herein described with reference to, Figures 1, 2, 3 a and 3 b in combination with either 120 Figures 4 a and 4 b or Figures 5 a and 5 b of the accompanying drawings.

For the Applicants:

P A MICHAELS, Chartered Patent Agent.

Printed for Her Majesty's Stationery Office by Burgess & Son (Abingdon), Ltd -1980.

Published at The Patent Office, 25 Southampton Buildings, London, WC 2 A l AY, from which copies may be obtained.