GB1574104A - Data processing apparatus - Google Patents

Description

(54) DATA PROCESSING APPARATUS (71) We, INTERNATIONAL BUSINESS MACHINES CORPORATION, a Corporation organized and existing under the laws of the State of New York in the United States of America, of Armonk, New York 10504, United States of America do hereby declare the invention for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement: The present invention relates to data processing apparatus.

The present invention provides data processing apparatus including a data storage subsystem and a data handling subsystem (i.e. processing system, transmission subsystem, further storage subsystem) within which a recording and accessing protocol obtains, means to generate and record a pair of data set identifiers at the beginning and end of the writing of a data set into the storage subsystem, such pair of identifiers being unique to the data set and independent of the protocol, and means to cause an error indication or absence of a validation indication (collectively error signal generating) when an apparent data set is read from the storage subsystem which is not bounded by a pair of data set identifiers which match.

Data storage for automatic data processing machines takes diverse forms with corresponding diverse data storage capacities. Strong trend has continued to increase the storage capacity of data storage apparatus. In particular, data storage apparatus under complete control of the automatic data processing machines has many economic advantages for the user in that human intervention is reduced to a minimum, thereby enhancing performance of a data processing system. Even with such substantial error-free automatic data storage apparatus. the requirements for data integrity and data correctness (absence of undetected data errors) continues to be the utmost requirement of a data storage apparatus.

A relatively high capacity data storage apparatus is the International Business Machines Corporation. Armonk, New York designed and built. Model 3850 Mass Storage System (MSS). This fully automatic, on-line data storage apparatus has a single address field with two levels of data storage. A first or staging level includes direct access storage devices (DASD) employing disk storage devices. Such DASD enable rapid access to data records and data sets and therefore find a high popularity in data processing applications. Unfortunately. DASD is substantially more expensive than the flexible magnetic tape storage systems. The latter which are essentially sequential in nature as opposed to random access, are characterized by long access time which is detrimental to overall data processing efficiencies. Further, the data capacity of the DASD is not as large as is often desired in data processing application.

The IBM 3850 MSS/(IBM being a registered Trade Mark) has combined the advantages of tape storage with DASD in that a lower level of the storage uses a magnetic tape in a data cartridge which is automatically fetched from a storage wall, inserted into a data recording device (DRD). then signals are exchanged between the data cartridge and the DASD under fully automatic control such that the using data processing system only sees the disk storage apparatus while having the capacity of tape storage.

In the fully automatic operations of such an MSS. signals are shuttled back and forth between the two levels at relatively high data rates. The storage of signals on the magnetic tape in the lower or destaged level uses the same information-bearing characters as used on DASD. Areas of the magnetic tape are allocated on a so-called cylinder basis for recording. A cylinder in a DASD device is one track on each of a plurality of recording surfaces. For example, if a DASD has nine disks with a 'comb head" carrying 18 transducers for respectively exchanging signals with the 18 surfaces of the nine disks; a cylinder consists of all 17 data tracks on the 17 surfaces. The eighteenth surface is a servo track for controlling the positioning of the transducers in the comb head with respect to the recording surfaces on all nine disks. Accordingly, it is seen that the data format is consistent throughout the various levels of data storage for enhancing efficiency.

The transfer of signals from the destaged or lower level to the upper or staging level is called a staging signal exchange. A staging operation moves the data to DASD for making it immediately available to the using data processing system. The signal transfer from staging or upper level to the destaged or lower tape level is called a destaging signal exchange. In either of the signal exchanges, it is important not only that the data being transferred is correct as detected and corrected by error detection and correction systems, but that also the integrity of the data be maintained over and above data correction. That is, the staging and destaging operations should not be interrupted such that partial data sets are transferred from one level to another resulting in a portion of a cylinder having desired data and the remaining portion having undesired data. When a situation does occur this is called loss of data integrity. A computer program operating with such data can result in substantial errors in the event of such a loss of data integrity. While loss of data integrity is extremely rare, the mere fact that it could happen in an undetected manner poses a serious challenge to the entire data processing system for ensuring data integrity and the resultant computations that are heavily relied upon as being impeccably accurate in diverse applications. On rare occasion a destaging operation being interrupted could result in a loss of data integrity, while powerful error detection and correction systems correct any resultant data errors, such correction does not necessarily indicate any loss of data set integrity.

Arrangements according to the present invention are thought to provide an effective way of ensuring data integrity in signal transfer operations.

The present invention will be described further by way of example with reference to embodiments thereof as illustrated in the accompanying drawings in which: FIGURE 1 is a simplified block diagram illustrating the operation of one form of apparatus of the invention in a first mode, together with an illustration of the relationship of data integrity signals and recorded data signals.

FIGURE 2 is a diagrammatic showing of a record member having valid data indicated by data integrity signals plus invalid data indicated by data integrity signals which show lack of data integrity.

FIGURE 3 diagrammatically shows a record member having an area with a loss of data integrity indicated by two data integrity signals.

FIGURE 4 is a block diagram of a preferred embodiment of the present invention together with a preferred form of data recording on a magnetic tape.

FIGURE 4A is a block diagram of a programmable computer suitable for use in the apparatus of FIGURE 4.

FIGURE 5 is a simplified computer program flow chart at the subroutine level showing the recording operation controlled by the computer of FIGURE 4.

FIGURE 6 is a simplified computer program flow chart at the subroutine level for illustrating a read operation for verifying data integrity of signals recorded by the computer in accordance with the FIGURE 5 illustrated flow chart.

FIGURE 7 is an instruction level flow chart illustrating operation of subroutine QT235.

FIGURE 8 is an instruction level flow chart illustrating a portion of subroutine QB455 which increments the count constituting the data integrity signals.

FIGURE 9 is a simplified subroutine level flow chart showing a second best mode of practicing the present invention and which is a preferred mode of practicing the invention with respect to certain aspects of the FIGURE 5 illustrated flow chart.

FIGURE 10 is an instruction level flow chart for subroutine QT150 as it pertains to the present invention.

FIGURES 11 and 12 are simplified instruction level flow charts concerned with recording data integrity signals.

FIGURE 13 is a portion of an instruction level flow chart for subroutine Owt 165 concerned with the read back of previously recorded data integrity signals.

FIGURE 14 is an instruction level flow chart of a portion of subroutine QT380 as it pertains to practicing the present invention during read back of signals and verifying the data integrity of such readback signals.

FIGURE 15 is an instruction level flow chart of a selected portion of QT434 for handling data integrity signals that have been read back in error.

FIGURE 16 is an instruction level flow chart of a portion of QT421 subroutine for verifying data integrity after a last recorded data integrity signal could not be read back successfully.

Referring now to the drawings, like numerals indicate like parts and structural features in the various diagrams. The present invention is most advantageously employed in signal transfers using a magnetic recording medium such as magnetic tape (no limitation thereto intended) particularly in a mass storage system having multiple levels of storage for ensuring data integrity in a fully automatic operation. As best seen in FIGURES 1,2 and 3 a magnetic tape 10 has recorded data signals together with data integrity signals identified as K1, K2, K3 and K21. The first recorded data integrity signals K1 bracket a first recorded data set DATA 1. When successfully recorded the K1 at 11 is identical to the K1 at 12. During readback of the signals from tape 10, K1 at 11 is first read back, followed by reading the data signal DATA 1, and finally reading K1 at 12. If the two K1's 11 and 12 are equal then the data set represented by DATA 1 has high integrity. It is assumed, of course, that data detection and correction systems ensure the lack of data errors which may be caused by the recording and readback operations or flaws in the magnetic tape 10.

The beginning of record BOR is signified by the K1 at 11, while the end of record EOR is signified by the K1 at 12. Similarly, tape 10 has other data sets bracketed by the data integrity signals K2 and K3. The size of the data sets is immaterial to the practice of the invention, it being remembered that data detection and correction systems will take care of the more probable data errors induced by the recording/readback operations.

Record medium 10 may have its recorded data sets updated from time to time during normal data processing operations. In some situations the size of the data set may expand or may be substantially reduced. Let's assume that DATA 1 has been manipulated by a data processing system such as utilization device 13 of FIGURE 1. As a result, a new data set DATA 21 has been generated by utilization device 13. Utilization device 13 then commands a recorder, later described, to record the new data set DATA 21 in the same area of tape 10 as DATA 1 was previously recorded. Then as seen in FIGURE 2 the BOR receives a first K21 data integrity signal at 14, followed by the DATA 21 data set and then by the second K21 data integrity signal at 15. OLD DATA 1 if not erased will remain, followed by the K1 at 12.

With such updating there are two end of records EOR1 signifying the original end of record from DATA 1, and EOR2 signifying the new updated end of record. While for security purposes it is desired that all of OLD DATA 1 be erased along with its K1 at 12 this may not always occur and in some systems may be omitted for purposes of performance. Accordingly, when the FIGURE 2 illustrated format is read back the K21 at 14 and 15 will signify the data integrity of the newly recorded DATA 21. It is to be understood that when DATA 21 is to be read back by the computer or utilization device 13 it will know the extent of DATA 21 and therefore quit reading at EOR2. Alternatively, at EOR2 a gap, i.e., erased portion of tape 10, may be imposed for signifying end of record. Other symbols may be used in addition to erasure. However. if for some reason the entire records from K21 at 14 through K1 at 12 are read then the lack of data integrity of the signals transferred from tape 10 will be indicated by the difference between K 1 and K2 1. Suitable error recovery procedures beyond the scope of this description are then employed to reread the record for trying to recover DATA 21 successfully from tape 10.

It may occur that the recording operation may be unintentionally interrupted. This interruption may be undetected for one reason or another. In that event the interrupted recording at 16 results in a data record on tape 10 having a BOR with K21 at 14, followed by a portion of NEW DATA 21. the interruption and remainder of OLD DATA 1. K 1 at 12 is still on tape 10. When the recorded signals of FIGURE 3 are read back, the count K21 at 14 will not compare with K1 at 12 nor with the old data located at 17 where the utilization device 13 would expect a second K21 count to be recorded. Since it was not recorded, lack of coincidence between the signals read back at 17 and the signals K21 at 14 indicate lack of data integrity to an interrupted recording.

The above showing of record member 10. FIGURES 1. 2 and 3. are diagrammatic and are intended to include disk files. magnetic core memories, semiconductive memories, optical memories, and any other record medium suitable for receiving signals. Later. with respect to FIGURE 4, a preferred form of the invention will be shown and described in detail.

Returning to FIGURE 1. utilization device 13 exchanges signals with tape 10 via a recorder employing a set of recording circuits 20, readback circuits 21. with the actual tape recorder 22 hereinafter referred to as DRD. The data integrity signals K1 and so forth, are generated by a destage counter 23 which in a preferred form has this function performed by computer programming.

Utilization device 13 at the onset of a desired recording operation will send a first signal over line 25 for enabling AND circuit 26 to pass the count contained in destage counter 23 through OR circuit 27. thence recording circuits 20 to be modulated for recording on tape 10.

Simultaneously with the signal on line 25 device 13 supplies a control signal over line 30 for actuating destage counter 23 to shift its count contents through AND circuit 26 and OR circuit 27 for recording as K1 at 11. Since the count field from counter 23 is a known size, utilization device upon counting the number of bits supplied by counter 23 will begin supplying data signals of DATA 1 over line 31 through OR circuit 27 to recording circuits 20.

Upon the secession of recording DATA 1, the utilization device supplies a last signal over line 32 enabling AND circuit 33 to pass the signals from destage counter 23 as initiated by the signal on line 30 to be recorded as K1 at 12. When the line 30 signal is removed destage counter 23 will increment to the next count. In this regard, destage counter 23 can be a three byte binary counter, a linear feedback shift register counter, a decimal counter, or any other form of sequential count generator.

As described above, destage counter 23 is altered or incremented each recording operation, thereby providing a unique count for each recording operation. That mode of operation is a first best mode. A second best mode envisions utilization device 13 either periodically or aperiodically but at least more often than recording operations supplying an increment signal over line 35 for altering the count of destage counter 23. That mode of operation is a second best mode wherein the successive data integrity signals recorded on a tape 10 are not successive counts, whether encrytped or not. Further, the count K1 at 11 and the count K1 at 12 can be different by a predetermined count or encryption algorithm. It is preferred that the counts at 11 and 12 be identical for simplicity purposes.

Verification of data integrity of DATA 1 is achieved in the readback circuit check registers 42, 47 that receive the signals from readback circuits 21. A read operation is commanded by utilization device 13 by a read signal supplied over line 40 to readback circuits 21 and DRD 22. First K1 at 11 is read and supplied through AND circuit 41 to a first register 42. It is also supplied to utilization device 13. An enabling signal over line 43 from readback circuits 21 enable AND circuit 41 to pass only the K1 count portion, i.e., the first three bytes of data read following BOR. Then readback circuits 21 having counted out three data bytes remove the enabling signal from line 43 disabling AND 41 such that the DATA 1 signals will go only to utilization device 13.

Upon completion of reading DATA 1, the K1 count at 12 is read and supplied to AND circuit 46 to a second register 47. The signal on line 48 is active for enabling AND circuit 46 for three bytes during the K1 period until EOR is reached. At this time registers 42 and 47 both should contain K1. These registers 42, 47 output the K1 count signal to a compare circuit 50 for searching for identity of K1. K2. Compare circuit 50 is actuated by readback circuits 21 detecting EOR as indicated by a signal supplied over line 51. Upon a successful compare. compare circuit 50 supplies data integrity OK signal over line 52 to utilization device 13. In the alternative. upon lack of compare, compare circuit 50 supplies a signal over line 53 for capturing the content of registers 42, 47 in an error log register 54. The error log register then can be read out by utilization device 13 for analysis and evaluation of the data integrity as signified by line 55.

A preferred form of the invention is shown in FIGURE 4 wherein the invention is practiced in the environment of a mass storage system employing an upper storage level consisting of a plurality of DASD and a lower storage level 61 consisting of a tape library type of storage device. Lower level 61 includes a mass storage facility MSF which consists of a storage wall of data cartridges which are automatically transportable to and from the storage locations in the storage wall and any one of a large plurality of DRD 22. The symbol DRD 22 in FIGURE 4 is intended to include the recording circuits 20 and the readback circuits 21 of FIGURE 1. Instead of the hardware generation circuits and detection circuits of FIGURE 1 a computer 62 performs the functions described with respect to FIGURE 1 via a computer program. Level 61 is completed by a mass storage control MSC which controls the operation of MSF and DRD's 22. as well as coordinating operation of the two levels 60 and 61 in a known manner.

Computer 62 includes the data processing circuits shown in FIGURE 4A. as well as a memory 63 which includes registers 23A for containing a destage count corresponding to destage counter 23 of FIGURE 1. Additionally. it is desired to identify the signal path over which the signals being destaged from DASD 60 to lower level 61 have passed. Accordingly. registers 23A additionally contain a portion for identifying the DRD 22 which effected the recording on the magnetic tape and is indicated in the memory by unit number. Similarly. in FIGURE 1 when those circuits are applied to a multiple path storage system such as a mass storage system. the destage counter 23 will include a register which is nonalterable for containing the address of recording circuits 20. readback circuits 21. and DRD 22: i.e.. identify the signal path through which the destaging operation or recording operation occurred.

Computer 62 also includes counter registers 42A for containing a first count and unit identification as read from tape 10 as will become apparent. Further. a second register 47A contains the second count corresponding to register 47 of FIGURE 1. Additionally. an RO count which is a third copy of the data integrity signals is stored in a register 64. Under ideal conditions. during a readback operation, the counts contained in registers 42A. 47A and 64 are all identical. A flag bit position 65 in memory 63 contains the result of the compare of the count fields 42A. 47A and 64 for indicating to the connected hosts or computers 66 of the data integrity of the signals being transferred from lower level 61 to DASD level 60.

Accordingly, when the host 66, including primary host 67, requests the data transfer from DASD 60 to their own main memory (not shown) the integrity of the data signal is known.

Additionally, memory 63 of computer 62 contains a set of programs in a set of registers 68 for operating a portion of the mass storage system as will become more apparent.

A preferred form of tape format used in connection with practicing the present invention in a mass storage system is illustrated in the lower part of FIGURE 4 as being written by one of the DRD's 22. DRD 22 is preferred to be a rotating head recorder wherein the record tracks are in the form of diagonal stripes across tape 10. As mentioned earlier, the stripes or record tracks are grouped into cylinders corresponding to DASD 60 format. Since such cylinders of data as recorded on tape 10 are not truly cylinders they are termed virtual cylinder 70 when recorded on tape 10. Each virtual cylinder is separated by a gap 71 for ease of identification and enabling updating in place. Accordingly, a first virtual cylinder 72 is separated from the virtual cylinder 70 by gap 71. Similarly, gap 73 separates virtual cylinder 70 from an adjacent virtual cylinder 74. In general, the recording operation on tape 10 as seen in FIGURE 4 proceeds from the left to the right. That is, first stripe 75 of virtual cylinder 70 is first recorded and will contain the data integrity signals together with the address of the DRD 22 performing the recording operation. A second stripe 76 is then recorded which contains the DATA 1 signal. Finally, the last stripe 77 contains the data signal to be recorded also includes a copy of the data integrity signal which is herein identified as K10. However, the entire virtual cylinder 70 is very seldom completely filled with data signals. This is to allow expansion and contraction of the data set during normal data processing operations. Accordingly, after recording the last stripe 77 including the data integrity signal K10, the DRD 22 performing the recording operation will effectively erase the remaining stripes down through the last stripe of the virtual cylinder 70 identified herein as RO. In RO the data integrity signal K10 is recorded as a backup data integrity signal to the last stripe 77 data integrity signal K10. That is, if last stripe 77 cannot be read and therefore data integrity cannot be verified with the first K10 of first stripe 75; then the backup K10 and RO can be used. In this instance even though stripe 77 could not be read the erase stripes in area 78 disposed between stripe 77 and RO stripe can be verified to contain erased signal patterns which can be a DC erase or all zero modulation signals.

As seen in FIGURE 4 the virtual cylinder stripe 72 has its data integrity indicated by data integrity signals K65 whereas virtual cylinder 74 has its data integrity verified by data integrity signals K14. This means that virtual cylinder 70 was most probably recorded first with the adjacent virtual cylinders 72,74 being recorded thereafter, as indicated by the higher numbered data integrity signals. In the event of an error in recording either of the virtual cylinders 72, 74 such as gaps 71. 73 being violated and thereby overriding a portion of the virtual cylinder 70, the data integrity signals K10 would detect such an error. It should be noted that since the stripes are recorded as entities by DRD's 22 that the error detection and correction circuits would not detect such inadvertent overriding and resultant destruction of desired recorded data. Only with practicing the present invention as shown with the particular mass storage system can such destruction of data integrity be accurately detected.

The address of the DRD doing the recording will identify such inadvertent errors and thereby assist maintenance personnel in diagnosing difficulties in the automatic operations of such a large data storage facility. It should be noted that the computer 62 can be switched between DASD 60 and DRD's 22 to stage and destage data to and from DASD 60 via one of a plurality of computers 62. Therefore, the address recorded on tape 10 will not only include the DRD doing the actual recording. but also which computer 62 handled the destaging operation. Therefore the count field in combination with the address field provides a unique pointer for assisting and diagnosing errors resulting in loss of data integrity as well as an unusual high data error rate. for example.

Both MSC and computers 62 are microprogrammable processors with computers 62 additionally having special circuits for exchanging data signals between a host 66, 67 and DASD 60. or between DASD spindles 60 and DRD's 22. Since a portion of the invention is initiated under microprogram control. the two microprocessors are described in diagrammatic form. FIGURE 4A shows one computer 62 (all are identical). Intercommunication between MSC and computer 62 is in accordance with U.S. patent 3,400.372. That is, primary host 67 and other hosts 66 communicate with MSC wherein MSC is a control unit of the I/O descriptive portion of 3.400.372. Similarly. computers 62 are also control units as described in that patent. Additionally. MSC acts as a host computer for the computers 62; i.e.. computers 62 are a "control unit" to MSC as that term is used in 3.400.372.

For convenience. computers 62 have a four-channel interface. i.e.. each computer 62 can connect up to four hosts; MSC appears as one of the hosts but always on the same interface connection. If the four connections are labeled A, B. C, and D. host MSC is connected to interface A. while primary host 67 and some of the other hosts 66 are connected to the other three interfaces. Primary host 67 needs not be connected to all computers 62, while MSC has to be connected to all computers 62.

The calculator portion of computers 62 and MSC are identical. Such calculators are also shown in FIGURE 4 of U.S. patent 3,716,837 and in the DASD Director Model 3830 produced by International Business Machines Corporation, Armonk, New York. For a better understanding of the micro-programming involved with the present invention, the calculator problems and their relationship to the computers 62 are set forth in sufficient detail in flow chart form to facilitate a ready understanding of what is achieved. A better understanding can be achieved by a reading of P. F. DeJohn et al, supra, as well as a description of the instructions for computers 62. Computers 62 of this application correspond to the storage director 16 of P. F. DeJohn et al, supra.

In computers 62 the program store 81 supplies the instruction word to an instruction holding register 85, the outputs of which drive decode circuit 86 to supply a set of micro orders to all the units. Such decoder is constructed as is well known in the arts and serves to sequence operation of all of the units. A portion of the instruction word is fed back to IAR in the W and X registers for program branching and accessing the next instruction word from program store 81, as will become apparent.

Computing circuits 80 operations all center about ALU 82. It has two inputs, the A register and the B register. These two registers receive signals from funnels or assembly circuits AASM and BASM, respectively. The assembly circuits merely take the signals from a plurality of signal busses and gate same to the A and B registers under control of decode 86.

Two of the input busses to the AASM and BASM are the A bus which transfers signals from a set of microprogram registers 87 to the A register, and the B bus which transfers signals to the B register from selected ones of the microprogram registers 87 and from the instruction word holding register 85. An important aspect of microprogramming computer circuits 80 is the assignment and construction of the microprogram registers is shown in the table below.

Microprogram Registers 87 General Purpose Registers GA GB GC GD TA TB TC TD NA NB NC ND MA MB MC MD Special Purpose Registers SA. SB, SC. SD: Inputs = Control Store, D Bus. External Outputs = Control Store, B Bus, External BR (Branch Register): Input = D Bus Output = B Bus. Control Store Address Decode ST (Status Register): Input = D Bus, Condition Sense Output = B Bus. External Not only must the assignment of the microprogram registers 87 to the general classes be understood. but also the specific application of the registers 87 to execution of the microprogram sequences must be known. The utilization of the microprogram registers 87 is set forth in the table below. The term "control unit" refers to the circuits associated with decode 86 which includes an oscillator (not shown) and sets of registers (not shown) for controlling the sequencing of the microprogram. all in accordance wit

From Register Position Meaning To CTL-1 ND0 CTL-1 Seiected Alert 1 Control Unit (Sp Op 13 and ND1 CTL-1 Select Active TD1=1) ND2 CTL-1 Sync in ND3 Indes ND4 CTL-1 Noimat End ND5 CTL-1 Check End ND6 CTL-1 Tag Vand ND7 Not Used C@@@@@ @@@ TA0 CTL 1 Bus Out 0 TA1 CTL 1 Bus Out 1 Tag Moddreis 10 DASD TA2 CTL-1 Bus Out 2 Contro@e@ TA3 CTL-1 Bus Out 3 TA4 CTL-1 Bus Out 4 TA5 CTL 1 Bus Out 5 TA6 CTL-1 Bus Out 6 TA7 CTL-1 Bus Out 7 Contr@@. @@@@ TB0 CTL-1 Select Hold D@@@ TB1 CTL 1 Tag Gate C@@@@@@@ TB2 CTL-1 Error Alert Gate CT@ 1 TB3 Allow Busy Channel A/B Channel TB4 Enable CU End Channel D Channel TB5 Enable CU End Channel Channel TB6 Enable CU End Channel B/Disable CU End Cha@@@ - Channel TB7 Anow NA Register Load Channel Cuntrol Und TCC 00 Not Used Channel Interface and 01 Channel Read Control TC1 10 Channel Write Control 11 Freere Transter TC2 Tast Gyts Request TC3 Operation In Channel A/B TC4 Addiess In Channel A/B TC5 States In Channel A/B TC6 00 Not Data Hesponse Mode Ch@@ and 01 CTL 1 W@@e 10 CTL 1 Read - No Load 5 Register TC7 11 CTL 1 Read - Load 5 Register @@@@@ @@@ TD@ CTL 1 Tag E t 0 Contr@ e@s TD1 CTL-1 Control @@@es to ND Regester TD2 Not Used TD3 Not Used TD4 CTL 1 Tag B@@ 4 TD5 CTL-1 Tag B@@ 5 TD6 CTL 1 Tag B@@ 6 TD7 CTL 1 Tag B@t 7

From Register Position Meaning To Control Unit MA0 CTL-1 Bus In Read Data Controt Storage (SA. SB. SC.

MA1 SD Regs@ (See MC Register) MA2 MA3 MA4 MA5 MA6 MA7 DASD Controner MA0 CTL-@ Bus in Read Data Control Unst (Translerred to MA1 MD Register on Read MA2 Operatronsl MA3 MA5 MA6 MA7 Control Unit MB0 Byte Counter High CTL-1 MB1 MB2 MB3 MB4 MB5 MB6 MB7 Control Und MC0 Byte Counter Low CTL-1 MC1 MC2 MC3 MC4 MC5 MC6 MC7 Control Und MD0 Bus In Bit 0 Selected Channel MD1 Bus In Bit 1 MD2 Bus In Bit 2 MD3 Bus In Bit 3 MD4 Bus In Bit 4 MD5 Bus In Bit 5 MD6 Bus In Bit 6 MD7 Bus In Bit 7 Conbrol @@@@ ME0 ADT Seleor Ho@d CTL1 ADT ME1 Not Used ME2 ADT Error Aiert Gate ME3 Not Used ME4 Not Used ME5 ADT/DASD Mode ME6 00 ADT Reset and 01 ADT W@@te ME7 10 ADT Read 11 ADT Dra@no@@@@ Re@@

From Register Position Meaning To Control Und ME0 Special Operation 02 Gates the conte@ts of the ME Register into AMR Register ME1 the AMR for addressing control storage when in mieroprogram ME2 extended format 1 mode ME3 Special Operation 49 gates a hard wired machine type code into Control Unit ME4 the ME Register for diagnostic microprogram usage ME5 ME6 ME7 Selected Channel NA0 Bus Out Bit 0 Control Unit (Not Special NA1 Bus Out Brt 1 Operation 14) NA2 Bus Out Brt 2 NA3 Bus Out Brt 3 NA4 Bus Out Brt 4 [Buffer A or B] NA5 Bus Out Brt 5 NA6 Bus Out Brt 6 NA7 Bus Out Brt 7 Channel NA0 Buffer Panty Check Control Unit (Special Operation Channel NA1 Interface Check Channel A 14) Channel NA2 Interface Check Channel B Channel NA3 Channel Transfer Check CTL-1 NA4 CTL-1 Check CTL-1 NA5 CTL-1 Load S register Check CTL-1 NA6 Compare Assist Check NA7 Not Used CTL-1 ADT NB0 ADT Controller Check Control Unit (Special Operation NB1 ADT Select Actrve Check 42) NB2 CTL-1 ADT Bus In Panty Check NB3 ADT Unexpected End Check NB4 ADT Byte Counter Check NB5 CTL-1 ADT Bus Out Pa@@ty Check NB6 ADT Syn@ In Check NB7 Any ADT Group E Error CTL 1 ADT/DBS NB0 ADT Address Register Check Control Und (Special Operation NB1 DBS Write Bus Check 43) NB2 CCU/DBS Read Bus Check NB3 Set Atert 3 NB4 ADT Transter Check NB5 DBS Audress Bus Check NB6 ADT DBS Read Bus Check NB7 ADT Recycle CTL-1 ND0 CTL 1 Controller Check Control Und Special Operation ND1 CTL-1 Select Active Check 13 and TDL=01 ND2 CTL 1 Buller Parity Check ND3 CTL-1 Unexpected End Check ND4 CTL 1 Tag Bus Check ND5 CTL 1 Bus Out Patity Check ND6 CTL 1 Transter Check ND7 Any ADT Check

From Register Position Meaning To Control Und TE0 Unsuppressible Request In Channel D Channel Interface TE1 Suppressible Request In Channel D TE2 Unsuppressible Request In Channel C TE3 Suppressible Request In Channel C TE4 CTL-1 to CTL-1 ADT Swstch TES Not Used TE6 Allow Disable Channel C TE7 Allow Disable Channel D Control Unit [Not TG0 Unsuppressible Request In Channe@ B Channel Interface MPL Op @ TG1 Suppressible Request In Channel B TG2 Unsuppressible Request In Channel A TG3 Suppressible Request In Channel A TG4 Block Switch to Channel D TG5 Block Switch to Channel C TG6 Block Switch to Channel B TG7 Block Switch to Channel A Control Unit [MPL TG0 Engage MPL File Head MPL File Op@ TG1 Move Head In 1 Track TG2 Move Head Out 1 Track TG3 MPL File Slart Read Dec He@ Special Operation Dec Hex Special Operation 0 0 Microprogram Stop 17 1B Unused 1 1 Check Stop 28 1C Oragnostic Selective Reset 2 2 Set Entended Format 1 Mode and Load AMR from 29 1D Unused ME Register 3 3 Reset Check 2 [Except ADT] 30 1E Propagate Select Out 4 4 Set Diagnostic W@te 31 1F Unused 5 5 Reset Dragnostic Wote 32 20 Switch to DBS 6 6 Load ACR Inline 33 21 Switch to Control Store 7 7 Inline @@LXEO Branch 34 22 Enable ADT Check 2 8 8 Stop MPL File 35 23 Load ADT Address into NB Register 9 9 Start MPL File 36 24 Load ADT Address Hign from ME Register 10 A MPL File Load SD Register 37 25 Load ADT Address Low from ME Register 11 B Reset Ex@ended Format 1 Mode 38 26 toad ADT Byte Count High from ME Register 12 C Un@sed 39 27 Load ADT Byte Count Low from ME Register 13 D Load ND Register - Check 2 10 28 Load AS Registers from DBS 14 E Load NA Register - Check 2 41 29 Set ADT Control B@@s 15 F Set CTL @ B @s in Par@y Ent@ 42 2A Load Grosp 1 ADT Check 2s into NB Register 16 10 Cate CTL 1 Response End 43 2B Load Grosp 2 ADT Chack 2s into NB Register 17 11 CTL 1 Recycle load B@@@er from TA Reo sie@ 44 2C Un@sed 18 12 Ga@@ A@etnate B@anch 45 2D toad DBS from AS Registers 19 13 Set @@@@e Active Branch 46 2E Diaqnoshe Syn@ in 20 14 Reset @@@e A@bve Br@och 47 2F Reset ADT Check 2 E@@@@@ 21 15 Unfree@e Channet Sw@tch 48 30 Unsed 22 16 A@@ow Disable Channe@ A 49 31 Load Machine Tupe In ME Register 23 17 Allow Disable Channes B 50 32 Set Stager Destage Mode 24 18 Load Compare Assist tarches into MB Reg@siet 51 33 Reset Stage/ Destage Mode 25 19 Unosed 52 34 Gate EAR Read Bus to NC Register 26 1A Fresze Channel Switch 53 35 Set altow 12 14K Expanded Control Storage 54 36 Reset anow B 12K and 12 14K Expanded Control Storage 55 37 Set anow B-12K Exparded Control Storage Another factor is the accessing of the program store, particularly through the address register IAR. In the table below the term "latched" means it is held over from the previous instruction word; i.e., not changed. The program store has a two-byte instruction address register IAR having the bit assignments set forth in the table below, Program Store Address Register Inputs Byte O (Type Instruction D-3 Latched, Bit 0=0) Type Bits Input A O 0 1-3 Latched 4-7 Latched/CV B 0 0 1-4 Latched 5-7 CV C O 0 1-3 CW 4-7 CV Byte 1: A-D 8-11 CX F-3 12 CH 13 CL 14, 15 0 E All CB The data address register, which accesses the control registers, is set forth below.

Data Address Register (Control Registers) Type Bits Input large 0-4 0 5-7 ML 8-15 CB 2a-2b 0 0 1-4 MH 5-7 ML 8-15 CB 3 0-4 0 5-7 ML 8-11 NH 12-15 NL As set forth above. the microprogram registers 87 supply signals to ALU 82 and also receive signals from ALU 82 via D bus. Registers 87 also supply signals to SERDES 90 and to channel circuits 91 for exchanging signals with hosts 66, 67 and MSC. Hence, the data loop in computer circuits 80 includes ALU 82, D bus, microprogram registers 87, A and B busses, and the A and B registers. It should be noted that the inputs from program store 81 to ALU 82 is via the B bus. All communications in the computer circuits flow through ALU 82. For example. D bus also goes to the IG register 92 which then supplies signals to channel circuits 91 which. in turn. are connected to one of the hosts 19. Channel circuits 91 are those channel circuits defined as a control unit in U.S. Patent 3,400,372, and are those used in connection with the type 370 computer manufactured by International Business Machines Corporation.

Armonk, New York. Further examination of FIGURE 4A, along with the charts above, clearly show the data flow of computer circuits 80, it being understood that this arrangement is essentially the same as that shown and used by International Business Machines Corporation in the 3830 Model II Director Unit.

Each computer 62 also has what is termed a "staging adapter." That is, a data buffer system (DBS) which connects DRD's 22 to the DASD controller 95 of DASD 60. B-ecause tape units operate at different rates than do disk storage spindles 96 of DASD 60, a buffer memory.

92 of the count-up/count-down type is interposed between the SERDES 90 which is at connection to DASD 60 units, as previously explained, and buffer memory 92. Buffer memory 92 includes independent control circuits known in the buffering art for automatically - transferring signals to the DRD 22 and for receiving signals with DASD 60 via SERDES 90.

All these operations are independent of computer circuits 80. It should be noted that computer circuits 80 are involved in transfer of signals from DASD 60 to the host computer 66, 67 or MSC via the SERDES 90 as was practiced in the International Business Machines Corporation manufactured 3830 Model II Director Unit. Buffer memory 42 has two parts which are alternately used. A first part receives signals from DRD 22, while the second part simultaneously supplies signals to SERDES 90 (staging). When the transfers are completed the operations are switched such that the first part is then supplying signals to SERDES 90; while the second part receives signals from DRD 22 for providing an uninterrupted exchange of data signals. The same operation is provided in moving data from the DASD 60 to DRD 22 (destage). Since such buffer memory operations are well known, they are not further described.

The action of any of the computers 62 for recording data signals on a tape 10 in accordance with the present invention is shown in abbreviated form in FIGURE 5. Omitted are the usual operations of a computer 62, such as those units in an IBM 3850 MSS, for recording signals but which are not pertinent to an understanding of the present invention. Such omitted subroutines are indicated in FIGURE 5 at 100. Before starting a recording operation a computer 62 responds to the subroutine QT235 of FIGURE 7 to clear a portion of memory 63 dedicated to maintaining a count area, such as registers 42A, 47A 64 and 65. Then in accordance with a first best mode the destage count in registers 23A is incremented by QB455. In a second best mode construction of the invention as later described with respect to FIGURE 9 the destage count (MVD--move data) is incremented asynchronously with respect to recording operations. In any event, the first stripe is set up by the computer responding to subroutine QT150. Then the first stripe is written via QT401. The intermediate stripes are recorded as indicated in FIGURE 4 and not described because such operations are well known. The last stripe, such as stripe 77, is written via subroutine QT360. The intermediate stripes 78 are then erased to all zeros with the last stripe in the virtual cylinder 70 being written via QT401 which writes the RO stripe including the data integrity signals.

The above steps describe recording one virtual cylinder on tape 10. It is to be understood that the addressing of the tape has been completed prior to operation set forth in FIGURE 5; i.e., the first stripe 75 has been positioned in a transducing relationship to DRD 22. In one embodiment of the invention a virtual cylinder, such as cylinder 70, is written such that each cylinder is independently recorded. However, it may be desired in some systems to record a succession of such virtual cylinders. In that case, a branch instruction 101 will sense whether or not the appropriate number of cylinders have been recorded on tap 10. If so, the recording operation is exited to other operations of computer 62. On the other hand, if more cylinders are to be recorded in this sequence the steps QT235 through QT401 are again performed for each cylinder. It should be noted that the data integrity signal is recorded three times for each virtual cylinder. while the address of the signal transfer path is only recorded once in the first stripe 75. Alternatively the address can be recorded in the last stripe 77 as well as the RO stripe demarking the end of the virtual cylinder 70.

Each of the indicated subroutines are shown in abbreviated form, i.e., only those instructions having a pertinency to a practice of the invention. are shown. QT235 is shown in FIGURE 7 as consisting of a single instruction which takes zeros and records zeros in the count area. such as registers 42A. Register 42A includes a byte indicating whether or not the count value is valid. Therefore instruction AE00 also resets the counter valid flag indicating that nothing has been read from tape 10 or nothing has been recorded on tape 10.

QB455 increments the destage count, herein termed MVD count. Three instructions shown in FIGURE 8 show that at 7A5C the previous count value is fetched from the destage count register 23A and placed into the calculator portion 80 of FIGURE 4A. The fetched count is then incremented at 7A68 in ALU 82. The incremented count is then stored back into the registers 23A by instruction located at 7D2C.

As mentioned earlier. the FIGURE 5 illustrated incrementing of the MVD count is but one of two best modes. FIGURE 9 illustrates the second best mode wherein the computer 62 has an idle scan routine which it repetitively enters when it is waiting for an action request from a host DASD 60 or lower level 61. Such an idle scan routine consists of a plurality of branch instructions which respond to interrupt or attention conditions for branching to appropriate programming indicated as being contained in registers 68. The MVD count is incremented once each execution of the idle scan routine QB455, as shown in FIGURE 8. Since the idle scan routine is always used more frequently than recording operations occur. the number of times the MVD count is incremented has no relationship to the number of recording operations but is always greater than the number of recording operations. The reasons for incrementing the MVD count in the idle scan routine is for ease of programming consideration.

Returning now to FIGURE 5. subroutine QT150 is shown in detail in FIGURE 10. The portion that applies to the present invention includes instruction located at 877C within registers 68 which fetches the DRD address. That is, this is the address to be recorded in stripe 75. To record the address the instruction located at 8BD8 is stored in the data buffer store 92 of FIGURE 4A. From DBS 92 the address goes automatically to DRD 22 for recording. Then the MVD count is fetched by instruction 86DC from the destage registers 23A. The count is then stored in DBS 92 by instruction 86B0 and then recorded on the tape.

As seen in FIGURE 4 K10 is shown as being recorded before the address. Either situation is appropriate. The advantage of recording the address second is that it is checked for data integrity along with the data signals.

Then the first stripe is written via subroutine QT401 shown in FIGURE 11. Actually FIGURES 11 and 12 are substantially identical except for the location of the instructions.

Accordingly, both will be simultaneously described. First the count is fetched such as by instruction at 9C54. Then the count is stored in the buffer such as by instruction 915C. Then the rest of the stripe is fetched and stored in DBS 92 as can be envisioned easily by one of ordinary skill in the art. Then, of course, subsequent stripes are written until the last stripe is to be written. Then at QT360 the data integrity count is written as indicated by the FIGURE 5 instruction level flow chart. Then the intermediate stripes 78 are erased to all zeros. Then the delimiting stripe of virtual cylinder 70 R0 is written by QT401 as shown in FIGURE 11.

The read and verification of the data integrity signals is shown in FIGURE 6. A read instruction has been received from one of the hosts by the computer 62 and the read operation has been set up. The portion that pertains to practicing the present invention is shown in block form in FIGURE 6 and described in detail later. The count area as above described is cleared by the previously described routine QT235. Then the routine at QT165 reads the first stripe which contains a first copy of the recorded data integrity signal.

Subsequent stripes are read when the last stripe 77 is read. Then the branch instruction at 102 determines whether or not there was an error condition in the readback of last stripe 77. If the readback was OK. that is, the error detection and corrections (not shown) together with the readback circuits (not shown) are provided error-free data from last stripe 77. the computer responds to QT380 to read the last count from DBS 92 and make a compare with the first read count read during QT165. The results of the comparison are set in a flag and the read routine is exited via branch instruction 103 which operates the same way as the previously described branch instruction 101.

If the last stripe 77 had an error condition. such that the validity of the readback data integrity signal K10 is in question. then the computer responds to QT434 to make the read last count invalid, i.e.. makes it all zeros, and resets the count valid flag (not shown). Then the subsequent stripes are read, including delimiter stripe RO. Then the computer responds to QT421 to compare the first count read via It 165 and the RO stripe copy of K10 for making a data integrity comparison. The results of the comparison are made available to the host 66,67 at MSC. In the constructed embodiment. the RO count is merely a backup count for the data integrity signal of last stripe 77. In the alternative, all three data integrity signals in stripes 75.

77 and RO could be compared.

The instructions pertinent to practicing the present invention from QT165 are shown in FIGURE 13. First the count is fetched by instruction A2B0. The computer 62 then determines whether or not the count is zero at A2E4. If it is not zero, then at A2E8 the count valid flag is set. This means that an all zero count indicates an invalid flag. The just read count is then saved in registers 42A.

QT380 is shown in FIGURE 14 wherein the count K10 from last strip 77 is read and identified as K10'. At D478 the count is sent to the three registers GA. GB. GC of the microprogram registers 87. Remember the count is three bytes long with each of the three registers GA. GB, GC containing one byte. The saved MVD count from register 42A is fetched by instruction D484. The two counts are then compared in ALU 82 for equality. instruction BOE4 is executed. It should be noted that if the count is not valid there is no comparison and no loss of data integrity can be indicated. Since the one stripe is in error such error will be communicated to the host such that appropriate protective action can be taken.

While the above flow charts show instructions usable particularly with the FIGURE 4A illustrated computer, no limitation thereto is intended. Any programmable processor may be employed, such as taught by Samir S. Hassen in Microprogramming Principles and Practices, Prentice Hall, Englewood Cliffs, New Jersey, 1970, Library of Congress Number 72-122612.

Subcoding of the illustrated flow charts is well within the skill of an average programmer.

To summarise, there has been described data processing apparatus including a data storage subsystem and a data handling subsystem (i.e. processing system, transmission subsystem, further storage subsystem) within which a recording and accessing protocol obtains, means to generate and record a pair of data set identifiers at the beginning and end of the writing of a data set into the storage subsystem, such pair of identifiers being unique to the data set and independent of the protocol, and means to cause an error indication or absence of a validation indication (collectively error signal generating) when an apparent data set is read from the storage subsystem which is not bounded by a pair of data set identifiers which match.

The identifiers of each pair may have a predetermined relationship, the error signal generator means being adapted to test for the relationship. The identifiers of each pair may be identical. The identifiers of a pair may include an indication of the source of the data set they are unique to. The identifiers of a pair may include a time of writing indication. The identifier generating means may function through progressive writing operations according to a maximal length shifting sequence. The identifier generating means incorporates a pseudo noise pattern sequence generator. The identifier generating means may incorporate a serial number generator, the identifier of a pair incorporating the next serial generated number.

As indicated, the storage subsystem and the handling subsystem may form adjacent levels of a hierarchical data storage system. the storage subsystem being the lower, the transfer of data to the lower level being termed destaging and the transfer of data to the higher level being termed staging. the identifier pair generating means being operative on destaging and the error signal generator being operative on staging. Means may be provided for stripping the identifier pair from a validly staged data set.

There may be a plurality of independent data transfer paths between the two levels, and the identifier pair generating means being arranged to include in the identifier pair accompanying a destaged data set an indication of the data transfer path used/to be used for the destaging operation. The apparatus may be arranged to log all destaging errors indicated by lack of identifier pair matching on attempted staging and to indicate which of the transfer paths has given rise (presumptively) to the greatest number of destaging errors and may be arranged to mark a staged set of signals for which the identifier pair do not match as having suspect data integrity with possible data errors.

The storage system may be connected to a plurality of host computers. one such being currently designated as primary host. the apparatus being arranged to signal the primary host as to the identity of all staged data sets for which the identifier paris do not match. The data storage subsystem may record data on a fixed size segmented recording medium, and include means for recording a further identifier matching the pair associated with a data set at intermediate segment boundaries traversed during the recording of the data set.

Claims (16)

WHAT WE CLAIM IS:

1. Data processing apparatus including a data storage subsystem and a data handling subsystem (i.e. processing system. transmission subsystem. further storage subsystem) within which a recording and accessing protocol obtains, means to generate and record a pair of data set identifiers at the beginning and end of the writing of a data set into the storage subsystem. such pair of identifiers being unique to the data set and independent of the protocol. and means to cause an error indication or absence of a validation indication (collectively error signal generating) when an apparent data set is read from the storage subsystem which is not bounded by a pair of data set identifiers which match.

2. Apparatus as claimed in Claim 1 in which the identifiers of each pair have a predeter mined relationship and the error signal generator means is adapted to test for the relation ship.

3. Apparatus as claimed in Claim 2 in which the identifiers of each pair are identical.

4. Apparatus as claimed in any preceding claim in which the identifiers of a pair include an indication of the source of the data set they are unique to.

5. Apparatus as claimed in any preceding claim in which the identifiers of a pair include a time of writing indication.

6. Apparatus as claimed in Claim 1 in which the identifier generating means functions through progressive writing operations according to a maximal length shifting sequence.

7. Apparatus as claimed in Claim 1 in which the identifier generating means incorporates a pseudo noise pattern sequence generator.

8. Apparatus as claimed in any preceding claim in which the identifier generating means incorporates a serial number generator, the identifier of a pair incorporating the next serial generated number.

9. Apparatus as claimed in any preceding claim in which the storage subsystem and the handling subsystem form adjacent levels of a hierarchical data storage system, the storage subsystem being the lower, the transfer of data to the lower level being termed destaging and the transfer of data to the higher level being termed staging1 the identifier pair generating means being operative on destaging and the error signal generator being operative on staging.

10. Apparatus as claimed in Claim 9 in which there are means for stripping the identifier pair from a validly staged data set.

11. Apparatus as claimed in Claim 10 in which there are a plurality of independent data transfer paths between the two levels, and the identifier pair generating means is arranged to include in the identifier pair accompanying a destaged data set an indication of the data transfer path used/to be used for the destaging operation.

12. Apparatus as claimed in Claim 11 arranged to log all destaging errors indicated by lack of identifier pair matching on attempted staging and to indicate which of the transfer paths has given rise (presumptively) to the greatest number of destaging errors.

13. Apparatus as claimed in any of Claims 9 to 12 arranged to mark a staged set of signals for which the identifier pair do not match as having suspect data integrity with possible data errors.

14. Apparatus as claimed in any of Claims 9 to 13 wherein the storage system is connected to a plurality of host computers, one such being currently designated as primary host, the apparatus being arranged to signal the primary host as to the identity of all staged data sets for which the identifier pairs do not match.

15. Apparatus as claimed in any preceding claim in which the data storage subsystem records data on a fixed size segmented recording medium, and including means for recording a further identifier matching the pair associated with a data set at intermediate segment boundaries traversed during the recording of the data set.

16. Apparatus as claimed in Claim 1 when substantially as hereinbefore described with reference to and as illustrated in the accompanying drawings.