GB1573950A - Bistable logic element - Google Patents

Bistable logic element Download PDF

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Publication number
GB1573950A
GB1573950A GB562577A GB562577A GB1573950A GB 1573950 A GB1573950 A GB 1573950A GB 562577 A GB562577 A GB 562577A GB 562577 A GB562577 A GB 562577A GB 1573950 A GB1573950 A GB 1573950A
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United Kingdom
Prior art keywords
transistor
zone
emitter
base
type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB562577A
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Thales SA
Original Assignee
Thomson CSF SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Thomson CSF SA filed Critical Thomson CSF SA
Publication of GB1573950A publication Critical patent/GB1573950A/en
Expired legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0214—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L
    • H01L27/0229—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L of bipolar structures
    • H01L27/0233—Integrated injection logic structures [I2L]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/07—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
    • H01L27/0744—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common without components of the field effect type
    • H01L27/075—Bipolar transistors in combination with diodes, or capacitors, or resistors, e.g. lateral bipolar transistor, and vertical bipolar transistor and resistor
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/082—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using bipolar transistors
    • H03K19/091—Integrated injection logic or merged transistor logic

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Bipolar Integrated Circuits (AREA)

Description

(54) A BISTABLE LOGIC ELEMENT (71) We, THOMSON-CSF, a French Body Corporate, of 173, Boulevard Haussmann-75008 Paris-France-do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement:- This invention relates to a new bistable logic element with very small dimensions and a very high switching speed.
This element is of the type comprising two complementary transistors, the collector of the second transistor being connected to the base of the first transistor, the emitter of the first transistor being connected to earth and the emitter of the second transistor being connected to a fixed bias voltage source, the two transistors being integrated on the same substrate, the current flowing through the first transistor perpendicularly and parallelly to the surface of the substrate, and the current flowing through the second transistor parallelly to the surface of the substrate.
According to the present invention, there is provided a bistable logic element comprising a first and a second complementary transistor, the first transistor being a vertical transistor and the second transistor being a lateral transistor whose base is formed by a first zone of a first conductivity type in which the logic element is integrated, and whose collector is formed by the base zone of the first transistor, said first zone having a free surface, the emitter of said first transistor having the first type of conductivity and a connection to earth, the emitter of said second transistor having a second type of conductivity opposite to the first and a connection to the pole of a bias supply having the polarity adapted to attract the majority carriers of said first zone and to cause a current in said second transistor to flow parallel to said free surface, said first transistor comprising a two part collector formed by said first zone and having said first type of conductivity, a first part being a second zone included in said first zone, said second zone having a shallow depth, and a second part being a third zone causing the current to flow in said first transistor both perpendicularly and parallel to said free surface.
The invention will be better understood from the following description in conjunction with the accompanying drawings, wherein: Figures 1 and 2 are respectively a section through and a plan view of a first embodiment of the invention.
Figure 3 shows the equivalent circuit diagram of the structure illustrated in Figure 1.
Figure 4 is one example of application of the structure illustrated in the preceding figures.
In Figures 1 and 2, the reference 1 denotes a substrate of silicon weakly doped of n-type conductivity (1016 at/cc) for example.
In the following, all the conductivity types may be reversed.
The substrate is covered by a thin layer 2 of silica.
A zone 3 of p-type conductivity (impurity concentration 10'7 at/cc, depth approximately 1 micron) is initially formed in this substrate by means of suitable masks and by ion implantation or by diffusion.
Zones 40 and 41 of p+ type conductivity both acting as collectors are then implanted in this zone through another mask. Of these two zones, the zone 41 is the so-called inner zone of small dimensions, whilst the zone 40 is the so-called outer zone and surrounds the structure. These two collectors are the collectors of one and the same transistor T1 which is shown in Figure 3 and which is of the pnp-type. A third zone 42, also of p+ type conductivity, is the emitter of this transistor.
Accordingly, this transistor comprises two collectors and one emitter and the current flows through it both parallel to and perpendicularly to the surface of the substrate. The depth of the zones 40 and 41 is of the order of 0.3 micron and the doping density is of the order of 1019 to 1020 at/cc.
Two n-type zones with a doping density of 1018 at/cc and a depth of 0.5 micron are then implanted. The first zone 51 is the base of this transistor and is also the collector of a complementary transistor T2 which forms part of the structure. The base 51 includes an n+ diffusion 52 with a depth of 0.3 micron and a doping density of 10'8 at/cc, this diffusion being connected to a metallic contact B. The second n- type zone 53 with the same depth as and separated from the first zone is the emitter of the second transistor.
It has the same doping concentration as the first zone and is in the shape of a T. The transverse part of this T acts as the actual emitter zone. The longitudinal part acts as a resistance Rs and is connected to an n+ diffusion 54 which is connected through an ohmic contact to a bias voltage source Vp of the assembly.
Similarly, the emitter 42 is connected to earth through a contact E. The base zone of the second transistor is provided by the part of zone 3 situated between the zones 53 and 52. The remainder of this zone 3 connected to the supply -Vp acts as a resistance RCC in series with said ase.
The equivalent circuit diagram of Figure 3 is thus obtained.
This structure is an element with two stable states and functions in the following manner: The contact B may be connected to earth or to a voltage Vp and acts as the input contact, being connected to the base of the transistor T1.
The output contact is the outer collector Cex.
The mode of operation is as follows: (a) B is connected to earth. The transistor T1 is blocked, its base and its emitter being connected to earth. The point C.x, disconnected from earth, is substantially at the potential Vp. The transistor T2, of which the base is at the potential of approximately -Vp, is also blocked. The point Ccx is substantially at the potential VD.
(b) The point B is at the potential Vp.
The transistor T1 is thus conductive. The point Ccx is connected to earth and also renders the transistor T2 conductive.
Accordingly, the structure has two stable states and may act as an inverter, the input being at the level "1" and the output being of necessity at the level "0" and vice versa.
This inverter is integrated in a single substrate. The resistances are integrated into the same substrate. The emitter and the collector of n-type conductivity can be implanted or diffused simultaneously with the same mask, thereby providing for perfect control of the thickness of the base of the lateral npn transistor.
Several inverters of the type shown in Figure 3 may be connected in series, the output Cex, of one being connected to the point B2 of the next. Since the multiplecollector transistor functions both in the lateral direction and in the transverse direction, it has a very low resistance in the conductive state.
The end product is thus a structure such as that illustrated in Figure 4 which shows two inverters INV1 and INV2. When one is conductive, the next is blocked and vice versa.
The references. of Figure 4 with respective indices 1 and 2 designate the same elements as in Figure 3.
All the conductivity types may of course be reversed with the same doping densities, and the bias voltage is reversed and becomes positive.
WHAT WE CLAIM IS: 1. A bistable logic element comprising a first and a second complementary transistor, the first transistor being a vertical transistor and the second transistor being a lateral transistor whose base is formed by a first zone of a first conductivity type in which the logic element is integrated, and whose collector is formed by the base zone of the first transistor, said first zone having a free surface, the emitter of said first transistor having the first type of conductivity and a connection to earth, the emitter of said second transistor having a second type of conductivity opposite to the first and connection to the pole of a bias supply having the polarity adapted to attract the majority carriers of said first zone and to cause a current in said second transitor to flow parallel to said free surface, said first transistor comprising a two part collector formed by said first zone and having said first type of conductivity, a first part being a second zone included in said first zone, said second zone having a shallow depth, and second part being a third zone causing the current to flow in said first transistor both perpendicularly and parallel to said free surface.
2. A bistable element as claimed in Claim 1, wherein a substrate surrounds said first zone, this substrate being of the second conductivity type, said first zone having a portion of small dimensions acting as the base for the second transistor, the remaining
**WARNING** end of DESC field may overlap start of CLMS **.

Claims (4)

**WARNING** start of CLMS field may overlap end of DESC **. Two n-type zones with a doping density of 1018 at/cc and a depth of 0.5 micron are then implanted. The first zone 51 is the base of this transistor and is also the collector of a complementary transistor T2 which forms part of the structure. The base 51 includes an n+ diffusion 52 with a depth of 0.3 micron and a doping density of 10'8 at/cc, this diffusion being connected to a metallic contact B. The second n- type zone 53 with the same depth as and separated from the first zone is the emitter of the second transistor. It has the same doping concentration as the first zone and is in the shape of a T. The transverse part of this T acts as the actual emitter zone. The longitudinal part acts as a resistance Rs and is connected to an n+ diffusion 54 which is connected through an ohmic contact to a bias voltage source Vp of the assembly. Similarly, the emitter 42 is connected to earth through a contact E. The base zone of the second transistor is provided by the part of zone 3 situated between the zones 53 and 52. The remainder of this zone 3 connected to the supply -Vp acts as a resistance RCC in series with said ase. The equivalent circuit diagram of Figure 3 is thus obtained. This structure is an element with two stable states and functions in the following manner: The contact B may be connected to earth or to a voltage Vp and acts as the input contact, being connected to the base of the transistor T1. The output contact is the outer collector Cex. The mode of operation is as follows: (a) B is connected to earth. The transistor T1 is blocked, its base and its emitter being connected to earth. The point C.x, disconnected from earth, is substantially at the potential Vp. The transistor T2, of which the base is at the potential of approximately -Vp, is also blocked. The point Ccx is substantially at the potential VD. (b) The point B is at the potential Vp. The transistor T1 is thus conductive. The point Ccx is connected to earth and also renders the transistor T2 conductive. Accordingly, the structure has two stable states and may act as an inverter, the input being at the level "1" and the output being of necessity at the level "0" and vice versa. This inverter is integrated in a single substrate. The resistances are integrated into the same substrate. The emitter and the collector of n-type conductivity can be implanted or diffused simultaneously with the same mask, thereby providing for perfect control of the thickness of the base of the lateral npn transistor. Several inverters of the type shown in Figure 3 may be connected in series, the output Cex, of one being connected to the point B2 of the next. Since the multiplecollector transistor functions both in the lateral direction and in the transverse direction, it has a very low resistance in the conductive state. The end product is thus a structure such as that illustrated in Figure 4 which shows two inverters INV1 and INV2. When one is conductive, the next is blocked and vice versa. The references. of Figure 4 with respective indices 1 and 2 designate the same elements as in Figure 3. All the conductivity types may of course be reversed with the same doping densities, and the bias voltage is reversed and becomes positive. WHAT WE CLAIM IS:
1. A bistable logic element comprising a first and a second complementary transistor, the first transistor being a vertical transistor and the second transistor being a lateral transistor whose base is formed by a first zone of a first conductivity type in which the logic element is integrated, and whose collector is formed by the base zone of the first transistor, said first zone having a free surface, the emitter of said first transistor having the first type of conductivity and a connection to earth, the emitter of said second transistor having a second type of conductivity opposite to the first and connection to the pole of a bias supply having the polarity adapted to attract the majority carriers of said first zone and to cause a current in said second transitor to flow parallel to said free surface, said first transistor comprising a two part collector formed by said first zone and having said first type of conductivity, a first part being a second zone included in said first zone, said second zone having a shallow depth, and second part being a third zone causing the current to flow in said first transistor both perpendicularly and parallel to said free surface.
2. A bistable element as claimed in Claim 1, wherein a substrate surrounds said first zone, this substrate being of the second conductivity type, said first zone having a portion of small dimensions acting as the base for the second transistor, the remaining
part being connected by an ohmic contact to the bais voltage source and acting as a leakage resistance.
3. An element as claimed in Claim 2, wherein the emitter of the second transistor is formed by a fourth zone of the second conductivity type included in said first zone, said second zone having an ohmic contact for connection to said supply, this second zone acting both as an emitter for the second transistor and as a biassing resistance.
4. A bistable element as hereinbefore described with reference to Figures 1 to 4.
GB562577A 1976-02-13 1977-02-10 Bistable logic element Expired GB1573950A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR7604082A FR2341232A1 (en) 1976-02-13 1976-02-13 BISTABLE LOGIC ELEMENT

Publications (1)

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GB1573950A true GB1573950A (en) 1980-08-28

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GB562577A Expired GB1573950A (en) 1976-02-13 1977-02-10 Bistable logic element

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JP (1) JPS5299056A (en)
CA (1) CA1081862A (en)
DE (1) DE2705796A1 (en)
FR (1) FR2341232A1 (en)
GB (1) GB1573950A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2414778A1 (en) * 1978-01-13 1979-08-10 Thomson Csf STATIC MEMORY ELEMENT WITH RANDOM ACCESS
DE3379563D1 (en) * 1982-12-20 1989-05-11 Philips Nv Integrated circuit and method

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1927585C3 (en) * 1969-05-30 1978-10-12 Siemens Ag, 1000 Berlin Und 8000 Muenchen Transistor with lateral emitter zone and equally doped lateral collector zone
IT957917B (en) * 1971-05-17 1973-10-20 Smiths Industries Ltd IMPROVEMENTS IN SEMICONDUCTOR DEVICES

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Publication number Publication date
CA1081862A (en) 1980-07-15
JPS5299056A (en) 1977-08-19
FR2341232B1 (en) 1979-07-20
FR2341232A1 (en) 1977-09-09
DE2705796A1 (en) 1977-08-18

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Legal Events

Date Code Title Description
PS Patent sealed
746 Register noted 'licences of right' (sect. 46/1977)
PCNP Patent ceased through non-payment of renewal fee