GB1573178A - Integrated semiconductor memory cirucuits - Google Patents

Description

(54) INTEGRATED SEMICONDUCTOR MEMORY CIRCUITS (71) We, INTERNATIONAL BUSINESS MACHINES CORPORATION, a Corporation organized and existing under the laws of the State of New York in the United States of America, of Armonk, New York 10504, United States of America do hereby declare the invention for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement:- This invention relates to integrated semiconductor memory circuits.

An integrated semiconductor memory circuit according to one aspect of the invention, comprises a semiconductor substrate, a dielectric medium disposed on said substrate, a first conductor disposed on said dielectric medium overlying a storage node in the surface region of said substrate, means to apply a data signal to said conductor to form a depletion well at the storage node and so render it capable of storing charge, a zone in the surface region of said substrate which is responsive to the application of a potential thereto to provide a charge source, the zone being spaced from said storage node, and a further conductor over]ying said surface region between said charge source and said storage node and insulated from said first conductor and means to apply a control voltage to said further conductor to form a depletion layer in said surface region coupling said charge source to said storage node.

Other aspects of the invention are defined in the claims appended hereto.

How the invention can be carried into effect will now be described by way of example. with-reference to the accompanying drawings, in which: FIG. 1 represents a cross-section of an integrated semiconductor memory circuit array embodying the invention, FIG. 2 is a simplified electrical schematic diagram of the memory array illustrated in FIG. 1, FIG. 3A is a plan of the memory array illustrated in FIG. 1 showing cells coupled to two word lines; FIG. 3B is a section taken on line 3B-3B in FIG. 3A; FIG. 3C is a section taken on line 3C-3C in FIG. 3A; FIG. 4 is a section similar to that illustrated in FIG. 3B but of another embodiment of the invention.

FIG. 5A represents a plan of a further semiconductor memory array embodying the invention; FIG. 5B is a section taken on line 5B-5B in FIG. 5A; FIG. 5C is a section on line 5C-5C in FIG.

5A; FIG. 6 comprises a series of schematic diagrams indicating charge flow into depletion wells at different time periods, FIG. 7 is a pulse program used to operate the memory array of FIGS 5A to 5C.

FIG. 8A is a plan of another semiconductor memory array embodying the invention; FIG. 8B is a section on line 8B-8B in FIG.

8A; FIG. 8C is a section on line 8C-8C in FIG.

8A; FIG. 9 comprises a series of schematic diagrams indicating charge flow into depletion wells at different time periods; and FIG. 10 is a pulse program used to operate the memory array of FIGS. 8A to 8C.

A memory array (FIG. 1) includes a semiconductor substrate 10 having disposed therein diffusion regions 12 and 14. The substrate 10 may be of p type conductivity, typically boron doped, with the diffusion regions 12 and 14 of n+ type, typically phosphorus or arsenic doped. Terminals 16 and 18 are connected to diffusion regions 12 and 14, respectively, to provide appropriate bias voltages for producing a source of charges. Disposed on the surface of the semiconductor substrate 10 is a first insulation layer 20 which is preferably made of silicon dioxide. A second insulation layer 22, preferably made of silicon nitride, is formed over the first insulation layer 20.

The thickness of the silicon dioxide layer 20 may be, for example, 500 angstroms and the thickness of the silicon nitride layer 22 may be, for example, 200 angstroms. A plurality of conductive lines 24, 26, 28 and 30, arranged parallel to each other, are disposed over the insulating layers 20 and 22 between the diffusion regions 12 and 14. The conductive lines 24, 26, 28 and 30, preferably made of doped polycrystalline silicon, are covered with insulating layers of oxidized polycrystalline silicon 32, 34, 36 and 38, respectively. A metal line 40 is disposed over the conductive lines 24, 26, 28 and 30 in a direction orthogonal to the direction of the conductive lines 24, 26, 28 and 30. The conductive lines and the metal line are insulated from each other by the insulating layers 32, 34, 36 and 38. The conductive lines 24. 26, 28 and 30 are portions of bitlsense lines B1, B2, B3 and B4, and the metal line 40 is a portion of a word line W 1.

In the operation of the array illustrated in FIG. 1 a suitable voltage is applied to the terminals 16 and 18 for providing a source of charges, preferably electrons, from diffusion regions 12 and 14. Voltages representing binary digits are applied to bit/sense lines B1, B2, B3 and B4. The voltages applied to these bit/sense lines produce depletion wells in the semiconductor substrate 10, as indicated by dashed lines 42, 44, 46 and 48. The depth of each of these depletion wells depends upon the magnitude of the voltage applied to the respective conductive lines 24, 26, 28 and 30. These conductive lines 24, 26, 28 and 30 along with the depletion wells and the dual insulating layers 20 and 22 form storage capacitors 50, 52, 54 and 56 of a word line W1 defined by metal line 40. It can be seen in FIG. 1 that the depletion wells 42 and 46 associated with storage capacitors 50 and 54 are deeper than the potential wells 44 and 48 associated with capacitors 52 and 56, respectively. In the array illustrated in FIG.

1 it will be assumed that the deeper potential wells 42 and 46 are to represent a 1 bit of binary information whereas the shallower wells 44 and 48 are to represent a 0 bit of binary information. In order to store information in capacitors 50, 52, 54 and 56 it is necessary to introduce charges into the potential wells of these capacitors from the diffusion regions 12 and 14. To introduce charges from charge sources 12 and 14 into the depletion wells 42, 44, 46, and 48, a conductive path is selectively produced between the sources 12 and 14 and each of the depletion wells 42, 44, 46 and 48. This path is produced by creating additional depletion regions 58 at the surface of the semiconductor substrate 10 between the diffusion regions 12 and 14 and the depletion regions 42 and 48, respectively, and also between the depletion regions 42 and 44, 44 and 46, and 46 and 48. These depletion regions 58 are produced by a word pulse having a positive polarity applied to the word line W 1. As is known, the charges flow from the diffusion regions 12 and 14 through depletion regions 58 into potential wells that are at a potential initially more positive than the potential applied to terminals 16 and 18 to form an inversion layer at the surface of the substrate 10. After depletion wells 42, 44, 46 and 48 are filled with the charges the word pulse is terminated and the depletion regions 42, 44, 46 and 48, now forming inversion layers, are isolated from the charge sources 12 and 14 and from each other. The voltage on the bit lines B1, B2, B3 and B4 representing the binary information is turned off after the word line pulse has terminated and puddles or packets of charge of two different magnitudes remain in substrate 10 to represent the stored binary digits. In a preferred array, a rest potential of about +5 volts is supplied to all bit lines at all times. Depending on the data to be written into storage capacitors 50, 52, 54 and 56 for storing a given word, selected bit lines B1, B2, B3 and B4 have their voltages raised from +5 volts to +10 volts and a word pulse of about +5 volts is applied to word line W1. To read the information stored in capacitors 50, 52, 54 and 56, the word line W1 is pulsed again to +5 volts, with the bit lines remaining at the rest potential, to connect all capacitors to the reference voltage at the terminals 16 and 18. The bit lines which had been at +10 volts while writing, that is, those storing a 1 bit of information, will experience a relatively strong positive discharge signal while the other bit lines representing a 0 bit of information will receive substantially a signal of zero magnitude. In the alternative, if desired, the rest potential on the bit lines may be +10 volts while the bit drive voltage may be lowered to +5 volts when storing information in, for example, the storage capacitors which are to store 0 bits of binary information.

In order to more clearly understand its operation, there is shown in FIG. 2 a simplified electrical schematic diagram of the memory array illustrated in FIG. 1 wherein common reference numerals refer to like elements. The principle elements of the array illustrated in FIG. 1 are shown in FIG.

2 as being the bit lines B1, B2. B3 and B4 connected to plates 24, 26, 28 and 30, respectively. These plates 24, 26, 28 and 30 along with plates 42, 44, 46 and 48, identified as depletion regions or inversion layers in connection with FIG. 1, provide the storage capacitors 50, 52, 54 and 56, respectively. The plates 42, 44, 46 and 48 are connected to a reference potential Vref through switches 58, indicated also as depletion region or inversion layers in connection with FIG. 1, when the word pulse is applied to the word line W1 of FIG. 1 to operate the switches 58 simultaneously. The switches 58 operate simultaneously since the word line W1 which includes metal line 40, as can be seen in FIG. 1. is in intimate contact with the silicon nitride layer 22 in the areas between the capacitors 50, 52, 54 and 56 and between the capacitors 50 and 56 and the diffusion regions 12 and 14, respectively, to produce the interconnecting depletion regions 58. It can be seen that by applying voltages of greater magnitude to, say, bit lines B1 and B3 when the switches 58 are closed, a larger charge is stored in capacitors 50 and 54 than is stored in capacitors 52 and 56.

The difference in voltage in these capacitors then can be readily detected by known voltage measuring techniques.

In FIG. 3A there is provided a plan view of a memory array showing two word lines Wl and W2. Word line W1 is the same word line illustrated in section in FIG. 1. The section shown in FIG. 1 is indicated in FIG. 3A as being taken through FIG. 3A at 1-1. The word line W2 is similar to word line W1 and has as a portion thereof another metal line 60 which is similar to metal line 40 of word line W1. The word lines W1 and W2 are connected to a word driver 62 which produces the necessary word pulses for word lines W1 and W2. The word lines W1 and W2 share the bit lines B1, B2, B3 and B4 which are connected to unit 64. Unit 64 includes any suitable bit drivers, sense amplifiers. and a bias source. At appropriate times the unit 64 produces bit pulses for writing information into the storage capacitors 50. 52, 54 and 56 in cooperation with a pulse on a selected one of word lines W1 and W2. When reading information from the storage capacitors 50, 52, 54 and 56. the bit drivers are disconnected from the bit lines B1. B2. B3 and B4 and sense amplifiers are connected to these bit lines, as is well known in the art. Since the bit lines including conductive lines 24, 26, 28 and 30 preferably have a rest potential of approximately +5 volts, the unit 64 may be utilized to provide the +5 volt bias voltage for these conductive lines. Although the capacitors 50. 52. 54 and 56 along a word line do not require isolation from each other, the capacitors associated with one of the word lines W1 and W2 must be isolated from the capacitors of the other of the word lines W1 and W2. Accordingly. as indicated in FIGS.

3A, 3B, which is a sectional view taken through FIG. 3A along lines 3B-3B, and FIG. 3C, which is a sectional view taken through FIG. 3A at 3C-3C, thick oxide strips 66 are provided to isolate the word lines from each other. It can be understood that the memory array illustrated in FIGS.

3A, 3B and 3C, having two word lines W1 and W2, operates in the same manner as does the array illustrated in FIG. 1 of the drawing except that it should be further understood that the word driver 62 is responsive to known circuitry, not shown, which selects only one word line at a time.

Consequently, either the word line W1 associated with storage capacitors 50, 52, 54 and 56 is selected, or word line W2 associated with storage capacitors similar to capacitors 50, 52, 54 and 56 is selected. The storage capacitors associated with word line W2 are located at the intersection of the conductive lines 24, 26, 28 and 30 and the metal line 60 of word line W2. When operating a memory array with two or more word lines, the voltage applied to the diffusion regions 12 and 14 must have a value such that there will be little or no disturbance in the storage cells of the word lines which are not selected.

It should be noted that the voltage applied to the terminals 16 and 18 for introducing charges into substrate 10 for the potential wells 42, 44, 46 and 48 should have a magnitude such that the n+ diffusion regions 12 and 14 produce a sufficient supply of electrons to fill the wells in a short period of time. An example of suitable voltage magnitudes and polarities for the array illustrated in FIGS. 3A, 3B and 3C is -3.0 volts applied to substrate 10 and approximately +3.5 to +4.0 volts applied to each of the terminals 16 and 18 when the voltage applied to the word line is 0 to +5 volts and the voltage applied to the bit lines is between +5 and +10 volts. It should also be noted that since this memory array utilizes dynamic cells they must be refreshed within predetermined time intervals in order to prevent the loss of stored information. Any known suitable refreshing technique may be employed.

In FIG. 4 there is shown a section similar to that illustrated in FIG. 3B but of another semiconductor memory array embodying the invention. A number of the elements shown in FIG. 4 are similar to those illustrated in FIG. 3, with like reference numerals representing the same elements. However, the embodiment in FIG. 4 differs from that illustrated in FIG. 3B in that the thick oxide 66 shown in FIGS. 3A, 3B and 3C has been removed and an ion implanted channel stop 68 is provided between and outside the word lines indicated by conductive lines 40 and 60. The implanted channel stop 68, which may be produced by the introduction of boron into the substrate 10, as is known, provides the isolation between word lines W1 and W2 which was provided in FIG. 3B by the thick oxide 66. The embodiment of FIG. 4 also differs from that illustrated in FIG. 3B in that the embodiment of FIG. 4 includes diffusion regions 70 forming with the conductive lines 24, 26, 28 and 30 the storage capacitors for the array. Phosphorus or arsenic doping may be used to form the diffusion regions 70 under the conductive lines 24, 26, 28 and 30 where they intersect with the metal lines 40 and 60. The embodiment of the memory array illustrated in FIG. 4 operates in the same manner as does the embodiment illustrated in FIG. 3B except that the rest potential of, say +5 volts, is not required on the conductive lines 24, 26, 28 and 30, and the binary digits may be simply represented by zero and +5 volts for 0 and 1 bits of information, due to the use of diffusion regions 70. An important aspect of the embodiment illustrated in FIG.

4 is that the array is made in a more planar fashion, with the exception of the metal lines 40 and 60. In fabricating this embodiment, the channel stops 68 may be formed by ion implantation after metal lines 40 and 60 have been formed in order to accurately align the channel stops 68 in the substrate 10.

The memory array, illustrated in FIGS.

3A, 3B and 3C, is fabricated in a manner similar to the fabrication of charge coupled devices which are disclosed in, for example, U.K. Patent Specification No. 1369606.

After the diffused reference voltage lines indicated in the figures as diffusion regions 12 and 14 have been formed, thick oxide 66 or, if desired, oxide/aluminium is grown over the surface of the substrate 10. A line is etched in the thick oxide 66 and thin oxide 20 is grown in the etched line. A thin layer of nitride 22 is then deposited over the entire surface. Doped polycrystalline silicon is thereafter deposited and etched to form the conductive lines 24, 26, 28 and 30. The storage capacitors or nodes are defined by the intersection of the doped polycrystalline silicon lines and the strip of thin oxide 20.

The switch for connecting the potential wells to the charge sources 12 and 14 is defined by the gap between adjacent polycrystalline silicon lines 24, 26, 28 and 30 along the thin oxide. It should be noted that this fabrication process is very simple and requires only two masks. which masks. even if poorly registered, define the cell areas of the array.

It can be seen from the plan view illustrated in FIG. 3A, that the size of each cell is equal to only approximately four times the area of the intersection of the word line W1 or W2 and more particularly the thin oxide or silicon dioxide layer 20 with one of the bit or conductive lines 24, 26, 28 and 30.

The metal lines 40 and 60 may be doped polycrystalline silicon lines similar to the conductive lines 24, 26, 28 and 30. Furthermore, the conductive lines 24, 26, 28 and 30 may be conductive metal lines, such as aluminium lines. When desired, the dual layers 20 and 22 disposed on substrate 10 between the strips of thick oxide 66 of FIGS. 3A, 3B and 3C may be replaced with a single insulation layer made of any known dielectric material, such as silicon dioxide.

Also, under some circumstances when it may be desired to provide n+ diffusions beneath the conductive lines 24, 26, 28 and 30 so as to eliminate the need to maintain a rest potential of 5 volts on the bit lines it may also be desired to use the strips of thick oxide 66 for providing the necessary isolation between word lines.

A further memory array (FIGS. SA to SC) includes a semiconductor substrate 10 having disposed therein diffusion regions 12 and 14. The substrate 10 may be of p type conductivity with the diffusion regions 12 and 14 of n+ type. Terminals 16 and 18 connect pulse sources 15 and 17 to diffusion regions 12 and 14, respectively, for producing pulses of charge. This oxide strips 19, or, if desired recessed oxide, are provided to isolate word lines W1 and W2 from each other. Disposed on the surface of the semiconductor substrate 10 between thick oxide strips 19 is a first insulation layer 20 which is preferably made of silicon dioxide. A second insulation layer 22, preferably made of silicon nitride, is formed over the first insulation layer 20 and over the thick oxide strips 19. The thickness of the silicon dioxide layer 20 may be, for example, 500 angstroms and the thickness of the silicon nitride layer 22 may be, for example, 200 angstroms. A plurality of conductive lines 24, 26, 28 and 30, arranged parallel to each other, are disposed over the insulating layers 20 and 22 between the diffusion regions 12 and 14. The conductive lines 24. 26.

28 and 30, preferably made of doped polycrystalline silicon, are covered with insulating layers of oxidized polycrystalline silicon 32.

34, 36 and 38, respectively. Metal lines 40 and 41 are disposed over the conductive lines 24, 26, 28 and 30 in a direction orthogonal to the direction of the conductive lines 24, 26, 28 and 30. The conductive lines and the metal lines are insulated from each other by the insulating layers 32, 34, 36 and 38. The conductive lines 24, 26. 28 and 30 are portions of bit/sense lines B1.

B2, B3 and B4, which are connected to unit 43, and the metal lines 40 and 41 are portions of the word lines W1 and W2. which are connected to word driver 45 which produces the necessary word pulses for word lines W1 and W2. The unit 43 includes any suitable bit drivers, sense amplifiers and a bias source.

The bit drivers of unit 43 apply voltages representing binary digits to bit/sense lines B 1. B2, B3 and B4. The voltages applied to these bit/sense lines produce depletion wells in the semiconductor substrate 10, as indicated by dashed lines 42, 44, 46 and 48 in FIG. 5B. The depth of each of these depletion wells depends upon the magnitude of the voltage applied to the respective conductive lines 24, 26, 28 and 30. These conductive lines 24, 26, 28 and 30 along with the depletion wells and the dual insulating layers 20 and 22 form storage capacitors 50, 52, 54 and 56 of the word line W1 defined by metal line 40. Likewise, word line W2 is associated with storage capacitors similar to capacitors 50, 52, 54 and 56. The storage capacitors associated with word line W2 are located at the intersection of the conductive lines 24, 26, 28 and 30 and the metal line 41. It can be seen in FIG. 5B that the depletion wells 42 and 46 associated with storage capacitors 50 and 54 are deeper than the potential wells 44 and 48 associated with capacitors 52 and 56, respectively. It is assumed that the deeper potential wells 42 and 46 are produced to represent a 1 bit of binary information, whereas the shallower wells 44 and 43 represent a 0 bit binary information.

In order to store information in capacitors 50, 52, 54 and 56 it is necessary to introduce charges into the potential wells of these capacitors from the diffusion regions 12 and 14. To introduce charges into the depletion wells 42, 44, 46, and 48, a conductive path is selectively produced between the sources 12 and 14 and each of the depletion wells 42, 44, 46 and 48. This path is produced by creating additional depletion wells 58 at the surface of the semiconductor substrate 10 between the diffusion regions 12 and 14 and the depletion wells 42 and 48, respectively, and also between the depletion wells 42 and 44, 44 and 46, and 46 and 48. These depletion wells 58. as indicated in FIG. SB of the drawing, are produced by a word pulse having a positive polarity applied from word driver 45 to the word line W1. The charges flow from the diffusion regions 12 and 14 through depletion wells 58 into potential wells that are at a potential initially more positive than the potential applied to terminals 16 and 18 to form an inversion layer at the surface of the substrate 10. After depletion wells 42, 44. 46 and 48 are filled with the charges, the word pulse is terminated and the depletion wells 42, 44, 46 and 48, now worming inversion layers for inversion storage capacitors 50, 52, 54 and 56, are isolated from the charge sources 12 and 14 and from each other. The voltages on the bit lines B1, B2, B3 and B4 representing the binary information are pulsed back to the rest potential after the word line pulse has terminated and puddles or packets of charge of two different magnitudes remain in potential wells to represent the stored binary digits. When reading the stored information from the capacitors 50, 52, 54 and 56, the bit drivers are disconnected from the bit lines B1, B2, B3 and B4 and sense amplifiers are connected to these bit lines, as is well known in the art.

In FIG. 6 there is shown a series of schematic diagrams showing charge flow from the pulsed charge sources 15 and 17 at the different time periods indicated in the pulse program of FIG. 7 which is used in the operation of the memory array of FIGS. 5A to 5C. As can be seen from the pulse program of FIG. 7, pulse sources 15 and 17 produce a charge injection pulse which is normally at +8.0 volts but is lowered to zero volts at predetermined intervals. The substrate 10 is preferably biased at -3.0 volts.

The word pulse applied selectively to word line W1 and word line W2 varies between -2.0 and +4.5 volts and the bit pulse used to write information into the cells has a rest potential of +8.5 volts and +4.5 volts for writing a, e.g., 1 bit of information. When a, e.g., 1 bit of information is being read from a cell, the bit lines having the 1 bit stored therein experience a relatively strong positive charge signal, indicated as the sense signal in FIG. 7, while the other bit lines representing a 0 bit of information receive only a signal of substantially zero magnitude. Prior to writing information into the cells, all bit lines are at +8.5 volts and the potential wells have a magnitude equal to that of wells 42 or 46.

Referring to FIGS. 6 and 7 in more detail, it can be seen that at time tl, when a 1 bit is being written into bit lines B2 and B4, the bit pulse voltage decreases to +4.5 volts, with the charge injection pulse at +8 volts, which prevents pulse sources 15 and 17 from supplying charge to the substrate 10.

Furthermore, the word pulse, which is at -2.0 volts, will not produce depletion wells 58. Accordingly, as can be seen at tl in FIG.

6, depletion wells 42, 44, 46 and 48 have been formed in the substrate 10 but no charges have been introduced into these wells from pulse sources 15 and 17. At time t2 the charge injection pulse is lowered to zero volts providing a large supply of charges which flow into the potential wells 42, 44, 46 and 48 as soon as the word pulse is raised to +4.5 volts to produce the potential wells 58. The potential wells 58 produce a conductive path between the pulse sources 15 and 17 and the potential wells 42, 44, 46 and 48. Charges are indicated in FIG. 6 as shaded lines. By lowering the pulse source voltage to zero volts, a large overdrive condition is created which rapidly fills the potential wells 42, 44, 46 and 48 with charge, as indicated in FIG. 6 at t2. At time t3, after the wells have been filled, the charge injection pulse is again raised to +8 volts which now causes the pulse sources 15 and 17 to act as drains which attract all charges in the depletion wells 42, 44, 46 and 48 above the barrier level produced by depletion wells 58, as indicated in t3 of FIG.

2. After all excess charges have been drained into the pulse sources 15 and 17, the word pulse voltage is lowered to -2.0 volts to very securely trap the remaining charges in the wells 42, 44, 46 and 48. It can be seen in t3 of FIG. 6 that very little, if any, charge remains in the potential wells 44 and 48, which represent 1 bit of information, since these wells are at substantially the same potential as potential wells 58, both being produced by the +4.5 volts applied to the dual insulation medium 20, 22. Furthermore, the wells 42, 44, 46 and 48 are now isolated and the bit pulse voltage is returned to 8.5 volts with relatively large puddles or packets of charge remaining in depletion wells 42 and 46, and little or no charge being stored in depletion wells 44 and 48, as shown at t4 in FIG. 6. It should be noted from FIG. 7 that when a 0 bit of information is to be written into a cell the bit pulse voltage simply remains at the rest potential of +8.5 volts. During the read operation, the bit pulse voltage on all bit lines is floated and connected to the sense amplifiers and the charge inject pulse and the word pulse are set as indicated in FIG. 7 during times tl through t4 with the sense signal indicating on the bit lines B1, B2, B3 and B4 a relatively large positive discharge for 1 bits and little or no discharge for 0 bits.

It should also be noted that by employing pulse charge injection. the potential wells can be rapidly overdriven with charges and then the excess charges rapidly drained off into a sink. By employing this technique all wells of cells along a word line can be very precisely filled within a very short period of time irrespective of bit position and bit patterns to reduce the memory cycle without disturbing information stored in cells associated with other word lines which share the common bit lines.

It should be noted more particularly that by maintaining the word pulse voltage at -2.0 volts on all word lines except for the select word line. the cells of the other or unselected word lines are protected from the low voltage, i.e., +4.5 which may be applied to a bit line used to store a 1 bit in the selected word. Furthermore, by raising the voltage of the pulse sources to +8 volts after injecting charges into the wells, excess charges which could cause a rapid deterioration of the stored information are removed from the memory array. The deterioration could be caused by permitting the excess charges to spill into the potential wells representing 1 bit, thus decreasing the difference in amount of charge stored in 1 bit wells and in 0 bit wells.

Of course, it should be understood that since the memory utilizes dynamic cells, it must be refreshed within predetermined time intervals in include any suitable bit drivers for producing complementary voltage pulses on bit/sense lines B1L and B1R, and B2L and B2R, respectively, and may also provide any desired bias voltages to these lines.

The complementary voltage pulses applied to these bit/sense lines produce depletion wells in the semiconductor substrate 10, as indicated by dashed lines 42, 44, 46 and 48 in FIG. 8B. The depth of each of these depletion wells depends upon the magnitude of the voltage applied to the respective conductive lines 24, 26, 28 and 30. These conductive lines 24, 26, 28 and 30 along with the depletion wells and the dual insulating layers 20 and 22 form storage capacitors 50, 52. 54 and 56 of the word line W1 defined by metal line 40. Likewise, word line W2 is associated with storage capacitors similar to capacitors 50, 52, 54 and 56. The storage capacitors associated with word line W2 are located at the intersection of the conductive lines 24, 26, 28 and 30 and the metal line 41. It can be seen in FIG. 8B that the depletion wells 42 and 48 associated with storage capacitors 50 and 56 are deeper than the potential wells 44 and 46 associated with capacitors 52 and 54. respectively. It should be noted that the deeper potential wells 42 and 48 have adjacent thereto shallower wells 44 and 46, respectively. The deep well 42 and the shallower well 44 are associated with the pair of bit lines B1L and B1R, respectively, which are used to write information into and read information out of the storage capacitors 50 and 52. forming a first cell 53 of the word line W1. A second cell 55 of word line 1 has storage capacitors 54 and 56. Of course, word line 1 would have additional cells but in the interest of clarity they are not shown.

It will be assumed that when complementary voltage pulses on bit/sense lines B1L and B 1 R produce the deep well 42 at capacitor 50 and the shallower well 44 at capacitor 52 a 1 bit of information is stored in cell 53 and when a deep potential well is produced at capacitor 52 and a shallower well at capacitor 50 a 0 bit of information is stored in cell 53. As noted in cell 55 a 0 bit of information is indicated as being stored therein with the deep well being associated with the right bit/sense line B2R and the shallower well being associated with the left bit line B2L.

In order to store information in capacitors 50, 52. 54 and 56 it is necessary to introduce charges into the potential wells of these capacitors from the diffusion regions 12 and 14. To introduce charges into the depletion wells 42, 44, 46. and 48, a conductive path is selectively produced between the sources 12 and 14 and each of the depletion wells 42, 44, 46 and 48. This path is produced by creating additional depletion wells 58 at the surface of the semiconductor substrate 10 between the diffusion regions 12 and 14 and the depletion wells 42 and 48, respectively, and also between the depletion wells 42 and 44, 44 and 46, and 46 and 48. These depletion wells 58, as indicated in FIG. 1C of the drawing, are produced by a word pulse having a positive polarity applied from word driver 51 to the word line W 1. The charges flow from the diffusion regions 12 and 14 through depletion wells 58 into potential wells that are at a potential initially more positive than the potential applied to terminals 16 and 18 to form an inversion layer at the surface of the substrate 10. After depletion wells 42, 44, 46 and 48 are filled with the charges, the word pulse is terminated and the depletion wells 42, 44, 46 and 48, now forming inversion layers for inversion storage capacitors 50, 52, 54 and 56, are isolated from the charge sources 12 and 14 and from each other. The voltages on the two pairs of bit lines B1L and B1R, and B2L and B2R, representing the binary information are pulsed back to the rest potential after the word line pulse has terminated and puddles or packets of charge of two different magnitudes remain in potential wells to represent the stored binary digits. When reading the stored information from the capacitors 50, 52, 54 and 56, the bit drivers are disconnected from the bit lines B1L, B1R, and B2L and B2R and differential sense amplifiers 45 and 49 are connected between the pair of bit/sense lines B 1 C and B 1 R and the pair of bit/sense lines B2L and B2R, respectively, as is well known in the art.

In FIG. 9 there is shown a series of schematic diagrams showing charge flow from the pulsed charge sources 15 and 17 at the different time periods indicated in the pulse program of FIG. 10 which is used in the operation of the memory array of FIGS.

8A to 8C. As can be seen from the pulse program of FIG. 10, pulse sources 15 and 17 produce a charge injection pulse which is normally at +8.0 volts but is lowered to zero volts at predetermined intervals. The substrate 10 is preferably biased at -3.0 volts.

The word pulse applied selectively to word line W1 and word line W2 varies between -2.0 and +4.5 volts and each of the bit lines used to write information into the cells has a rest potential of +8.5 volts. To store a 1 bit of information in cell 53, a voltage of +8.5 volts is maintained on bit/sense line B1L and a voltage of +4.5 volts is applied to bit/sense line B1R to produce the potential wells 42 and 44, respectively. Thereafter, charge is introduced into the wells from sources 15 and 17. When information is being read from the cell 53, the bit/sense line having less charge stored therein experiences a relatively strong positive charge signal while the bit/sense line having more charge stored therein has applied thereto only a signal of substantially zero magnitude. To store a 0 bit of information in cell 53 the size of potential wells 42 and 44 is reversed, thus appearing as the wells do in cell 55 with the right well being deeper than the left well. In the differential sense amplifier 45 the signal produced for the 0 bit of information has a polarity opposite to that of the signal produced for the 1 bit of information.

Referring to FIGS. 9 and 10 in more detail. it can be seen that at time tl, when a 1 bit is being written into bit/sense lines B 1 L and B1 R, the bit pulse voltage from complementary bit driver 43 decreases to +4.5 volts for bit/sense line B1R while B1L remains at +8.5 volts, with the charge injection pulse at +8 volts, which prevents pulse sources 15 and 17 from supplying charge to the substrate 10. Furthermore, the word pulse, which is at-2.0 volts, will not produce depletion wells 58. Accordingly, as can be seen at tl in FIG. 9, depletion wells 42, 44, 46 and 48 have been formed in the substrate 10 but no charges have been introduced into these wells from pulse sources 15 and 17. At time t2 the charge injection pulse is lowered to zero volts providing a large supply of charges which flow into the potential wells 42, 44, 46 and 48 as soon as the word pulse is raised to +4.5 volts to produce the potential wells 58. The potential wells 58 provide a conductive path between the charge sources 15 and 17 and the potential wells 42, 44, 46 and 48. Charges are indicated in FIG. 9 as shaded lines. By lowering the charge injection pulse source voltage to zero volts, a large overdrive condition is created which rapidly fills the potential wells 42, 44, 46 and 48 with charge, as indicated in FIG.

9 at t2. At time t3, after the wells have been filled, the charge injection pulse is again raised to +8 volts which now causes the pulse sources 15 and 17 to act as drains which attract all charges in the depletion wells 42, 44, 46 and 48 above the barrier level produced by depletion wells 58, as indicated in t3 of FIG. 9. After all excess charges have been drained into the pulse sources 15 and 17, the word pulse voltage is lowered to -2.0 volts to very securely trap the remaining charges in the wells 42, 44, 46 and 48. It can be seen in t3 of FIG. 9 that very little, if any, charge remains in the potential wells 44 and 46 since these wells are at substantially the same potential as potential wells 58, both being produced by the +4.5 volts applied to the dual insulation medium 20. 22. Furthermore, the wells 42, 44, 46 and 48 are now isolated and the bit pulse voltage is returned to the rest potential of +8.5 volts with relatively large puddles or packets of charge remaining in depletion wells 42 and 48, and little or no charge being stored in depletion wells 44 and 46, as shown at t4 in FIG. 9. It should be noted from FIG. 10 that when a 1 bit of information is to be written into a cell the bit pulse voltage simply remains at the rest potential of +8.5 volts on the bit/sense line at the left side of the cell and the bit pulse voltage applied to the bit/sense line at the right side of the cell is lowered to +4.5 volts.

During the read operation, the bit pulse voltage on all bit lines is floated from the rest potential of +8.5 volts and the lines are connected to the differential sense amplifiers 45 and 49, and the charge injection pulse and the word pulse are set as indicated in FIG. 3 during times tl through t4 with the sense signal produced by differential sense amplifier 45 indicating a relatively large positive pulse for 1 bits of information and as indicated in FIG. 10 a relatively large negative pulse for 0 bits of information, such as that stored in cell 55.

It should be noted that when only a single storage capacitor, such as capacitor 50, is used to store information, a reference voltage having a value or magnitude approximately midway between the two possible storage signal values is used in the sense amplifier. Accordingly, in, for example, a sense amplifier utilizing a flip-flop circuit, a reference voltage of +1.5 volts would be applied to one input of the circuit with the other input having a +3.0 volts or zero volt storage signal applied thereto, depending upon the information stored. It can be seen that in one instance the differential signal is of a positive polarity and in the other instance the signal is negative. In either instance the absolute difference between the voltages applied to the inputs of the circuit is only one half the difference between the two storage or bit signals 0 and +3 volts. When using the two capacitors or nodes for one cell, the voltage from one of the capacitors is applied to one of the inputs of the sense amplifier and the voltage from the other capacitor is applied to the other input of the sense amplifier. With this arrangement, if a +3 volt signal is derived from one capacitor and a zero volt signal is derived from the other capacitor an absolute difference voltage of 3 volts is applied to the two inputs of the sense amplifier. This stronger signal is useful in many memory applications. Furthermore, this structure is symmetrical and is less sensitive to noise and tolerances.

Although a reading technique has been described hereinabove, it should be understood that other reading arrangements may be employed. For example, if desired, both of the lines of the pair of bit/sense lines may be placed at an intermediate voltage level, the lines then floated and the word pulse applied to the word line to cause a partial charge exchange between the two potential wells of the cell.

It should also be noted that since information is stored in complementary form there is an equal number of substantially empty wells, such as wells 44 and 46, and substantially filled wells, such as 42 and 46. Thus, when one bit of information in a cell is to be replaced by the other bit of binary information, for example, a 0 bit replaces a 1 bit, the charge in one of the two potential wells is simply transferred to the other well, the charge source need only supply the charge lost by leakage. These exchanging arrangements provide for rapid storing of new information into the cells. When employing the exchanging arrangements, isolation gates should be used between the array of storage cells and the charge sources.

If a direct current charge source is employed, the direct voltage applied to diffusion regions 12 and 14 should be set at approximately one volt below the cut off voltage.

This charge source can automatically replenish the charge leakage.

Of course, it should be understood that since the memory utilizes dynamic cells, it must be refreshed within predetermined time intervals in order to prevent the loss of stored information.

WHAT WE CLAIM IS: 1. An integrated semiconductor memory circuit comprising a semiconductor substrate, a dielectric medium disposed on said substrate a first conductor disposed on said dielectric medium overlying a storage node in the surface region of said substrate, means to apply a data signal to said conductor to form a depletion well at the storage node and so render it capable of storing charge a zone in the surface region of said substrate which is responsive to the application of a potential thereto to provide a charge source, the zone being spaced from said storage node. and a further conductor overlying said surface region between said charge source and said storage node and insulated from said first conductor and means to apply a control voltage to said further conductor to form a depletion layer in said surface region coupling said charge source to said storage node.

2. A memory circuit as claimed in claim 1. further comprising means to apply a bias voltage to said first conductor.

3. A memory circuit as claimed in claim 1. in which said substrate is of one conductivity type and said storage node comprises a zone of the opposite conductivity type.

4. A memory circuit as claimed in any preceding claim, further including sensing means to determine the quantity of charge stored at said storage node.

5. A memory circuit as claimed in any preceding claim, in which said substrate is of p conductivity type and the charge source zone of n + conductivity type.

6. A memory circuit as claimed in claim 5, including means to apply a constant potential to the charge source zone throughout operation of the circuit.

7. A memory circuit as claimed in claim 5, including means to apply first and second potentials alternately to the charge source zone in each period of operation of the circuit during which the charge source is coupled to the storage node.

8. A memory circuit as claimed in claim 7, in which the first and second potentials are such that the charge source releases charges to the substrate when the charge source zone is at the first potential and attracts charges from the substrate when the charge zone is at the second potential.

9. A memory circuit as claimed in claim 8, in which the means to apply a data signal to said conductor is arranged to apply such a data signal for an interval lasting both during and after such a period during which the charge source is coupled to the storage node.

10. A memory circuit as claimed in any preceding claim, comprising a plurality of first conductors disposed on said dielectric medium, each overlying and associated with an individual storage node in said surface region, means to apply data signals selectively to said first conductors to render selected ones of the storage nodes capable of storing charge representing the data signals applied to the first conductors, and in which circuit said further conductor overlies said surface region between said charge source and each of said storage nodes, application of said control voltage to said further conductor forming an inversion layer in said surface region linking said storage nodes to said charge source.

11. A memory circuit as claimed in claim 10, in which the first conductors are disposed substantially at right angles to said further conductor.

12. A memory circuit as claimed in claim 11, in which each of the first conductors overlies and is associated with a plurality of storage nodes, the circuit further comprising a plurality of charge sources and a plurality of further conductors each of the further conductors serving to couple a word of storage nodes, one associated with each of the first conductors to an individual one of the charge sources.

13. A memory circuit as claimed in claim 1, further comprising a second conductor disposed on said dielectric medium overlying a second storage node in said surface region of said substrate, the first and second storage nodes being operably associated to form a single memory cell, means to apply complementary data signals to said

**WARNING** end of DESC field may overlap start of CLMS **.

Claims (25)

**WARNING** start of CLMS field may overlap end of DESC **. charge exchange between the two potential wells of the cell. It should also be noted that since information is stored in complementary form there is an equal number of substantially empty wells, such as wells 44 and 46, and substantially filled wells, such as 42 and 46. Thus, when one bit of information in a cell is to be replaced by the other bit of binary information, for example, a 0 bit replaces a 1 bit, the charge in one of the two potential wells is simply transferred to the other well, the charge source need only supply the charge lost by leakage. These exchanging arrangements provide for rapid storing of new information into the cells. When employing the exchanging arrangements, isolation gates should be used between the array of storage cells and the charge sources. If a direct current charge source is employed, the direct voltage applied to diffusion regions 12 and 14 should be set at approximately one volt below the cut off voltage. This charge source can automatically replenish the charge leakage. Of course, it should be understood that since the memory utilizes dynamic cells, it must be refreshed within predetermined time intervals in order to prevent the loss of stored information. WHAT WE CLAIM IS:

1. An integrated semiconductor memory circuit comprising a semiconductor substrate, a dielectric medium disposed on said substrate a first conductor disposed on said dielectric medium overlying a storage node in the surface region of said substrate, means to apply a data signal to said conductor to form a depletion well at the storage node and so render it capable of storing charge a zone in the surface region of said substrate which is responsive to the application of a potential thereto to provide a charge source, the zone being spaced from said storage node. and a further conductor overlying said surface region between said charge source and said storage node and insulated from said first conductor and means to apply a control voltage to said further conductor to form a depletion layer in said surface region coupling said charge source to said storage node.

2. A memory circuit as claimed in claim 1. further comprising means to apply a bias voltage to said first conductor.

3. A memory circuit as claimed in claim 1. in which said substrate is of one conductivity type and said storage node comprises a zone of the opposite conductivity type.

4. A memory circuit as claimed in any preceding claim, further including sensing means to determine the quantity of charge stored at said storage node.

5. A memory circuit as claimed in any preceding claim, in which said substrate is of p conductivity type and the charge source zone of n + conductivity type.

6. A memory circuit as claimed in claim 5, including means to apply a constant potential to the charge source zone throughout operation of the circuit.

7. A memory circuit as claimed in claim 5, including means to apply first and second potentials alternately to the charge source zone in each period of operation of the circuit during which the charge source is coupled to the storage node.

8. A memory circuit as claimed in claim 7, in which the first and second potentials are such that the charge source releases charges to the substrate when the charge source zone is at the first potential and attracts charges from the substrate when the charge zone is at the second potential.

9. A memory circuit as claimed in claim 8, in which the means to apply a data signal to said conductor is arranged to apply such a data signal for an interval lasting both during and after such a period during which the charge source is coupled to the storage node.

10. A memory circuit as claimed in any preceding claim, comprising a plurality of first conductors disposed on said dielectric medium, each overlying and associated with an individual storage node in said surface region, means to apply data signals selectively to said first conductors to render selected ones of the storage nodes capable of storing charge representing the data signals applied to the first conductors, and in which circuit said further conductor overlies said surface region between said charge source and each of said storage nodes, application of said control voltage to said further conductor forming an inversion layer in said surface region linking said storage nodes to said charge source.

11. A memory circuit as claimed in claim 10, in which the first conductors are disposed substantially at right angles to said further conductor.

12. A memory circuit as claimed in claim 11, in which each of the first conductors overlies and is associated with a plurality of storage nodes, the circuit further comprising a plurality of charge sources and a plurality of further conductors each of the further conductors serving to couple a word of storage nodes, one associated with each of the first conductors to an individual one of the charge sources.

13. A memory circuit as claimed in claim 1, further comprising a second conductor disposed on said dielectric medium overlying a second storage node in said surface region of said substrate, the first and second storage nodes being operably associated to form a single memory cell, means to apply complementary data signals to said

first and second conductors, and in which circuit application of said control voltage to said further conductor couples said charge source simultaneously to both of said first and second storage nodes.

14. A memory circuit as claimed in claim 13, further comprising a differential sensing means coupled to said first and second storage nodes for differentially sensing charges stored on said first and second storage nodes.

15. An integrated semiconductor memory circuit comprising, a semiconductor substrate, means to apply to a given region of said substrate a first voltage to produce a source of charges and a second voltage to produce a drain for attracting charges, an insulating medium disposed on said substrate, a plurality of spaced apart conductive lines disposed on said insulating medium, a conductive control line arranged on said insulating medium and substantially orthogonal to and over, but insulated from, said plurality of conductive lines, said control line extending from said given region to each of said spaced apart conductive lines, means to apply data voltage pulses at a given time interval to said plurality of spaced apart conductive lines, and means to apply a control voltage pulse to said control line to couple said given region to each of said spaced apart conductive lines during said given time interval said given region producing charges at a first portion of said given time interval and attracting charges into said drain during a second portion of said time interval.

16. A memory circuit as claimed in claim 15, in which said data voltage applying means applies voltages of first and second magnitudes to said spaced apart conductive lines and the magnitude of said control voltage is equal to that of said first magnitude.

17. A memory circuit as claimed in claim 16. in which said data voltage means applies voltages of said second magnitude to each of said spaced apart conductive lines at a time period subsequent to the termination of said control voltage pulse.

18. A memory circuit as claimed in claim 17, further including means coupled to said plurality of spaced apart conductive lines to detect charge upon the application of said control pulse when each of said spaced apart conductive lines has applied thereto voltages of said second magnitude.

19. A memory circuit as claimed in any of claims 16 to 18. in which said control voltage pulse applying means has a first voltage magnitude to create a potential well in said substrate and a second voltage magnitude to suppress a potential well.

20. An integrated semiconductor memory circuit comprising a semiconductor substrate having a first type conductivity and a given region therein having a conductivity opposite to that of said first type conductivity, means to apply a voltage to said given region to produce a source of charges, an insulating medium disposed on said substrate, a plurality of pairs of spaced apart conductive lines disposed on said insulating medium, a conductive control line arranged on said insulating medium and substantially orthogonal to and over, but insulated from said plurality of pairs of lines, said control line extending from said source of charges, means to apply complementary data signals to each pair of said plurality of pairs of conductive lines, and means to apply a control voltage pulse to said control line to couple said source of charges to each of said spaced apart conductive lines.

21. A memory circuit as claimed in claim 20, in which the data signals applying means applies a first signal having a first given magnitude and a second signal having a second given magnitude substantially greater than said first given magnitude for producing potential wells of different depths in said semiconductor substrate.

22. A memory circuit as claimed in claim 21, further including means for selectively applying a bias voltage to each of said spaced apart lines as a rest potential during a first period of time during operation of the circuit.

23. A memory circuit as claimed in claim 22, in which said bias voltage applying means disconnects said bias voltage from said spaced apart lines to produce a floating condition on said spaced apart lines during a second period of time and said control voltage pulse means couples said charge source to said potential wells during said second period of time and further including means coupled to each pair of said plurality of pairs of conductive lines during said second period of time to differentially sense charge flowing into said potential wells.

24. A memory circuit as claimed in any of claims 20 to 23, in which the control voltage pulse applying means applies the control pulse with a magnitude equal to that of said first signal.

25. An integrated semiconductor memory circuit substantially as described with reference to Figs. 1 and 2 or Figs. 3A to 3C, or Fig. 4, or Figs. 5A to 7 or Figs. 8A to 10 of the accompanying diagrammatic drawings.