GB1572797A - High speed high density logic - Google Patents
High speed high density logic Download PDFInfo
- Publication number
- GB1572797A GB1572797A GB32076A GB32076A GB1572797A GB 1572797 A GB1572797 A GB 1572797A GB 32076 A GB32076 A GB 32076A GB 32076 A GB32076 A GB 32076A GB 1572797 A GB1572797 A GB 1572797A
- Authority
- GB
- United Kingdom
- Prior art keywords
- transistor
- base
- collector
- logic gate
- region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
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Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/082—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using bipolar transistors
- H03K19/091—Integrated injection logic or merged transistor logic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0214—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L
- H01L27/0229—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L of bipolar structures
- H01L27/0233—Integrated injection logic structures [I2L]
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/082—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using bipolar transistors
- H03K19/084—Diode-transistor logic
Description
(54) HIGH SPEED HIGH DENSITY LOGIC
(71) We, TEXAS INSTRUMENTS
LIMITED a British Company, of Manton
Lane, Bedford, do hereby declare the invention for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement: This invention relates to logic cells suitable for fabrication as semiconductor integrated circuits and methods of fabricating such semiconductor integrated circuits.
A recent advance in bipolar semiconductor integrated circuit technology is the use of an active semiconductor current source rather than the conventional voltage source and resis- tor for providing operating currents in logic gates. This technique has been applied in a number of ways to various circuit configurations to give bipolar transistor logic circuits in integrated form, of which Integrated
Injection Logic (I2L) Merged Transistor Logic (MTL) and Complementary Constant Current
Logic (C3L) are examples.
Complementary Constant Current Logic employs a conventional planar transistor having the buried layer as its collector whereas
Integrated Injection Logic and Merged Tran sistor Logic use "upside-down' transistors in which the emitters are provided by the bulk substrate material. These forms of logic are all extensions of Diode Translstor Logic, and it has been proposed to improve their speed by the use of Schottky-barrier decoding diodes and Schottky-clamped transistors. Improved speed comes from the reduced voltage excursion needed between the logic levels and because of the reduction in charge storage delay.
One problem to be overcome in the use of Schottky junctions in logic gates is that the offset potential from the decoder diodes must not exceed the barrier potential of the
Schottky clamped transistor, and this problem has so far been solved by the use of two different metals for the two types of Schottky diode, which increases the number of steps needed for the fabricatinn of such logic gates.
It is an object of the present mvention to provide a logic gate emploving Schottky junctions which is simpler to fabricate.
According to the invention a logic gate comprises a first bipolar transistor having base, collector and emitter regions, a second bipolar transistor of complementary conductivity type to the first transistor and arranged to inject carriers into the base region of the first transistor, a resistor in series with a metal- semiconductor clamp diode connected between the base and collector regions of the first transistor, and a plurality of metalsemiconductor decoder diodes connected to either the base or the collector region of the first transistor, wherein the same metal is used in both clamp and decoder diodes.
The collector region of the second cransistor may be connected to the base region of the first transistor, the base region of the second transistor mainrained at a suitable potential and charges injected from the emitter of the second transistor either by means of a potential applied to the emitter or by photo generation of hole-electron pairs.
The first transistor may be an NPN type in which case the second transistor is a PNP type, or vice-versa. The first transistor may be a conventional planar transistor having the buried layer as the collector region or the first transistor may be of inverred planar construction having the bulk substrate material or buried layer as the emitter region.
The resistor is preferably formed by a semiconductor path in semiconductor material which may be either the collector region of the first transistor or the base region of rhe first transistor. The semiconductor path forming the resistive path may be defined by depositing the metal part of a metalsemiconductor junction on either the base region of the first transistor at a position remote from the collector region or depositing the metal on the collector region of the first transistor at a position remote from the base region, thereby constraining charge carriers to flow through the bulk material of either the base or the collector region and providing resistive and diode paths in series when the base and collector regions are connected externally.
The metal-semiconductor clamp diode con nected in series with the semiconductor bulk resistor between the base and collector regions of the first transistor is arranged in the conventional manner to prevent the collector potential from falling to such a level that the forward conduction potential of the basecollector diode of the first transistor is exceeded.
The decoder diodes connected to either the base regions or the collector regions of the first transtor are also arranged convention ally in the manner of decoding diodes in diode-transistor logic gates.
The metal-semiconductor diodes all employ the same metal but the potential drop provided by the diode-resistor series combination establishes a different forward conduction characteristic for the clamp diode. The value of the resistor is adjusted so that the voltage developed across it because of the circuit current is equal to the required value of logic swing. The resistor may be formed in the epitaxial layer or an existing diffused layer or it may be formed in an additional layer which may be an ion implanted, diffused or deposited layer. The metal-semiconductor diodes may include, for example, titanium, tungsten, platinum, titanium-tungsten alloy Or aluminium or may be a combination of these metals in the metallic part of the diode structure, and aluminium may form the interconnections.
A method of fabricating a bipolar transistor logic gate comprises the steps of forming, in a semiconductor substrate material, a bipolar transistor and an island separated from the base region of the said transistor by semiconductor material of conductivity type posite that of the said base region, the island being formed of semiconductor material of the same conductivity type as the said base region, depositing on either the base or the collector region of the said transistor a plurality of metal areas in such a manner and of a metal appropriate to forming metal semiconductor diodes, the diodes being remote from the base-collector juncrion, depositing at selected positions on the surface a plurality of obm1L metal contacts adapted to provide external contacts to the logic gate and to connect one of the said diodes to the base region if the said diode is formed on the collector region and to the collector region if the said diode is formed on the base region, whereby the diode connected between collector and base of the transistor forms a clamp diode in series with a semiconductor resistance path between the transistor base and collector and the remaining diodes form decoder diodes attached to either the base or collector of the transistor, and the island forms part of a further transistor arranged to Eject carriers into the base region of the first rnsnsistor.
As logic gate is suitable for implementation in integrated form. In one embodiment a conventional planar transistor is fabricated in an epitaxial layer formed on a bulk of semiconductor material, Schottky metal contacts are introduced on the epitaxial layer at positions remote from the base and emitter regions of the transistor and one of the Schottky contacts is connected to the base region to fonn the clamp diode, the remainder of the diodes being decoder diodes connected to the collector of the transistor. In another embodiment an inverted transistor is fabricated in an epitaxial layer formed on a bulk of semiconductor material, the base region being relatively extensive, Schottky metal contacts are introduced on the base region at positions remote from the collector region and one of the Schottky contacts is connected to the collector region to form the clamp diode, the remainder of the diodes being decoder diodes connected to the base of the transistor.
Logic gates in accordance with the invention will now be described by way of example only and with reference to the accompanying drawings in which:
Figure 1 is a schematic diagram of a logic gate having Schottky decoder diodes connecred to the transistor collector and a series diode-resistor clamp;
Figure 2 is a schematic representation of the logic gate of Figure 1 in integrated form;
Figure 3 is a schematic diagram of a logic gate having Schottky decoder diodes connected to the transistor base and a series diode-resistor clamp; and
Figure 4 is a schematic representationt of the logic gate of Figure 3 in integrated form.
Referring to Figure 1, PNP transistor 8 is arranged to function as a current generator which injects charge carriers into the base terminal 2 of NPN transistor 10. Base terminal 2 may be held at a potential resent ing either a logic 1 or logic 0, and the in jected carriers may either be drawn off at terminal 2 in which case transistor 10 remains off, or they may accumulate m the base region of transistor 10 and cause the transistor to become conductive, which corresu ponds to a logic 0 condition for the gate. This condition is propagated to other dependent gates via decoder diodes 12, 13 and 14 which are fanned out to other gates. The clamp diode 11 and the resistor 9 have a forward conduction potential which is greater than that of the diodes 12, 13 and 14 but less than the forward conduction potential of the base-collector diode of transistor 1Q. This ensures that the voltage swing at the collector of transistor 10 is large enough to operate the dependent logic gates while the basecollector diode of transistor 10 is prevented from becoming forward biassed. This condition is obtained even though diodes 11, 12, 13 and 14 are made from the same materials.
Figure 2 represents schematically the integrated circuit form of Figure 1. Transistor 8 is formed by the region having terminals 3, 1 and 2 as external terminals, the contacts to the semiconductor material being non rectifylng ohmic contacts. It will be noted that the collector terminal of PNP transistor 8 and the base terminal of NPN transistor 10 are one and the same.
Schottky contacts are formed on the N-type collector material to provide diodes 11, 12, 13 and 14, and the anode of diode 11 is connected externally to the base terminal of transistor 10. The metallic part of diode 11 is deposited a short distance from the P-type base material of transistor 10 to establish a resistive path 9 between the cathode of the diode and the transistor collector. Because the same metal is used in fabricating all the diodes the number of fabrication steps is reduced in comparison with logic gates requiring differing types of diodes.
Figure 3 shows another gate configuration, the diodes being implemented in the transistor base, however, instead of the collector. Transistor 110 injects current into the base of transistor 113, and this current may be removed if any of decoder diodes 107, 108, or 109 is connected to a low potential, i.e.
logic 0. If all inputs to the decoder diodes are high then current charges accumulate in the base of transistor 113 makirg it conductive. Transistor 113 collector will normally be connected to a dependent gate.
Figure 4 represents an integrated circuit implementation of Figure 3 where a P-type island forms the emitter of transistor 110 and the adjacent N-material acts both as transistor 110 base and transistor 113 emitter.
Injected carriers from transistor 110 are either drawn off by decoder diodes 107, 108, and 109 on reaching the P-type material acting as transistor 110 collector and transistor 113 base, or they accumulate in the base causing transistor 113 to become conductive. The metal parts of diodes 107, 108, 109 and 112 are deposited on the base material of transistor 113 and diode 112 alone is connected to collector terminal 105 of transistor 113.
This establishes a semiconductor bulk resistance path in series with the diode 112 between the base and collector electrodes of transistor 113. The circuit therefore provides clamp and decoder Schottky diodes formed with the same metal but having different forward conduction characteristics.
It will be appreciated that Figures 2 and 4 are entirely diagrammatic, and in particular in Figure 2 the base contact 1 will probably be situated elsewhere, since the spacing between the two P-type regions will be quite small.
WHAT WE CLAIM IS:
1. A logic gate comprising a first bipolar transistor having base, collector, an emitter regions, a second bipolar transistor of complementary conductivity type to the first transistor and arranged to inject carriers into the base region of the first transistor, a resis r in series with a metal-semiconductor clamp diode connected between the base and collector regions of the first transistor, and a plurality of metal-semiconductor decoder diodes connerted to either the base or the collector region of the first transistor, wherein the same metal is used in both clamp and decoder diodes.
2. A logic gate as claimed in claim 1, wherein the resistor is formed by a semiconductor path in a region of the first transistor.
3. A logic gate as claimed in claim 2, wherein the semiconductor path is formed in the collector region of the first transistor.
4. A logic gate as claimed in claim 2, wherein the semiconductor path is formed in the base region of the first transistor.
5. A logic gate as claimed in any one of the preceding claims. wherein the collector region of the second transistor is connected to the base region of the first transistor.
6. A logic gate as claimed in any one of claims 1 to 5, wherein the first transistor is an
NPN type and the second transistor is a
PNP type.
7. A logic gate as claimed in any one of claims 1 to 5, wherein the first transistor is a PNP type and the second transistor is an
NPN type.
8. A logic gate as claimed in any one of
claims 1 to 7, wherein the first transistor is a planar transistor having a buried layer as the collector region.
9. A logic gate as claimed in any one of
claims 1 to 7, wherein the first transistor is a planar transistor having the bulk substrate material as the emitter region.
10. A logic gate as claimed in any one of claims 1 to 7, wherein the first transistor is a planar transistor having a buried layer as the emitter region.
11. A logic gate as claimed in any one of claims 1 to 10, wherein the resistor is formed in an epitaxial layer in which the transistors are formed.
12. A logic gate as claimed in any one of claims 1 to 10, wherein the resistor is formed in an diffused layer formed in an epitaxial layer in which the transistors are formed.
13. A logic gate as claimed in any one of claims 1 to 10, wherein the resistor is formed m a layer additional to those required for fabricating transistors.
14. A logic gate as claimed in claim 13, wherein the additional layer is an ion implanted layer.
15. A logic gate as claimed in claim 13, wherein the additional layer is a diffused layer.
**WARNING** end of DESC field may overlap start of CLMS **.
Claims (23)
1. A logic gate comprising a first bipolar transistor having base, collector, an emitter regions, a second bipolar transistor of complementary conductivity type to the first transistor and arranged to inject carriers into the base region of the first transistor, a resis r in series with a metal-semiconductor clamp diode connected between the base and collector regions of the first transistor, and a plurality of metal-semiconductor decoder diodes connerted to either the base or the collector region of the first transistor, wherein the same metal is used in both clamp and decoder diodes.
2. A logic gate as claimed in claim 1, wherein the resistor is formed by a semiconductor path in a region of the first transistor.
3. A logic gate as claimed in claim 2, wherein the semiconductor path is formed in the collector region of the first transistor.
4. A logic gate as claimed in claim 2, wherein the semiconductor path is formed in the base region of the first transistor.
5. A logic gate as claimed in any one of the preceding claims. wherein the collector region of the second transistor is connected to the base region of the first transistor.
6. A logic gate as claimed in any one of claims 1 to 5, wherein the first transistor is an
NPN type and the second transistor is a
PNP type.
7. A logic gate as claimed in any one of claims 1 to 5, wherein the first transistor is a PNP type and the second transistor is an
NPN type.
8. A logic gate as claimed in any one of
claims 1 to 7, wherein the first transistor is a planar transistor having a buried layer as the collector region.
9. A logic gate as claimed in any one of
claims 1 to 7, wherein the first transistor is a planar transistor having the bulk substrate material as the emitter region.
10. A logic gate as claimed in any one of claims 1 to 7, wherein the first transistor is a planar transistor having a buried layer as the emitter region.
11. A logic gate as claimed in any one of claims 1 to 10, wherein the resistor is formed in an epitaxial layer in which the transistors are formed.
12. A logic gate as claimed in any one of claims 1 to 10, wherein the resistor is formed in an diffused layer formed in an epitaxial layer in which the transistors are formed.
13. A logic gate as claimed in any one of claims 1 to 10, wherein the resistor is formed m a layer additional to those required for fabricating transistors.
14. A logic gate as claimed in claim 13, wherein the additional layer is an ion implanted layer.
15. A logic gate as claimed in claim 13, wherein the additional layer is a diffused layer.
16. A logic gate as claimed in claim 13,
wherein the additional layer is a deposited layer.
17. A logic gate as claimed in any one of claims 1 to 16, wherein the metal part of the metal-semiconductor diodes is titanium, or tungsten, or platinum, or titanium-tungsten alloy, or aluminium, or a combination of these metals, and aluminium forms the interconnections
18. A logic gate as claimed in any one of the preceding claims and fabricated as an integrated circuit.
19. A logic gate substantially as herein described with reference to and as illustrated by Fig. 1, or Fig. 2, or Fig. 3, or Fig. 4 of the accompanying drawings.
20. A method of fabricating a bipolar transistor logic gate comprising the steps of forming, in a semiconductor substrate material, a bipolar transistor and an island separated from the base region of the said transistor by semiconductor material of conductivity type opposite that of the said base region, the island being formed of semiconductor material of the same conductivity type as the said base region, depositing on either the base or the collector region of the said transistor a plurality of metal areas in such a manner and of a metal appropriate to forming metalsemiconductor diodes, the diodes being remote from the base-collector junction, depositing at selected positions on the surface a plurality of ohmic metal contacts arranged ro provide external contacts to the logic gate and to connect one of the said diodes to the base region if the said diode is formed on the collector region and to the collector region if the said diode is formed on the base region, whereby the diode connected between collector and base of the transistor forms a clamp diode in series with a semiconductor resistance path between the transistor base and collector and the remaining diodes form decoder diodes atrached to either the base or collector of the transistor, and the island forms part of a further transistor arranged to inject carriers into the base region of the first transistor.
21. A method of fabricating a bipolar transistor logic gate as claimed in claim 20, wherein a planar transistor is fabricated in an epitaxial layer formed on a bulk of semiconductor material, and including the steps of forming, in the said epitaxial layer. first and second islands of semiconductor material of the same conductivity type as the base region of the planar transistor, the said islands being adjacent to each other, isolating the planar transistor from the transistor formed by the two islands and the epitaxial layer, introducing Schottky metal contacts on the epitaxial layer at positions remote from the base and emitter regions of the planar transistor, connecting one of the Schottky contacts to the base regions and the second semiconductor island, and providing external contacts to the remaining Schottky contacts, the epitaxial layer in the region of the two semiconductor islands, the nutter region of the planar transistor, the base region of the planar transistor and the first semiconductor island.
22. A method of fabricating a bipolar transistor logic gate as claimed in claim 20, comprising the steps of fabricating an inverted planar transistor in an epitaxial layer formed on a bulk of semiconductor material. forming Schotiy metal contacts on the base region of the inverted planar transistor at positions remote from the collector region, connecting one of the Schottky metal contacts to the collector region to form the clamp diode, and providing external contacts to the remaining
Schottky metal contacts, the epitaxial layer, the collector region of the inverted planar transistor, and the semiconductor island.
23. A method of fabricating a bipolar tran Aster logic gate substantially as heron d scribed with reference to and as illustrated by Figs. 1 and 2, or Figs 3 and 4 of the accompanying drawings.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB32076A GB1572797A (en) | 1977-01-05 | 1977-01-05 | High speed high density logic |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB32076A GB1572797A (en) | 1977-01-05 | 1977-01-05 | High speed high density logic |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| GB1572797A true GB1572797A (en) | 1980-08-06 |
Family
ID=9702313
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB32076A Expired GB1572797A (en) | 1977-01-05 | 1977-01-05 | High speed high density logic |
Country Status (1)
| Country | Link |
|---|---|
| GB (1) | GB1572797A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4728824A (en) * | 1985-10-29 | 1988-03-01 | Thomson-Csf | Control circuit of a plurality of STL type logic cells in parallel |
| US4752701A (en) * | 1984-11-21 | 1988-06-21 | Sony Corporation | Direct coupled semiconductor logic circuit |
| US4943742A (en) * | 1985-10-03 | 1990-07-24 | Fujitsu Limited | Schottky barrier diode clamp transistor |
-
1977
- 1977-01-05 GB GB32076A patent/GB1572797A/en not_active Expired
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4752701A (en) * | 1984-11-21 | 1988-06-21 | Sony Corporation | Direct coupled semiconductor logic circuit |
| US4943742A (en) * | 1985-10-03 | 1990-07-24 | Fujitsu Limited | Schottky barrier diode clamp transistor |
| US4728824A (en) * | 1985-10-29 | 1988-03-01 | Thomson-Csf | Control circuit of a plurality of STL type logic cells in parallel |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PS | Patent sealed | ||
| PCNP | Patent ceased through non-payment of renewal fee |