GB1572489A - Television signal data slicer - Google Patents

Description

(54) TELEVISION SIGNAL DATA SLICER (71) We, PHILIPS ELECTRONIC AND ASSOCIATED INDUSTRIES LIMITED, of Abacus House, 33, Gutter Lane, London, EC2V 8AH, a British Company, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement: This invention relates to television receiver arrangements in or for use in a television transmission system of a character in which coded data pulses pertaining to alpha-numeric text or other message information are transmitted in a video signal in at least one television line in field-blanking intervals where no picture signals pertaining to normal picture information are present.

A television transmission system of the above character is described in United Kingdom patent specification No:1,370,535. A conventional television receiver for the system includes a special data acquisition circuit to extract the coded data pulses from a received video signal. The extracted coded data pulses are stored and after a plurality of frame periods an entity of related message information, for example a page of text, has been received and stored. The receiver also includes a decoding circuit for converting the stored message information into a video signal which is used to cause the display of the message information at the television receiver.

In a practical realisation of a data acquisition circuit for extracting coded data pulses from a received video signal, a difficulty that arises is to determine in the data acquisition circuit a suitable bias voltage level, relative to the received video signal level, which serves as a so-called "slicing level". Only pulse amplitudes in the received video signal which are greater than the slicing level are extracted as data pulses. It is known to provide in the data acquisition circuit a data slicer which clamps the received video signal and slices it at a fixed d.c. level, but this data-slicing technique requires the level of the received video signal to remain fairly accurately related to the fixed d.c. level at all times, which causes problems when video signals are being received from different sources. It is also known to provide in the data acquisition circuit an adaptive data-slicer in which the slicing level is set automatically mid-way between positive and negative peaks of the received video signal. Such an adaptive data-slicer eliminates the need for clamping the received video signal and is more sensitive to changes in video signal level, so that errors in data acquisition are reduced as compared with a data-slicer which uses a fixed d.c. level. However, a disadvantage with this known adaptive data-slicer is that on a blank television line in a field-blanking interval the data-slicer will set the slicing level to black level. As a result, the data slicer will produce spurious "data pulses" whenever the (black) slicing level is exceeded by random noise. Such spurious "data pulses" may correspond to an acceptable start code which could result in an unintelligible display. With a view to avoiding the above disadvantage, it has been proposed to arrange for the data acquisition circuit to receive the output from the data slicer only during the television line or lines in a fieldblanking interval which is/are allocated for the transmission of coded data pulses. One particular way of achieving this, in a system in which in each television line containing coded data pulses, there is included the same sequence of clock run-in pulses which precede the actual coded data pulses, is to detect the presence of these clock run-in pulses each time and only then to render the data acquisition circuit responsive to accept the coded data pulses that follow.

The present invention also provides an adaptive data-slicer which avoids the above disadvantage and which utilises such a sequence of clock run-in pulses in its operation, but in what is believed to be a simpler, cheaper and more reliable way.

According to the present invention there is provided, for use in a television transmission system of the character referred to in which the coded data pulses are preceded in each television line in which they occur by the same sequence of clock run-in pulses, a television receiver arrangement which is adapted to display such alpha-numeric text or other message information and which comprises an adaptive data-slicer which includes slicing level means for determining, in respect of each successive television line containing coded data pulses, a slicing level which is a function of the magnitude of only the received pulses that form the clock run-in sequence in the television line, said slicing level determining means comprising a integrator to which the received pulses forming the clock run-in sequence in a television line are applied said integrator being responsive to provide the slicing level as a function of the charge which a capacitor of the integrator acquires due to these received pulses. The integrator may include means for limiting the extent to which such a capacitor can become discharged between successive clock run-in sequences of pulses, so that a minimum slicing level always exists. This minimum level would be chosen so that noise on blank television lines in the field-blanking interval would be of insufficient magnitude to cause the data-slicer to produce spurious "data pulses" in response to such noise.

In carrying out the invention the slicing level may be arranged to be adjusted in accordance with the mean or average magnitude of the received pulses that form the clock run-in sequence in a television line, so as to tend to provide one-to-one mark/space ratio data slicing of the coded data pulses that follow in the television line.

The pulses of the clock run-in sequences can be gated to the integrator by a gating circuit which is arranged to be opened for the duration of each clock run-in sequence; for instance, by the output from a monostable circuit, which is arranged to be triggered each time by the line synchronising pulse for the television line concerned, which line sync hronising pulse is extracted or reconstituted from the received video signal.

The invention also extends to a television receiver arrangement as set forth above, embodied in a television transmission system of the character referred to. Also, a television receiver arrangement as set forth above can be adapted to display the alpha-numeric text or other message information concurrently with, or as a selectable alternative to, normal picture information.

In order that the invention may be more fully understood reference will now be made by way of example to the accompanying drawings, of which: Figure 1 is a block diagram of a television transmission system of the character referred to; Figure 2 shows explanatory waveform diagrams relating to the data pulse coding and transmission of alpha-numeric text or other message information by the system of Figure 1; Figure 3 shows diagrammatically an adaptive data-slicer for use in the television receiver arrangement of the system of Figure 1; and Figure 4 shows a circuit diagram for the data-slicer of Figure 3.

Referring to Figure 1 of the drawings, which shows diagrammatically a television transmission system of the character referred to having a television receiver arrangement for displaying selectively either a television picture which is produced from picture information in a normal broadcast or cable television video signal, or alpha-numeric text or other message information which is produced from coded data pulses which are transmitted in the video signal in vertical or field-blanking intervals thereof. The possibility can also exist for displaying such message information concurrently with a television picture, for instance as sub-titles or captions which are superimposed on the television picture.

The incoming television video signal appears at an input lead 1 of the television receiver arrangement via its front end 2 which comprises the usual amplifying, tuning, i.f. and detector circuits. The front end 2 is assumed to be coupled to a television transmitter 3 via a conventional over-air broadcast or cable transmission link 4. The transmitter 3 includes in known manner means for producing television picture information, means for producing alphanumeric text or other message information, and further means for generating the appropriate composite television video signal containing picture signals representative of the picture information, and coded data pulses representative of the message information, together with the usual synchronising, equalizing and blanking signals which are necessary for the operation of the television receiver arrangement.

For normal picture display in the television receiver arrangement, the received video signal is applied to a selector circuit 5 which includes a selector switch 6. When the switch 6 is closed, the video signal is applied to a colour decoder 7 which produces the R, G AND B component signals for the picture display, these component signals being applied via video interface circuit 8 to the red, green and blue guns of a colour cathode ray tube (C.R.T.).

Coded data pulses in the video signal representing message information do not affect the picture display because they occur in one or more lines in the field-blankin interval when there is no picture display. Of the lines occurring in the field-blanking interval, most could be used to transmit coded data pulses representing message information. However, in the experimental BBC/IBA Teletext System for which the present invention was originally conceived, it is proposed to restrict such use to lines 17/18 of even fields and lines 330/331 of odd fields of the 625 line broadcast television system used in the United Kingdom.

The video signal on the input lead 1 is also applied to a data acquisition circuit 9. It is assumed that the message information represented by the coded data pulses contained in the video signal is divided into different pages of information, and that each page is for display as a whole on the screen of the C.R.T. with the coded data pulses representing each page of information being repeated periodically with or without updating of the information. It is further assumed that each page of message information is identified by means of a unique page address code which is included in the coded data pulses and defines the page number. The television receiver arrangement includes a code selector circuit 10 which controls the particular coded data pulses that are acquired by the data acquisition circuit 9 at any time. (This control is indicated by a broad-arrow connection representing the presence of n parallel channels which form an n-bit channel link for carrying n-bits of information required for data selection - other groups of parallel channels forming multi-bit channel links in the television receiver arrangement are represented similarly as m p, q and r numbers of channels and bits of information). The acquired coded data pulses are fed from the data acquisition circuit 9 to a memory device 11 over an m-bit channel link, m bit bytes being required for each character (or other item of information) contained in the message information, where m = 7, for example.

The memory device 11 can store a complete page of message information. In a typical Telextext transmission, each page of message information would contain up to 24 rows of characters, with each row containing up to 40 characters. Thus, in order to identify the different characters of a page, it is furthermore assumed that the coded data pulses also include an address code for each character, this address code employing r bits and being fed to the memory device 11 from the data acquisition circuit 9 over an r-bit channel link.

In view of the restricted transmission time which is available for transmitting the coded data pulses representing message information, for instance, sufficient time to transmit the coded data pulses for only one character row during a television line in the field blanking interval, character data for a page of message information has to be stored row-byrow in the memory device 11 over a relatively large number of television fields. This storing character data row-by-row in the memory device 11 is under the control of the address codes received from the data acquisition circuit 9 over the r-bit channel link.

A character generator 12 of the television receiver arrangement is responsive to the character data stored in the memory device 11 to produce character generating data which can be used to derive what is effectively a new picture signal for displaying the characters represented by the stored character data. As mentioned previously, different characters can be represented by respective m-bit bytes. The bits of each byte are fed in parallel from memory device 11 to character generator 12 asp-bit bytes. A character format for characters to be displayed can be a co-ordinate matrix composed of discrete elements arranged in rows and columns, this format being derived from a "read-only" memory which serves as the character generator 12 and which provides bits of character generating data in rows and columns, one row at a time. Since the character generating data is required as a modulation of a video signal in order to produce selective bright-up of the screen of the C.R.T. to achieve character display, the character generating data is produced serially (as l's and 0's) by using a parallel-to-serial convertor 13 to convert each row of bits of data read out from the character generator 12 (e.g. a = 5) into serial form.

In order to effect character display on the screen of the C.R.T. using standard line and frame scans, the logic of the television receiver arrangement in respect of character display is so organised that for each row of characters to be displayed, all the characters of the row are built up television line-by-line television line as a whole, and the rows of characters built up in succession. It takes a number of television lines to build up one row of characters. In the first television line, character data from the memory device 11 to the character generator 12 would cause the latter to produce character generating data in respect of the first row of discrete elements for the first character of the row, then in respect of the first row of discrete elements for the second character, and so on for the successive characters of the row. In the second television line, character generating data in respect of the second row of discrete elements for each character of the row would be produced in turn, and so on for the remaining television lines concerned.

The logic of the television receiver arrangement is organised by means of a clock pulse and timing pulse chain circuit 14 which provides appropriate clock and timing pulses to the memory device 11 to the character generator 12 and to the data acquisition circuit 9. The circuit 14 is synchronised in oper ation with the scanning circuits (not shown) of the C.R.T. by line and field synchorinising pulses which are extracted from the incoming video signal by a sync. separator circuit 15.

The output from the convertor 13 is applied to a colour coder 16 which produces R', G' and B' component signals for character display, these component signals being also applied to the video interface circuits 8.

The colour coder 16 can be controlled (in a manner not shown) by selected items of the character data in the memory device 11 to provide a controlled colour character display. Of course, black-and-white picture and character display is also possible, in which event the colour decoder 7 and colour coder 16 would be omitted.

Referring now to Figure 2, waveform diagram (a) represents a television video signal for one television line which occurs in a field-blanking interval and which includes coded pulse data. In this waveform diagram the line synchronising pulse for the television line concerned is represented at 17, and the line synchronising pulse for the next television line is represented at 18. The colour burst on the television line concerned and that on the next television line, are represented at 19 and 20, respectively. Assuming the television broadcast standards for 625 - line systems as employed in the United Kingdom, the period of one television line (i.e. the period between the leading edges of successive line synchronising pulses) is 64 ,us., as indicated. Further assuming the standards adopted (experimentally at present) in the United Kingdom for information transmission by digitally coded pulses in the field-blanking interval of such a 625 - line system, then the television line shown would be line number 17 or 18 in an even field and line number 330 or 331 in an odd field. Such a television line is referred to as a television data line and can contain coded data pulses representing 360 binary bits which may be considered as 45 eight-bit bytes. The position of the coded pulse data in the data line is indicated at 21. The binary bit signalling rate is approximately 7 Mbit/s (i.e. 6.9375 + 25 parts per million), and the binary bit signalling levels are defined on a scale in which, taking black level BL as 0% and peak white level WL as 100%, the binary '0' level is 0% and the binary '1' level is 66% (ignoring tolerances).

Waveform diagram (b) of Figure 2 illus trates a possible format for coded pulse data in a television data line. As mentioned above, the binary bits representing the coded pulse data are divided up into eight-bit bytes 1,2,... 20... In accordance with the particular character of television transmission system to which the present invention obtains, the first two bytes 1 and 2 comprise a sequence of clock run-in pulses which in the present example consist of a sequence of alternating bits 10101010/10101010. The third byte 3 comprises a framing or start code, e.g.

11100100, which a television receiver arrangement has to identify before it will respond to accept message information which is contained in the remaining eight-bit bytes 4, 5..20... This identification of the framing code is effected in known manner in the television receiver arrangement of Figure 1 by the data acquisition circuit 9. However, this part of the data acquisition circuit operation is not relevant to the present invention so that it is not thought necessary to include any details of such operation in the present specification.

Waveform diagram (c) of Figure 2 illustrates in idealised form the first part of a video signal waveform for a television data line showing the sequence of clock run-in pulses CL and the sequence of pulses which comprise the framing code FR. The first few coded data pulses which represent alphanumeric characters or other message information are shown at DP. The line synchronising pulse is represented at LS and the colour burst at CB. It is the pulse sequence CL which the present invention utilises as will now be considered with reference to Figures 3 and 4.

The adaptive data-slicer which is shown diagrammatically in Figure 3 forms part of the data acquisition circuit (9-Figure 1) of the television receiver arrangement. This adaptive data-slicer comprises a comparator 22 to one input 23 of which the incoming video signal VS is applied. A second input 24 of the comparator 22 is connected to the output 25 of an integrator 26. There is thus produced at the output 27 of the comparator 22 a "magnitude adapted" version of the incoming video signal VS, the actual instantaneous magnitude of which depends on the magnitude of a comparison signal applied from the integrator output 25 to the comparator input 24. A limiter 28 has an input 29 connected to the comparator output 27 and provides amplitude limiting of the magnitude-adapted" version of the incoming video signal VS as produced at the comparator output 27. A resultant data signal DS is produced at the limiter output 30 for utilisation in the data acquisition circuit.

The magnitude of the comparison signal which is produced by the integrator 26 is determined, as follows, as a function of the magnitude of the incoming video signal VS during the period of the sequence of clock run-in pulses (CL - Figure 2c). A gate 31 has a first input 32 connected to the comparator output 27, and a second input 33 connected to the output 34 of a monostable 35. The gate 31 has an output 36 connected to an input 37 of the integrator 26, and the monostable 35 has an input 38 connected to receive the line synchronising pulses LS which are extracted from the incoming video signal by the sync.

separator circuit (15 - Figure 1). In response to each line synchronising pulse LS applied to it, the monostable 35 produces at its output 34 for the period that the following sequence of clock run-in pulses CL occurs, a gating signal which is applied to the gate input 33. During the persistance of this gating signal, the gate 31 is open so that the comparator output signal is fed via the gate 31 to the integrator 26. As a result, the comparison signal which is produced at the integrator output 25 depends for its magnitude on the magnitude of the incoming video signal VS during the period of the sequence of the clock run-in pulses CL. This magnitude of the comparison signal therefore provides a data slicing level which is corrected at the beginning of each television data line. It will be apparent that although the incoming video signal VS is applied continuously to the data acquisition circuit 9, and thus to the adaptive data-slicer, suitable gating within the data acquisition circuit using the field synchronising pulses can serve to render the adaptive data slicer operative only during the field blanking intervals so that only television data lines are dealt with by it. As will be described with reference to Figure 4, the integrator 26 can be arranged to provide a minimum magnitude of comparison signal, so that noise signals on unused television data lines are optimally below the slicing level and cannot therefore give rise to the production of spurious data pulses.

An example of a detailed circuit for the adaptive data-slicer of Figure 3 is given in Figure 4. This circuit has a comparator amplifier formed by two transistors 39 and 40 having respective collector resistors 41 and 42 and a common emitter resistor 43, these two transistors 39 and 40 being connected between earth and a positive supply line (+ve). The incoming video signal VS is applied to the base of transistor 39. The base of transistor 40 is connected to the junction of two resistors 44 and 45 which are connected in series between earth and the positive supply line (+ve). Depending on the magnitude of the voltage at the junction of the resistors 44 and 45 relative to the mag nitude of the incoming video signal voltage, transistor 40 conducts to a lesser or greater extent relative to transistor 39. The resulting data signal DS is produced at the collector of a limiter transistor 46 which has its base con nected to the collector of transistor 40 and which has its emitter-collector path connected in series with resistors 47 and 48 between earth and the positive supply line (+ve).

The voltage at the junction of the resistors 44 and 45, and thus at the base of transistor 40, varies in magnitude in dependence on the extent of conduction of a Darlington pair consisting of two transistors 49 and 50 which are arranged in an emitter-follower configuration with the emitter of transistor 49 connected to said junction, the common collector connection of the two transistors 49 and 50 connected directly to the positive supply line +ve, and the base of transistor 50 connected to one current path of a current mirror comprising two transistors 51 and 52.

This current path of the current mirror includes a transistor 53 and the other current path includes a transistor 54 which are connected as a long-tailed pair. In the current mirror, the two transistors 51 and 52 have their emitters connected via respective resistors 55 and 56 to the positive supply line +ve, their collectors connected respectively to the collectors of the transistors 53 and 54, and their bases connected together. The transistor 52 serves as the diode for the current mirror by having its base and collector strapped together.

The common emitter connection of the two transistors 53 and 54 is connected to the collector of a further transistor 57 which together with associated components forms a monostable or timing circuit which is triggered by the line synchronising pulses LS. In this timing circuit, the emitter of transistor 57 is connected via a resistor 58 to a negative supply line -ve, and its base is connected to this negative supply line -ve via a capacitor 59 and to the junction of two resistors 60 and 61 via a resistor 62 and a diode 63 connected in parallel. The two resistors 60 and 61 are connected in series between earth and the negative supply line -ve, and the collector of a transistor 64 is also connected to their junction. The emitter of this transistor 64 is connected directly to the negative supply line -ve and its base is connected to earth via a resistor 65 and to a coupling capacitor 66 via which the line synchronising pulses are applied to the base of this transistor 64. In operation of the timing circuit, transistor 64 is normally "on" and transistor 57 is normally "off". On the trailing edge of a line synchronising pulse LS, transistor 64 is turned off and the junction of resistors 60 and 61 goes positive to charge capacitor 59 quickly via diode 63 and to turn on transistor 57. The time constant of capacitors 66 and resistor 65 cause transistor 64 to turn on again after a set period. Transistor 57 then starts to turn off at a rate set mainly by the time constant of capacitor 59 and resistor 62.

In this way transistor 57 is held turned on for a period during which the sequence of clock run-in pulses occur in a television data line, being turned off gradually over a last part of this period: Thus, the current mirror is enabled for response only during each such period and thereby serves as a gate in this respect. In the current mirror, the current in the path including the transistor 53 is controlled by the conduction of this transistor.

Transistor 54 controls the current in the other current path. Its base is connected directly to earth, but the base of transistor 53 is connected to the collector of a further transistor 67 which has its emitter-collector path connected in series with two resistors 68 and 69 between the positive and negative supply lines +ve and -ve, and its base connected to the collector of the transistor 40 in the comparator amplifier. The transistor 53 conducts in response to the signal input to its base from the transistor 67. An integrator capacitor 70 connected to the current path including transistor 53 acquires a charge in accordance with the current flow in this current path. A transistor 71 has its emitter connected to the other side of the capacitor 70, this transistor 71 being biased into a particular conductive state by the connection of its base to a variable resistor 72 which is connected in series with two further resistors 73 and 74 between earth and the positive supply line +ve. The collector of transistor 71 is connected directly to the positive supply line +ve, and its emitter is connected to earth via a resistor 75. Adjustment of the resistor 72 determines a minimum data slicing level. A diode 76 connected across the capacitor 70 ensures that at least this minimum slicing level always exists by providing a control voltage at the base of transistor 50. Otherwise, the charge on the capacitor 70 determines the slicing level by providing this control voltage. This capacitor 70 is charged and discharged to a mean or average value in response to the conduction of transistor 53 which is turned on and off during the period of the sequence of clock run-in pulses in each television data line. During the remainder of a television data line, this mean or average value of charge is substantially maintained on the capacitor 70, which undergoes only a slow discharge through the Darlington pair transistors 49 and 50. Thus, coded data pulses in the remainder of the television data line are sliced at a slicing level which is determined at the beginning of each television data line in accordance with the mean or average magnitude of the pulses that form the clock run-in sequence in the television line.

WHAT WE CLAIM IS: 1. A television receiver arrangement adapted for use in a television transmission system of a character in which coded data pulses pertaining to alpha-numeric text or other message information are transmitted in a video signal in at least one television line in field-blanking intervals where no picture signals pertaining to normal picture information are present, the coded data pulses being preceded in each television line in which they occur by the same sequence of clock run-in pulses, which television receiver arrangement is adapted to display such alphanumeric text or other message information and comprises an adaptive data-slicer which includes slicing level means for determining, in respect of each successive television line containing coded data puls

Claims (9)

**WARNING** start of CLMS field may overlap end of DESC **. a period during which the sequence of clock run-in pulses occur in a television data line, being turned off gradually over a last part of this period: Thus, the current mirror is enabled for response only during each such period and thereby serves as a gate in this respect. In the current mirror, the current in the path including the transistor 53 is controlled by the conduction of this transistor. Transistor 54 controls the current in the other current path. Its base is connected directly to earth, but the base of transistor 53 is connected to the collector of a further transistor 67 which has its emitter-collector path connected in series with two resistors 68 and 69 between the positive and negative supply lines +ve and -ve, and its base connected to the collector of the transistor 40 in the comparator amplifier. The transistor 53 conducts in response to the signal input to its base from the transistor 67. An integrator capacitor 70 connected to the current path including transistor 53 acquires a charge in accordance with the current flow in this current path. A transistor 71 has its emitter connected to the other side of the capacitor 70, this transistor 71 being biased into a particular conductive state by the connection of its base to a variable resistor 72 which is connected in series with two further resistors 73 and 74 between earth and the positive supply line +ve. The collector of transistor 71 is connected directly to the positive supply line +ve, and its emitter is connected to earth via a resistor 75. Adjustment of the resistor 72 determines a minimum data slicing level. A diode 76 connected across the capacitor 70 ensures that at least this minimum slicing level always exists by providing a control voltage at the base of transistor 50. Otherwise, the charge on the capacitor 70 determines the slicing level by providing this control voltage. This capacitor 70 is charged and discharged to a mean or average value in response to the conduction of transistor 53 which is turned on and off during the period of the sequence of clock run-in pulses in each television data line. During the remainder of a television data line, this mean or average value of charge is substantially maintained on the capacitor 70, which undergoes only a slow discharge through the Darlington pair transistors 49 and 50. Thus, coded data pulses in the remainder of the television data line are sliced at a slicing level which is determined at the beginning of each television data line in accordance with the mean or average magnitude of the pulses that form the clock run-in sequence in the television line. WHAT WE CLAIM IS:

1. A television receiver arrangement adapted for use in a television transmission system of a character in which coded data pulses pertaining to alpha-numeric text or other message information are transmitted in a video signal in at least one television line in field-blanking intervals where no picture signals pertaining to normal picture information are present, the coded data pulses being preceded in each television line in which they occur by the same sequence of clock run-in pulses, which television receiver arrangement is adapted to display such alphanumeric text or other message information and comprises an adaptive data-slicer which includes slicing level means for determining, in respect of each successive television line containing coded data pulses, a slicing level which is a function of the magnitude of only the received pulses that form the clock run-in sequence in the television line, said slicing level determining means comprising an integrator to which the received pulses forming the clock run-in sequence in a television line are applied, said integrator being responsive to provide the slicing level as a function of the charge which a capacitor of the integrator acquires due to these received pulses.

2. A television receiver arrangement as claimed in Claim 1, wherein the slicing level is arranged to be adjusted in accordance with the mean or average magnitude of the received pulses that form the clock run-in sequence in a television line, so as to tend to provide one-to-one mark/space ratio data slicing of the coded data pulses that follow in the television line.

3. A television receiver arrangement as claimed in Claim 1 or Claim 2, wherein said integrator includes means for limiting the extent to which said capacitor can become discharged between successive clock run-in sequences of pulses.

4. A television receiver arrangement as claimed in Claim 2 or Claim 3, including a gating circuit which is arranged to be opened for the duration of each clock run-in sequence of pulses to gate these pulses to the integrator.

5. A television receiver arrangement as claimed in Claim 4, wherein said gating circuit is opened by the output from a monostable trigger circuit which is arranged to be triggered each time by the line synchronising pulse for the television line concerned, which line synchronising pulse is extracted or reconstituted from the received video signal.

6. A television receiver arrangement as claimed in any preceding Claim, adapted to display said alpha-numeric text or other message information concurrently with, or as a selectable alternative to, normal picture information.

7. A television receiver arrangement as claimed in any preceding Claim, embodied in a television transmission system of the character referred to.

8. A television receiver arrangement

comprising an adaptive data-slicer substantially as hereinbefore described with refer- ence to Figures 3 and 4 of the accompanying drawings.

9. A television receiver arrangement as claimed in Claim 8, embodied in a television transmission system substantially as hereinbefore described with reference to Figures 1 and 2 of the accompanying draw ings.