GB1571230A - Fault detection in electrostatographic machines - Google Patents

Description

PATENT SPECIFICATION ( 11) 1571230

s ( 21) Application No 35110/78 ( 22) Filed 14 April 1977 ó ( 62) Divided out of No1 571 229 ( 19) i ( 31) Convention Application Nos 677 111 and 677 472 ( 32) Filed 15 April 1976 in U ( 33) United States of America (US) ( 44) Complete Specification published 9 July 1980 ( 51) INT CL 3 G 03 G 15/00 ( 52) Index at acceptance B 6 C 104 1200 1211 1232 1241 1242 1249 1250 1260 WK ( 54) FAULT DETECTION IN ELECTROSTATOGRAPHIC MACHINES ( 71) We, XEROX CORPORATION of Rochester, New York State, United States of America, a Body Corporate organized under the laws of the State of New York, United States of America, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be

performed, to be particularly described in and by the following statement: 5

This invention relates to electrostatic reproduction machines and more particularly, to an improved fault detection system for such machines.

The advent of higher speeds and more complex copiers and reproduction machines has brought with it a corresponding increase in the complexity in the machine control wiring and logic While this complexity manifests itself in many 10 ways, perhaps the most onerous involves the inflexibility of the typical control logic/wiring systems For as can be appreciated, simple unsophisticated machines with relatively simple control logic and wiring can be altered and modified easily to incorporate changes, retrofits, and the like Servicing and repair of the control logic is also fairly simple On the other hand, some modern high speed machines, 15 which often include sorter, a document handler, choice of copy size, multiple paper trays, jam protection and the like have extremely complex logic systems making even the most minor changes and improvements in the control logic difficult, expensive and time consuming And servicing or repairing, the machine control logic paper handling systems, electromechanical components, etc may similarly 20 entail substantial difficulty, time and expense.

To mitigate problems of the type alluded to a programmable controller may be used, to operate the machine However, the complexity and operational speed of such machines makes the identification and handling of machine faults and malfunctions difficult For example, in the event of a paper jam, the jam must be 25 located from among a maze of paper transports Otherwise, the entire paper path must be accessed and every transport device checked, through inspection or actual operation a time consuming job, and particularly annoying in a high speed, high volume reproduction machine.

According to the present invention there is provided a reproduction system 30 comprising a plurality of copy processing components cooperable to produce copies and a controller for operating said components in accordance with a program to produce copies, said program incorporating a fault flag array each flag of said fault flag array being associated with an individual fault, plural fault sensors for detecting faults during operation of said copy processing components, each of 35 said fault sensors being associated with a predetermined one of said fault flags in said fault array, each of said fault sensors setting the fault flag associated therewith in response to detection of a fault by said sensor means to initiate scanning of said array of fault flags; means for generating a preset fault signal for each fault flag, and display means responsive to said preset fault signals to identify the fault 40 represented by any fault flag in said array that has been set.

An example of the invention will now be described with reference to the accompanying drawings in which:

Fig Ia is a schematic representation of an exemplary reproduction apparatus incorporating the control system of the present invention; 45 Fig lb shows a door alarm for the apparatus of Figure la:

Fig 2 is a vertical sectional view of the apparatus shown in Fig Ia along the image plane:

Fig 3 is a top plan view of the apparatus shown in Fig la; Fig 4 is an isometric view showing the drive train for the apparatus shown in Fig 1:

Fig 5 is an enlarged view showing details of the photoreceptor edge fadeout mechanism for the apparatus shown in Fig Ia; 5 Fig 6 is an enlarged view showing details of the developing mechanism for the apparatus shown in Fig la; Fig 7 is an enlarged view showing details of the developing mechanism drive; Fig 8 is an enlarged view showing details of the developability control for the apparatus shown in Fig la; 10 Fig 9 is an enlarged view showing details of the transfer roll support mechanism for the apparatus shown in Fig la; Fig 10 is an enlarged view showing details of the photoreceptor cleaning mechanism for the apparatus shown in Fig la; Fig 11 is an enlarged view showing details of the fuser for the apparatus shown 15 in Fig Ia; Fig 12 is a schematic view showing the paper path and sensors of the apparatus shown in Fig Ia; Fig 13 is an enlarged view showing details of the copy sorter for the apparatus shown in Fig Ia; 20 Fig 14 is a schematic view showing details of the document handler for the apparatus shown in Fig Ia; Fig 15 is a view showing details of the drive mechanism for the document handler shown in Fig 14; Fig 16 is a block diagram of the controller for the apparatus shown in Fig Ia; 25 Fig 17 is a block diagram of the controller CPU; Fig 18 a is a block diagram showing the CPU microprocessor input/output connections; Fig 18 b is a timing chart of Direct Memory Access (DMA) Read and Write cycles; 30 Fig 19 a is a logic schematic of the CPU clock; Fig 19 b is a chart illustrating the output wave form of the clock shown in Fig.

I 9 a; Fig 20 is a logic schematic of the CPU memory; Fig 21 is a logic schematic of the CPU memory ready; 35 Figs 22 a, 22 b, 22 c are logic schematics of the CPU power supply stages; Figs 23 a and 23 b comprise a block diagram of the controller I/O module; Fig 24 is a logic schematic of the nonvolatile memory power supply; Fig 25 is a block diagram of the apparatus interface and remote output connections; 40 Fig 26 is a block diagram of the CPU interface module; Fig 27 is a block diagram of the apparatus special circuits module; Fig 28 is a block diagram of the main panel interface module; Fig 29 is a block diagram of the input matrix module:

Fig 30 is a block diagram of a typical remote; 45 Fig 31 is a block diagram of the sorter remote; Fig 32 is a view of the control console for inputting copy run instructions to the apparatus shown in Fig Ia; Fig 33 is a flow chart illustrating a typical machine state; Fig 34 is a flow chart of the machine state routine; 50 Fig 35 is a view showing the event table layout; Fig 36 is a flow chart of the fault scanning routine; Fig 37 is a flow chart of the fault display routine; Fig 38 is a flow chart of the cover actuated fault display routine; Fig 39 is a flow chart of the fault find routine; 55 Fig 40 is a flow chart of the fault code digit fetch routine; Fig 41 is a flow chart of the jam scan routine; Fig 42 is a flow chart of the fault lamp control routine; Fig 43 is a flow chart of the fault status panel lamp routine; Fig 44 a, b and c is a flow chart of the non-volatile memory update routine; 60 Fig 45 is a flow chart of the byte counter update routine; and Fig 46 a, b and c is a timing chart illustrating an exemplary copy run.

Referring particularly to Figures 1-3 of the drawings, there is shown an electrostatic reproduction system, identified by numeral 10 The reproduction system 10 is divided into a main electrostatic xerographic processor 12, sorter 14, 65 I 1,571,230 document handler 16, and controller 18 Other processor, sorter and/or document handler types and constructions, and different combinations thereof may instead be envisioned.

The description of the complete reproduction machine is omitted as this machine is well known as is its operating parts Parts of the machine are described, 5 especially the sensors and operating elements as necessary to illustrate the cooperating of the controller with the reproduction machine and the operation of the subject device.

PROCESSOR Processor 12 utilizes a photoreceptor in the form of an endless photo 10 conductive belt 20 supported in generally triangular configuration by rolls 21, 22, 23 Belt supporting rolls 21, 22, 23 are in turn rotatably journaled on subframe 24.

Belt tracking switch 25 (shown in Fig 2) monitors movement of belt 20 from side to side.

Processor 12 includes a generally rectangular, horizontal transparent platen 35 15 on which each original 2 to be copied is disposed A two or four sided illumination assembly, consisting of internal reflectors 36 and flash lamps 37 (shown in Fig 2) is disposed below and along at least two sides of platen 35 To control temperatures within the illumination space, the assembly is coupled through conduit 33 with a vacuum pump 38 which is adapted to withdraw overly heated air from the space 20 The light image generated by the illumination system is projected via mirrors 39, 40 and a variable magnification lens assembly 41 onto the photoreceptive belt at the exposure station 27 Reversible motor 43 is provided to move the main lens and add on lens element that comprise the lens assembly 41 to different predetermined positions and combinations to provide the preselected image sizes 25 corresponding to push button selectors 818, 819, 820 on operator module 800 (See Figure 32) Sensors 116, 117, 118 signal the present disposition of lens assembly 41.

Referring to Figs 1, 6 and 7, magnetic brush rolls 50 are provided in a developer housing 51 at developing station 28 Housing 51 is pivotally supported adjacent the lower end thereof with interlock switch 52 to sense disposition of 30 housing 51 in operative position adjacent belt 20.

To regulate development of the latent electrostatic images on belt 20, magnetic brush sleeves 55 are electrically biased A suitable power supply 60 is provided for this purpose with the amount of bias being regulated by controller 18.

Developing material is returned to the upper portion of developer housing 51 35 for reuse and is accomplished by utilizing a photocell 62 which monitors the level of developing material in housing 51 and a photocell lamp 62 ' spaced opposite to the photocell 62 in cooperative relationship therewith The disclosed machine is also provided with automatic developability control which maintains an optimum proportion of toner-to-carrier material by sensing toner concentration and 40 replenishing toner, as needed As shown in Fig 8, the automatic developability control comprises a pair of transparent plates 64 mounted in spaced, parallel arrangement in developer housing 51 such that a portion of the returning developing material passes therebetween A suitable circuit, not shown, alternately places a charge on the plate 64 to attract toner thereto Photocell 65 on one side of 45 the plate pair senses the developer material as the material passes therebetween.

Lamp 65 ' on the opposite side of plate pair 64 provides reference illumination In this arrangement, the returning developing material is alternately attracted and repelled to and from plate 64 The accumulation of toner, i e, density determines the amount of light transmitted from lamp 62 ' to photocell 62 Photocell 65 50 monitors the density of the returning developing material with the signal output therefrom being used by controller 18 to control the amount of fresh or make-up toner to be added to developer housing 51 from toner supply container 67.

To discharge toner from container 67, rotatable dispensing roll 68 is provided in the inlet to developer housing 51 Motor 69 drives roll 68 When fresh toner is 55 required, as determined by the signal from photocell 65, controller 18 actuates motor 69 to turn roll 68 for a timed interval.

Referring to Figs 4, 9, and 12, to transfer developed images from belt 20 to the copy sheets 3, a transfer roll 75 is provided To facilitate and control transfer of the developed images from belt 20 to the copy sheets 3, a suitable electrical bias is 60 applied to transfer roll 75.

To obviate the danger of copy sheets remaining on belt 20 and becoming entangled with the belt cleaning mechanism, a deflector 96 is provided upstream of cleaning brush 85 Deflector 96, which is pivotally supported on the brush housing I 1,571,230 86, is operated by solenoid 97 In the normal or off position, deflector 96 is spaced from belt 20 (the solid line position shown in the drawings) Energization of solenoid 97 pivots deflector 96 downwardly to bring the deflector leading edge into close proximity to belt 20.

Sensors 98, 99 are provided on each side of deflector 96 for sensing the 5 presence of copy material on belt 20 A signal output from upstream sensor 98 triggers solenoid 97 to pivot deflector 96 into position to intercept the copy sheet on belt 20 The signal from sensor 98 also initiates a system shutdown cycle (mis strip jam) wherein the various operating components are, within a prescribed interval, brought to a stop The interval permits any copy sheet present in fuser 150 10 to be removed, sheet trap solenoid 158 having been actuated to prevent the next copy sheet from entering fuser 150 and becoming trapped therein The signal from sensor 99, indicating failure of deflector 96 to intercept or remove the copy sheet from belt 20, triggers an immediate or hard stop (sheet on selenium jam) of the processor In this type of power to drive motor 34 is interrupted to bring belt 20 and 15 the other components driven therefrom to an immediate stop.

Referring particularly to Figures 1 and 12, copy sheets 3 comprise precut paper sheets supplied from either main or auxiliary paper trays 100, 102 Each paper tray has a platform or base 103 for supporting in stack like fashion a quantity of sheets The tray platforms 103 are supported for vertical up and down movement 20 as motors 105, 106 Side guide pairs 107, in each tray 100, 102 delimit the tray side boundaries, the guide pairs being adjustable toward and away from one another in accommodation of different size sheets Sensors 108, 109 respond to the position of each side guide pair 107, the output of sensors 108, 109 servicing to regulate operation of edge fadeout lamps 45 and fuser cooling valve 171 Lower limit 25 switches 110 on each tray prevent overtravel of the tray platform in a downward direction.

To advance the sheets 3 from either main or auxiliary tray 100, 102, main and auxiliary sheet feeders 120, 121 are provided Feeders 120, 121 each include a nudger roll 123 to engage and advance the topmost sheet in the paper tray forward 30 into the nip formed by a feed belt 124 and retard roll 125 Retard rolls 125, which are driven at an extremely low speed by motor 126, cooperate with feed belts 124 to restrict feeding of sheets from trays 100, 102 to one sheet at a time.

Feed belts 124 are driven by main and auxiliary sheet feed motors 127, 128, respectively Nudger rolls 123 are supported for pivotal movement about the axis of 35 feed belt drive shaft 129 with drive to the nudger rolls taken from drive shaft 129.

Stack height sensors 133, 134 are provided for the main and auxiliary trays, the pivoting nudger rolls 123 serving to operate sensors 133, 134 in response to the sheet stack height Main and auxiliary tray misfeed sensors 135, 136 are provided at the tray outlets 40 Main transport 140 extends from main paper tray 100 to a point slightly upstream of the nip formed by photoconductive belt 20 and transfer roll 75.

Transport 140 is driven from main motor 34 To register sheets 3 with the images developed on belt 20, sheet register fingers 141 are provided, fingers 141 being arranged to move into and out of the path of the sheets on transport 140 once each 45 revolution Registration fingers 141 are driven from main motor 34 through electromagnetic clutch 145 A timing or reset switch 146 is set once on each revolution of sheet register fingers 141 Sensor 139 monitors transport 140 for jams.

The image bearing sheets leaving the nip formed by photoconductive belt 20 and transfer roll 75 are picked off by belts 155 of the leading edge of vacuum 50 transport 149 Belts 155, which are perforated for the admission of vacuum therethrough, ride on forward roller pair 148 and rear roll 153 A pair of internal vacuum plenums 151, 154 are provided, the leading plenum 154 cooperating with belts 155 to pick up the sheets leaving the belt/transfer roll nip Transport 149 conveys the image bearing sheets to fuser 150 Vacuum conduits 147, 156 communicate 55 plenums 151, 154 with vacuum pump 152 A pressure sensor 157 monitors operation of vacuum pump 152 Sensor 144 monitors transport 149 for jams.

To prevent the sheet on transport 149 from being carried into fuser 150 in the event of a jam or malfunction, a trap solenoid 158 is provided below transport 149.

Energization of solenoid 158 raises the armature thereof into contact with the lower 60 face of plenum 154 to intercept and stop the sheet moving therepast.

To invert duplex copy sheets following fusing of the second or duplex image, a displaceable sheet stop 190 is provided adjacent the discharge end of chute 186.

Stop 190 is pivotally supported for swinging movement into and out of chute 186.

Solenoid 191 is provided to move stop 190 selectively into or out of chute 186 65 I 1,571,230 1,571,230 5 Pinch roll pairs 192 193 serve to draw the sheet trapped in chute 186 by stop 190 and carry the sheet forward onto discharge transport 181.

Output tray 195 receives unsorted copies Transport 196 a portion of which is wrapped around a turn around roll 197, serves to carry the finished copies to tray 195 Sensor 194 monitors transport 196 for jams To route copies into output tray 5 195, a deflector 198 is provided Deflector solenoid 199, when energized, turns deflector 198 to intercept sheets on conveyor 181 and route the sheets onto conveyor 196.

When output tray 195 is not used, the sheets are carried by conveyor 181 to sorter 14 10 SORTER Referring particularly to Fig 13, sorter 14 comprises upper and lower bin arrays 210, 211 Each bin array 210, 211 consists of series of spaced downwardly inclined trays 212, forming a series of individual bins 213 for receipt of finished copies 3 ' Conveyors 214 along the top of each bin array, cooperate with idler rolls 15 215 adjacent the inlet to each bin to transport the copies into juxtaposition with the bins Individual deflectors 216 at each bin cooperate when depressed, with the adjoining idler roll 215 to turn the copies into the bin associated therewith An operating solenoid 217 is provided for each deflector.

To detect entry of copies 3 ' in the individual bins 213, a photoelectric type 20 sensor 225, 226 is provided at one end of each bin array 210, 211, respectively.

Sensor lamps 225 ', 226 ' are disposed adjacent the other end of the bin array To detect the presence of copies in the bins 213, a second set of photoelectric type sensors 227, 228 is provided for each bin array on a level with tray cutout 229.

Reference lamps 227 ', 228 ' are disposed opposite sensors 227, 228 25 DOCUMENT HANDLER Referring particularly to Figs 14 and 15, document handler 16 includes a tray 233 into which originals or documents 2 to be copied are placed by the operator following which a cover (not shown) is closed A movable bail or separator 235, driven in an oscillary path from motor 236 through a solenoid operated one 30 revolution clutch 238, is provided to maintain document separation.

A document feed belt 239 is supported on drive and idler rolls 240, 241 and kicker roll 242 under tray 233, tray 233 being suitably apertured to permit the belt surface to project therewithin Feed belt 239 is driven by motor 236 through electromagnetic clutch 244 Guide 245, disposed near the discharge end of feed 35 belt 239, cooperates with belt 239 to form a nip between which the documents pass.

A photoelectric type sensor 246 is disposed adjacent the discharge end of belt 239 Sensor 246 responds on failure of a document to feed within a predetermined interval to actuate solenoid operated clutch 248 which raises kicker roll 242 and increase the surface area of feed belt 239 in contact with the documents 40 Document guides 250 route the document fed from tray 233 via roll pair 251, 252 to platen 35 Roll 251 is drivingly coupled to motor 236 through electromagnetic clutch 244 Contact of roll 251 with roll 252 turns roll 252.

Roll pair 260, 261 at the entrance to platen 35 advance the document onto platen 35, roll 260 being driven through electromagnetic clutch 262 in the forward 45 direction Contact of roll 260 with roll 261 turns roll 261 in the document feeding direction Roll 260 is selectively coupled through gearset 268 with motor 236 through electromagnetic clutch 265 so that on engagement of clutch 265 and disengagement of clutch 262, roll 260 and roll 261 therewith turn in the reverse direction to carry the document back to tray 233 One way clutches 266, 267 permit 50 free wheeling of the roll drive shafts.

The document leaving roll pair 260, 261 is carried by platen feed belt 270 onto platen 35, belt 270 being comprised of a suitable flexible material having an exterior surface of xerographic white Belt 270 is carried about drive and idler rolls 271, 272.

Roll 271 is drivingly coupled to motor 236 for rotation in either a forward or reverse 55 direction through clutches 262, 265 Engagement of clutch 262 operates through belt and pulley drive 279 to drive belt in the forward direction, engagement of clutch 265 operates through drive 279 to drive belt 270 in the reverse direction.

To locate the document in predetermined position on platen 35, a register 273 is provided at the platen inlet for engagement with the document trailing edge For 60 this purpose, control of platen belt 270 is such that following transporting of the document onto plate 35 and beyond register 273, belt 270 is reversed to carry the document backwards against register 273.

To remove the document from platen 35 following copying, register 273 is retracted to an inoperative position Solenoid 274 is provided for moving register 273.

A document deflector 275, is provided to route the document leaving platen 35 into return chute 276 For this purpose, platen belt 270 and pinch roll pair 260, 261 5 are reversed through engagement of clutch 265 Discharge roll pair 278, driven by motor 236, carry the returning document into tray 233.

To monitor movement of the documents in document handler 16 and detect jams and other malfunctions, photoelectric type sensors 246 and 280, 281 and 282 are disposed along the document routes 10 To align documents 2 returned to tray 233, a document patter 284 is provided adjacent one end of tray 233 Patter 284 is oscillated by motor 285.

To provide the requisite operational synchronization between host machine 10 and controller 18 as will appear, processor or machine clock 202 is provided.

Referring particularly to Fig 1, clock 202 comprises a toothed disc 203 drivingly 15 supported on the output shaft of main drive motor 34 A photoelectric type signal generator 204 is disposed astride the path followed by the toothed rim of disc 203, generator 204 producing, whenever drive motor 34 is energized, a pulse like signal output at a frequency correlated with the speed of motor 34, and the machine components driven therefrom 20 As described, a second machine clock, termed a pitch reset clock 138 herein, and comprising timing switch 146 is provided Switch 146 cooperates with sheet register fingers 141 to generate an output pulse once each revolution of fingers 141.

As will appear, the pulse like output of the pitch reset clock is used to reset or resynchronize controller 18 with host machine 10 25 Referring to Fig 15, a document handler clock 286 consisting of apertured disc 287 on the output shaft of document handler drive motor 236 and cooperating photoelectric type signal generator 288 is provided As in the case of machine clock 202, document handler clock 286 produces a pulse.

CONTROLLER 30 Referring to Figure 16 controller 18 includes a Computer Processor Unit (CPU) Module 500, Input/Output (I/O) Module 502, and Interface 504 Address, Data, and Control Buses 507, 508, 509, respectively, operatively couple CPU Module 500 and I/O Module 502 CPU Module 500 and I/O Module 502 are disposed within a shield 518 to prevent noise interference 35 Interface 504 couples I/O Module 502 with special circuits module 522, input matrix module 524, and main panel interface module 526 Module 504 also couples I/O Module 502 to operating sections of the machine, namely, document handler section 530, input section 532, sorter section 534 and processor sections 536, 538 A spare section 540, which may be used for monitoring operation of the host 40 machine, or which may be later utilized to control other devices, is provided.

Referring to Figures 17, 18, CPU Module 500 comprises a processor 542 such as an Intel 8080 microprocessor manufactured by Intel Corporation, Santa Clara, California, 16 K Read Only Memory (herein ROM) and 2 K Random Access Memory (herein RAM) sections 545, 546, Memory Read section 548, power 45 regulator section 550, and onboard clock 552 Bipolar tri-state buffers 510, 511 in Address and Data buses 507, 508 disable the bus on a Direct Memory Access (DMA) signal (HOLD A) as will appear While the capacity of memory sections 545, 546 are indicated throughout as being 16 K and 2 K respectively, other memory sizes may be readily contemplated 50 Referring particularly to Figure 19, clock 552 comprises a suitable clock oscillator 553 feeding a multi-bit (Qa-Qn) shift register 554 Register 554 includes an internal feedback path from one bit to the serial input of register 554 Output signal waveforms 0,, 02, 0,-1 and 02 1 are produced for use by the system.

Referring to Figure 20, the memory bytes in ROM section 545 are 55 implemented by Address signals (Ao-A 15) from processor 542, selection being effected by 3 to 8 decode chip 560 controlling chip select I (CS-1) and a 1 bit selection (A 13) controlling chip select 2 (CS-2) The most significant address bits (A 14, A 15) select the first 16 K of the total 64 K bytes of addressing space The memory bytes in RAM section 546 are implemented by Address signals (Ao-A 15) 60 through selector circuit 561 Address bit A 10 serves to select the memory bank while the remaining five most significant bits (A 11-A 15) select the last 2 K bytes out of the 64 K bytes of addressing space RAM memory section 546 includes a 40 bit output buffer 546 ', the output of which is tied together with the output from 1,571,230 ROM memory section 545 and goes to tri-state buffer 562 to drive Data bus 508.

Buffer 562 is enabled when either memory section 545 or 546 is being addressed and either a (MEM READ) or DMA (HOLD A) memory request exists An enabling signal (MEMEN) is provided from the machine control or service panel (not shown) which is used to permit disabling of buffer 562 during servicing of CPU 5 Module 500 Write control comes from either processor 542 (MEM WRITE) or from DMA (HOLD A) control Tri-state buffers 563 permit Refresh Control 605 of I/O Module 502 to access MEM READ and MEM WRITE control channels directly on a DMA signal (HOLD A) from processor 542 as will appear.

Referring to Figure 21, memory ready section 548 provides a READY signal to 10 processor 542 A binary counter 566, which is initialized by a SYNC signal ( 0,) to a prewired count as determined by input circuitry 567, counts up at a predetermined rate At the maximum count, the output at gate 568 comes true stopping the counter 566 If the cycle is a memory request (MEM REQ) and the memory location is on board as determined by the signal (MEM HERE) to tri-state buffer 15 569, a READY signal is sent to processor 542 Tri-state buffer 570 in MEM REQ line permits Refresh Control 605 of I/O Module 502 to access the MEM REQ channel directly on a DMA signal (HOLD A) from processor 542 as will appear.

Referring to Figure 22, power regulators 550, 551, 552 provide thvarious voltage levels, i e, + 5 v, 12 v, and -5 v D C required by the module 500 Each of 20 the three on board regulators 550, 551, 552 employ filtered D C inputs Power Not Normal (PNN) detection circuitry 571 is provided to reset processor 542 during the power up time Panel reset is also provided via PNN An enabling signal (INHIBIT RESET) allows completion of a write cycle in Non Volatile (N V) Memory 610 of 1/0 Module 502 25 Referring to Figs 18, 20, 21, and the DMA timing chart (Fig 18 a) data transfer from RAM section 546 to host machine 10 is effected through Direct Memory Access (DMA), as will appear To initiate DMA, a signal (HOLD) is generated by Refresh Control 605 (Fig 23 a) On acceptance, processor 542 generates a signal HOLD ACKNOWLEDGE (HOLD A) which works through tri-state buffers 510, 30 511 and through buffers 563 and 570 to release Address bus 507, Data bus 508 and MEM READ, MEM WRITE, and MEM REQ channels (Figs 20, 21) to Refresh Control 605 of I/O Module 502.

Referring to Figure 23, I/O Module 502 interfaces with CPU module 500 through bi-directional Address, Data and Control buses 507, 508, 509 I/O Module 35 502 appears to CPU Module 500 as a memory portion Data transfers between CPU and I/O modules 500, 502, and commands to I/O module 502 except for output refresh are controlled by memory reference instructions executed by CPU module 500 Output refresh which is initiated by one of several uniquely decoded memory reference commands, enables Direct Memory Access (DMA) by I/O Module 502 40 to RAM section 546.

I/O module 502 includes Matrix Input Select 604 (through which inputs from the host machine 10, are received), Refresh Control 605, Nonvolatile (NV) memory 610, Interrupt Control 612, Watch Dog Timer and Failure Flag 614 and clock 570.

A Function Decode Section 601 receives and interprets commands from CPU 45 section 500 by decoding information on address bus 507 along with control signals from processor 542 on control bus 509 On command, decode section 601 generates control signals to perform the function indicated These functions include (a) controlling tri-state buffers 620 to establish the direction of data flow in Data bus 508: (b) strobing data from Data bus 508 into buffer latches 622; (c) controlling 50 multiplexer 624 to put data from Interrupt Control 612, Real Time clock register 621, Matrix Input Select 604 or N V memory 610 onto data bus 508; (d) actuating refresh control 605 to indicate a DMA operation: (e) actuating buffers 634 to enable address bits Ao-A 7 to be sent to the host machine 10 for input matrix read operations, (f) commanding operation of Matrix Input Select 604; (g) initiating 55 read or write operation of N V memory 610 through Memory Control 638; (h) loading Real Time clock register 621 from data bus 508; and (i) resetting the Watch Dog timer or setting the Fault Failure flag 614 In addition, section 601 includes logic to control and synchronize the READY control line to CPU module 500, the READY line being used to advise module 500 when data placed on the Data Bus 60 by I/O Module 502 is valid.

Watch dog timer and failure flag 614, which serves to detect certain hardwired and software malfunctions, comprises a free running counter which under normal circumstances is periodically reset by an output refresh command (REFRESH) from Function Decode Section 601 If an output refresh command is not received 65 I 1,571,230 within a preset time interval, (i e, 25 M sec) a fault flip flop is set and a signal (FAULT) sent to the host machine 10 The signal (FAULT) also raises the HOLD line to disable CPU Module 500 Clearing of the fault flip flop may be by cycling power or generating a signal (RESET) A selector (not shown) may be provided to disable (DISABLE) the watch dog timer when desired The fault flip flop may also 5 be set by a command from the CPU Module to indicate that the operating program detected a fault.

Matrix Input Select 604 has capacity to read up to 32 groups of 8 discrete inputs from host machine 10 Lines A 2 through A 7 of Address bus 507 are routed to host machine 10 via CPU Interface Module 504 to select the desired group of 8 10 inputs The selected inputs from machine 10 are received via Input Matrix Module 524 (Fig 28) and are placed by matrix 604 onto data bus 508 and sent to CPU Module 500 via multiplexer 624 Bit selection is effected by lines A, through A 2 of Address bus 507.

Output refresh control 605, when initiated, transfers either 16 or 32 sequential 15 words from RAM memory output buffer 546 ' to host machine 10 at the predetermined clock rate in line 574 Direct Memory Access (DMA) is used to facilitate transfer of the data at a relatively high rate On a Refresh signal from Function Decode Section 601, Refresh Control 605 generates a HOLD signal to processor 542 On acknowledgement (HOLD A) processor 542 enters a hold 20 condition In this mode, CPU Module 500 releases address and data buses 507, 508 to the high impedance state giving I/O module 502 control thereover I/O module 502 then sequentially accesses the 32 memory words from output buffer 546 ' (REFRESH ADDRESS) and transfers the contents to the host machine 10 CPU Module 500 is dormant during this period 25 A control signal (LOAD) in line 607 along with the predetermined clock rate determined by the clock signal (CLOCK) in line 574 is utilized to generate eight 32 bit serial words which are transmitted serially via CPU Interface Module 504 to the host machine remote locations where serial to parallel transformation is performed Alternatively, the data may be stored in addressable latches and 30 distributed in parallel directly to the required destinations.

N.V memory 610 comprises a predetermined number of bits of non-volatile memory stored in I/O Module 502 under Memory Control 538 N V memory 610 appears to CPU module 500 as part of the CPU module memory complement and therefore may be accessed by the standard CPU memory reference instruction set 35 Referring particularly to Fig 24, to sustain the contents of N V memory 610 should system power be interrupted, one or more rechargeable batteries 635 are provided exterior to I/O module 502 CMOS protective circuitry 636 couples batteries 635 to memory 610 to preserve memory 610 on a failure of the system power A logic signal (INHIBIT RESET) prevents the CPU Module 500 from being reset during 40 the N V memory write cycle interval so that any write operation in progress will be completed before the system is shut down.

For tasks that require frequent servicing, high speed response to external events, or synchronization with the operation of host machine 10, a multiple interrupt system is provided These comprise machine based interrupts, herein 45 referred to as Pitch Reset, Machine, and Document Handler interrupts A fourth clock driven interrupt, the Real Time interrupt, is also provided.

Referring particularly to Figs 23 (b) and 34, the highest priority interrupt signal, Pitch Reset signal 640, is generated by the signal output of pitch reset clock 138 The clock signal is fed via optical isolator 645 and digital filter 646 to edge 50 trigger flip flop 647.

The second highest priority interrupt signal, machine clock signal 641, is sent directly from machine clock 202 through isolation transformer 648 to a phase locked loop 649 Loop 649, which serves as bandpath filter and signal conditioner.

sends a square wave signal to edge trigger flip flop 651 The second signal output 55 (LOCK) serves to indicate whether loop 649 is locked onto a valid signal input or not.

The third highest priority interrupt signal, Document Handler Clock signal 642, is sent directly from document handler clock 286 via isolation transformer 652 and phase locked loop 653 to flip flip 654 The signal (LOCK) serves to indicate the 60 validity of the signal input to loop 653.

The lowest priority interrupt signal, Real Time Clock signal 643, is generated by register 621 Register 621 which is loaded and stored by memory reference instructions from CPU module 500 is decremented by a clock signal in line 643 which may be derived from I/O Module clock 570 On the register count reaching 65 I 1,571,230 zero, register 621 sends an interrupt signal to edge trigger flip flop 656.

Setting of one or more of the edge trigger flip flops 647, 651, 654, 656 by the interrupt signals 640, 641, 642, 643 generates a signal (INT) via priority chip 659 to processor 542 of CPU Module 500 On acknowledgement, processor 542, issues a signal (INTA) transferring the status of the edge trigger flip flops 647, 651, 654, 656 5 to a four bit latch 660 to generate an interrupt instruction code (RESTART) onto the data bus 508.

Each interrupt is assigned a unique RESTART instruction code Should an interrupt of higher priority be triggered, a new interrupt signal (INT) and RESTART instruction code are generated resulting in a nesting of interrupt 10 software routines whenever the interrupt recognition circuitry is enabled within the CPU 500.

Priority chip 659 serves to establish a handling priority in the event of simultaneous interrupt signals in accordance with the priority schedule described.

Once triggered, the edge trigger flip flop 647, 651, 654, or 656 must be reset in 15 order to capture the next occurrence of the interrupt associated therewith Each interrupt subroutine serves, in addition to performing the functions programmed, to reset the flip flops (through the writing of a coded byte in a uniquely selected address) and to re-enable the interrupt (through execution of a reenabling instruction) Until re-enabled, initiation of a second interrupt is precluded while 20 the first interrupt is in progress.

Line 658 permit interrupt status to be interrogated by CPU module 500 on a memory reference instruction.

I/O Module 502 includes a suitable pulse generator or clock 570 for generating the various timing signals required by module 502 Clock 570 is driven by the pulse 25 like output 0, 0, of processory clock 552 (Fig 19 a) As described, clock 570 provides a reference clock pulse (in line 574) for synchronizing the output refresh data and is the source of clock pulses (in line 643) for driving Real Time register 621.

CPU interface module 504 interfaces I/O module 502 with the host machine 10 30 and transmits operating data stored in RAM section 546 to the machine Referring particularly to Fig 25 and 26, data and address information are inputted to module 504 through suitable means such as optical type couplers 700 which convert the information to single ended logic levels Data in bus 508 on a signal from Refresh Control 605 in line 607 (LOAD), is clocked into module 546 at the reference clock 35 rate in line 574 parallel by bit, serial by byte for a preset byte length, with each data bit of each successive byte being clocked into a separate data channel DOD 7 As best seen in Fig 25, each data channel DO-D 7 has an assigned output function with data channel DO being used for operating the front panel lamps 830 in the digital display, (see Fig 32), data channel Dl for special circuits module 522, and 40 remaining data channels D 2-D 7 allocated to the host machine operating sections 530, 532, 534, 536, 538 and 540 Portions of data channels Dl-D 7 have bits reserved for front panel lamps and digital display.

Since the bit capacity of the data channels D 2-D 7 is limited, a bit buffer 703 is preferably provided to catch any bit overflow in data channels D 2-D 7 45 Inasmuch as the machine output sections 530, 532, 534, 536, 538 and 540 are electrically a long distance away, i e, remote, from CPU interface module 504, and the environment is electrically "noisy", the data stream in channels D 2D 7 is transmitted to remote sections 530, 532, 534, 536, 538, and 540 via a shielded twisted pair 704 By this arrangement, induced noise appears as a differential input 50 to both lines and is rejected The associated clock signal for the data is also transmitted over line 704 with the line shield carrying the return signal currents for both data and clock signals.

Data in channel D 1 xestined for special circuits module 522 is inputted to shift register type storage circuitry 705 for transmittal to module 522 Data is also 55 inputted to main panel interface module 526 Address information in bus 507 is converted to single ended output by couplers 700 and transmitted to Input Matrix Module 524 to address host machine inputs.

CPU interface module 504 includes fault detector circuitry 706 for monitoring both faults occurring in host machine 10 and faults or failures along the buses, the 60 latter normally comprising a low voltage level or failure in one of the system power lines Machine faults may comprise a fault in CPU module 500, a belt mistrack signal from sensor 27 (see Fig 2), opening one of the machine doors or covers as responded to by conventional cover interlock sensors (not shown), a fuser over temperature as detected by sensors 175, etc In the event of a bus fault, a reset 65 I 1,571,230 signal (RESET) is generated automatically in line 709 to CPU module 500 (see Figs.

17 and 18) until the fault is removed In the event of a machine fault, a signal is generated by the CPU in line 710 to actuate a suitable relay (not shown) controlling power to all or a portion of host machine 10 A load disabling signal (LOAD DISBL) is inputted to optical couplers 700 via line 708 in the event of a fault in 5 CPU module 500 to terminate input of data to host machine 10 Other fault conditions are monitored by the software background program In the event of a fault, a signal is generated in line 711 to the digital display on control console 800 (via main panel interface module 526) signifying a fault.

Referring particularly to Figs 25 and 27, special circuits module 522 comprises 10 a collection of relatively independent circuits for either monitoring operation of and/or driving various elements of host machine 10 Module 522 incorporates suitable circuitry 712 for amplifying the output of sensors 225, 226, 227, 228, and 280, 281, 282 of sorter 14 and document handler 16 respectively; circuitry 713 for operating fuser release clutch 159; and circuitry 714 for operating main and 15 auxiliary paper tray feed roll clutches 130, 131 and document handler feed clutch 244.

Additionally, fuser detection circuitry 715 monitors temperature conditions of fuser 150 as responded to by sensor 174 On overheating of fuser 150, a signal (FUS-OT) is generated to turn heater 163 off, actuate clutch 159 to separate 20 fusing and pressure rolls 160, 161; trigger trap solenoid 158 to prevent entrance of the next copy sheet into fuser 150, and initiate a shutdown of host machine 10.

Circuitry 715 aiso cycles fuser heater 163 to maintain fuser 150 at proper operating temperatures and signals (FUS-RDUT) host machine 10 when fuser 150 is ready for operation 25 Circuitry 716 provides closed loop control over sensor 98 which responds to the presence of a copy sheet 3 on belt 20 On a signal from sensor 98, solenoid 97 is triggered to bring deflector 96 into intercepting position adjacent belt 20 At the same time, a backup timer (not shown) is actuated If the sheet is lifted from the belt 20 by deflector 96 within the time allotted, a signal from sensor 99 disables the 30 timer and a mis strip type jam condition of host machine 10 is declared and the machine is stopped If the signal from sensor 99 is not received within the allotted time, a sheet on selenium (SOS) type jam is declared and an immediate machine stop is effected.

Circuitry 718 controls the position (and hence the image reduction effected) 35 by the various optical elements that comprise main lens 41 in response to the reduction mode selected by the operator and the signal inputs from lens position responsive sensors 116, 117, 118 The signal output of circuitry 718 serves to operate lens drive motor 43 as required to place the optical elements of lens 41 in proper position to effect the image reduction programmed by the operator 40 Referring to Fig 28, input matrix module 524 provides analog gates 719 for receiving data from the various host machine sensors and inputs (i e, sheet sensors 135, 136; pressure sensor 157; etc), module 524 serving to convert the signal input to a byte oriented output for transmittal to I/O module 502 under control of Input Matrix Select 604 The byte output to module 524 is selected by address 45 information inputted on bus 507 and decoded on module 524 Conversion matrix 720, which may comprise a diode array, converts the input logic signals of "O" to logic "I" true Data from input matrix module 524 is transmitted via optical isolators 721 and Input Matrix Select 604 of I/O module 502 to CPU Module 500.

Referring particularly to Fig 29, main panel interface module 526 serves as 50 interface between CPU interface module 504 and operator control console 800 for display purposes and as interface between input matrix module 524 and the console switches As described, data channels DO-D 7 have data bits in each channel associated with the control console digital display or lamps This data is clocked into buffer circuitry 723 and from there, for digital display, data in channels 55 DI-D 7 is inputted to multiplexer 724 Multiplexer 724 selectively multiplexes the data to HEX to 7 segment converter 725 Software controlled output drivers 726 are provided for each digit which enable the proper display digit in response to the data output of converter 725 This also provides blanking control for leading zero suppression or inter digit suppression 60 Buffer circuitry 723 also enables through anode logic 728 the common digit anode drive The signal (LOAD) to latch and lamp driver control circuit 729 regulates the length of the display cycle.

For console lamps 830, data in channel DO is clocked to shift register 727 whose output is connected by drivers to the console lamps Access by input matrix 65 lo 1,571,230 module 524 to the console switches and keyboard is through main panel interface module 526.

The machine output sections 530, 532, 534, 536, 538, 540 are interfaced with I/O module 502 by CPU interface module 504 At each interrupt/refresh cycle, data is outputted to sections 530, 532, 534, 536, 538, 540 at the clock signal rate in line 5 574 over data channels D 2, D 3, D 4, D 5, D 6, D 7, respectively.

Referring to Fig 30, wherein a typical output section, i e document handler section 530 is shown, data inputted to section 530 is stored in shift register/latch circuit combination 740, 741 pending output to the individual drivers 742 associated with each machine component Preferably d c isolation between the 10 output sections is maintained by the use of transformer coupled differential outputs and inputs for both data and clock signals and a shielded twisted conductor pair.

Due to transformer coupling, the data must be restored to a d c waveform For this purpose, control recovery circuitry 744, which may comprise an inverting/noninverting digital comparator pair and output latch is provided 15 The LOAD signal serves to lockout input of data to latches 741 while new data is being clocked into shift register 740 Removal of the LOAD signal enables commutation of the fresh data to latches 741 The LOAD signal also serves to start timer 745 which imposes a maximum time limit within which a refresh period (initiated by Refresh Control 605) must occur If refresh does not occur within the 20 prescribed time limit, timer 745 generates a signal (RESET) which sets shift register 740 to zero.

With the exception of sorter section 534 discussed below, output sections 532, 536, 538, and 540 are substantially identical to document handler section 530.

Referring to Fig 31 wherein like numbers refer to like parts, to provide 25 capacity for driving the sorter deflector solenoids 221, a decode matrix arrangement consisting of a Prom encoder 750 controlling a pair of decoders 751.

752 is provided The output of decoders 751, 752 drive the sorter solenoids 221 of upper and lower bin arrays 210, 211, respectively Data is inputted to encoder 750 by means of shift register 754 30 Referring now to Fig 32, control console 800 serves to enable the operator to program host machine 10 to perform the copy run or runs desired At the same time, various indicators on console 800 reflect the operational condition of machine 10 Console 800 includes a bezel housing 802 suitably supported on host machine 10 at a convenient point with decorative front or face panel 803 on which 35 the various machine programming buttons and indicators appear Programming buttons include power on/off buttons 804, start print (PRINT) button 805, stop print (STOP) button 806 and keyboard copy quantity selector 808 A series of feature select buttons consisting of auxiliary paper tray button 810, two sided copy button 811, copy lighter button 814, and copy darker button 815, are provided 40 Additionally, image size selector buttons 818 819, 820: multiple or single document select buttons 822, 823 for operation of document handler 14: and sorter sets or stacks buttons 825, 826 are provided An on/off service selector 828 is also provided for activation during machine servicing.

Indicators comprise program display lamps 830 and displays such as READY 45 WAIT, SIDE 1, SIDE 2, ADD PAPER, CHECK STATUS PANEL, PRESS FAULT CODE QUANTITY COMPLETED, CHECK DOORS, UNLOAD AUX TRAY, CHECK DOCUMENT PATH, CHECK PAPER PATH, and UNLOAD SORTER Other display information may be envisioned.

OPERATION 50 As will appear, host machine 10 is conveniently divided into a number of operational states The machine control program is divided into Background routines and Foreground routines with operational control normally residing in the Background routine or routines appropriate to the particular machine state then in effect The output buffer 546 ' of RAM memory section 546 is used to 55 transfer/refresh control data to the various remote locations in host machine 10, control data from both Background and Foreground routines being inputted to buffer 546 ' for subsequent transmittal to host machine 10 Transmittal/refresh of control data presently in output buffer 546 ' is effected through Direct Memory Access (DMA) under the aegis of a Machine Clock interrupt routine 60 Foreground routine control data which includes a Run Event Table built in response to the particular copy run or runs programmed, is transferred to output buffer 546 ' by means of a multiple prioritized interrupt system wherein the Backgaound routine in process is temporarily interrupted while fresh Foreground 1 1 I 1,571,230 1 1 routine control data is inputted to buffer 546 ' following which the interrupted Background routine is resumed.

The operating program for host machine 10 is divided into a collection of foreground tasks, some of which are driven by the several interrupt routines and background or non-interrupt routines Foreground tasks are tasks that generally 5 require frequent servicing, high speed response, or synchronization with the host machine 10 Background routines are related to the state of host machine 10, different background routines being performed with different machine states A single background software control program (STATCHK), (TABLE I) composed of specific sub-programs associated with the principal operating states of host 10 machine 10 is provided A byte called STATE contains a number indicative of the current operating state of host machine 10 The machine STATES are as follows:

STATE NO MACHINE STATE CONTROL SUBR.

0 Software Initialize INIT I System Not Ready NRDY 2 System Ready RDY 3 Print PRINT 4 System Running, Not Print RUNNPRT Service TECHREP Referring to Figure 33, each STATE is normally divided into PROLOGUE, LOOP and EPILOGUE sections As will be evident from the exemplary program STATCHK reproduced in TABLE I, entry into a given STATE (PROLOGUE) normally causes a group of operations to be performed, these consisting of.

operations that are performed once only at the entry into the STATE For complex operations, a CALL is made to an applications subroutine therefor Relatively simpler operations (i e turning devices on or off, clearing memory, presetting memory, etc) are done directly.

Once the STATE PROLOGUE is completed, the main body (LOOP) is entered The program (STATCHK) remains in this LOOP until a change of STATE request is received and honored On a change of STATE request, the STATE EPILOGUE is entered wherein a group of operations are performed, following which the STATE moves into the PROLOGUE of the next STATE to be entered.

Referring to Fig 34 and the exemplary program (SZATCHK) in TABLE I, on actuation of the machine POWER-ON button 804, the software Initialize STATE (INIT) is entered In this STATE, the controller is initialized and a software controlled self test subroutine is entered If the self test of the controller is successfully passed, the System Not Ready STATE (NRDY) is entered If not, a fault condition is signalled.

In the System Not Ready STATE (NRDY), background subroutines are entered These include setting of Ready Flags, control registers, timers, and the like; turning on power supplies, the fuser, etc, initializing the Fault Handler, checking for paper jams (left over from a previous run), door and cover interlocks, fuser temperatures, etc During this period, the WAIT lamp on console 800 is lit and operation of host machine 10 precluded.

When all ready conditions have been checked and found acceptable, the controller moves to the System Ready State (RDY) The READY lamp on console 800 is lit and final ready checks made Host machine 10 is now ready for operation upon completion of input of a copy run program, loading of one or more originals 2 into document handler 16 (if selected by the operator), and actuation of START PRINT button 805 As will appear hereinafter, the next state is PRINT wherein the particular copy run programmed is carried out.

Following the copy run, (PRINT), the controller normally enters the System Not Ready state (NRDY) for rechecking of the ready conditions If all are satisfied, the system proceeds to the System Ready State (RDY) unless the machine is turned off by actuation of POWER OFF button 804 or a malfunction inspired shutdown is triggered The last state (TECH REP) is a machine servicing state wherein certain I 1,571,230 service routines are made available to the machine/repair personal i e, Tech Reps (Technical Representatives).

A description of the aforemention data transfer system is found in copending application 15483/77 (Serial No.

To identify faults in the diverse host machine components, the master 5 operating program for the machine 10 includes a routine for checking the condition of an array of fault flags Each flag in the array is associated with and represents a particular machine fault Signal lamps 851 (PRESS FAULT CODE), 852 (CHECK STATUS) and 853 (CHECK DOORS) are provided on control console 800 for fault identification A specific identifying code is assigned to each fault to permit the 10 fault to be pin pointed A display arrangement is provided on console 800 (Fig 32) using the copy count numerical display of the coded number A suitable chart (not shown) is provided to relate the different coded numbers with the proper machine component.

Additionally, a status panel 901, which comprises a schematic of the paper 15 feed path (see Fig Ia) is provided on the underside of transport 900, cover 900 being suitably mounted for lifting movement for access to the transport 182 therebelow as well as when viewing the status panel 901 A series of lamps 903, located at strategic points along the paper path schematic, are selectively lit to display the particular place or places in the paper path where a fault exists Raising 20 of cover 900 to expose the paper path schematic and lamps 903 is in response to lighting of signal lamp 852 (CHECK STATUS) on console 800 To provide a permanent record or history of the faults that occur during the life of host machine 10, a record is kept in non-volatile memory 610 of at least some fault occurrences.

As described earlier, sensors are associated with various of the machine 25operating components to sense the operating status of the component For example, a series of sheet jam sensors 133, 134, 139, 144, 176, 183, 179, 194 are disposed at strategic points along the path of copy sheets 3 to detect a sheet jam of other feeding failure (see Fig 12) Other sensors 280, 281 and 282 monitor document handler 16 and sensors 225, 226, sorter 14 (See Figs 14, 13) Conditions 30 within fuser 150 are responded to by detector 174 while other detectors 157 monitor pressures in the machine vacuum system (Fig 12) Sensors 98, 99 guard against the presence of sheets 3 on belt 20 following transfer (See Fig 10).

Additional sensors 910 monitor the several exterior doors and covers of host machine 10 such as transport cover 900 and door 911 to trigger an alarm should a 35 cover be open or ajar (See Fig lb) As will be understood, other sensing and monitoring devices may be provided for various operating components of host machine 10 Those shown and described herein are therefore to be considered exemplary only.

Referring particularly to Figure 36 and TABLE II, the routine for scanning the 40 array of fault flags (FLT SCAN) is initiated from time to time as part of the background program of host machine 10 Initially, paper path sensors 133, 134, 139, etc are polled to determine if a paper jam exists (JAM SCAN) in the sheet transport path The starting address of the fault array (ADDR OF FLT TBL) and the total number of fault flags to be scanned (FLT CNT) are obtained The flag 45 counter (B) is set to the total number of fault flags and fault flag counter (E) is set to zero.

Scanning of the fault flag array (SCAN) is then initiated, the first fault flag obtained, and the flag pointer (H) indexed to the next flag The flag is tested (TEST FLAG) and if set, indicating the existence of a fault, the fault counter (E) is 50 incremented A query is made as to whether readout of both code and status lamps 851 852 are required (FLT CDPL) and the particular lamp or lamps (FLT LAMP) determined.

It is understood that the code readout is obtained on numerical display 830 of control console 800 while the lamp display is obtained through the actuation of the 55 prescribed jam lamp 903 on status panel 901 of cover 900.

The flag counter (B) is decremented and the foregoing loop is repeated until the last flag of the array has been checked at which point the flag counter (B) is zero A query is made if any flags have been set (FLAGS SET), and if so, the fault signal lamp (PRESS FAULT CODE) 851 on console 800 is lit and the fault ready 60 flag reset If not, the fault code lamp is held off and the fault ready flag set The number of fault flags set are saved (FLT TOT).

When the machine operator, notified that one or more faults exist by lamp 851 (PRESS FAULT CODE) on console 800, desires to identify the fault, fault display button 850 may be depressed to produce a coded number on copy count numerical 65 i 1,571 230 display 830 If lamp 852 (CHECK STATUS) is lit, transport cover 900 may be raised to identify, by means of lamps 903, the fault condition in the sheet transport system If the fault is not in the sheet transport system, identification can be effected only by depressing fault display button 850.

The fault display (FLT DISP) subroutine shown in Fig 37 and TABLE III, 5 which is entered on depressing of fault display button 851, queries whether or not any faults exist (FLT TOT) arid if so, a check is made to determine if the fault code is already display (FLT SHOW) If not, the next fault is looked for (FLT FIND), the code for that fault (FLT DCTL) obtained, and display requested (DISPL IST).

If the fault code is already displayed and the display button 851 remains 10 depressed, the old display is continued If there are no faults (FLT TOT = 0), no display is made and the display request flags (DSPL FLT; FLT SHOW, DSPL IST) are cleared.

As long as fault display button 850 is depressed the fault code, identifying the specific fault, appears on console 800 To determine if additional faults beside the 15 one displayed exist, the operator momentarily releases button 850 When redepressed, scanning of the fault flag array for the next fault (if any) is resumed If a second fault is found, the code number for that fault is displayed If no other fault exists, the scanning loop returns to the first fault and the code for that fault is again displayed on console 800 20 Where the fault exists in the machine paper path, the code display therefor on console 800 may be fetched either by depressing fault display button 850 or raising transport cover 900.

Referring to the subroutine shown in Fig 38 and TABLE IV, where the fault consists of a jam or malfunction in the machine paper path, a check is made to 25 determine if fault display button 850 has been actuated (DSPL FLT) If so, display of the fault code is made as described heretofore in connection with Fig 36 If button 850 has not been depressed a check is made to determine if the fault is a processor jam (PROC JAM) The status of cover 900 is checked (TCVR OPEN) and whether or not a new display is requested by cover 900 (FLT CSHW) With 30 cover 900 open and a display requested, the fault flag is found (FLT CFIND) and the fault code obtained (FLT DCTL) Display of the fault code on numerical display 830 (DSPL IST) is made.

If the malfunction is confined to the area of host machine 10 other than the paper feed path, or if top cover 900 is not opened, no display (under this routine) is 35 made, and the fault flags (FLT C SHW; DSPL IST) are cleared (RESET).

In the subroutine (TABLE V) to determine which fault is to be displayed (FLT FIND), schematically shown in Fig 39 A, 39 B and on entry, a fault while loop flag (FLT WILE) is set and the address to begin searching for the next flag (FLT ADDR) obtained On entering the loop, a check is made to determine if the fault 40 pointer is at the top of the fault table (FLT TOP) If not, the fault number (FLT BCD) is obtained The fault counter is incremented (INCR A), the fault flag is obtained (GET FLAG), and the flag tested (TEST FLAG) If the flag is set, the loop control flag (FLT WILE) is reset, a check is made for the end of the fault array (FLT FLGS EQ E), and the address of the next flag (FLT ADDR) obtained In the 45 event the fault flag is not set, a check is made to determine if the flag was the last flag in the table, and the loop repeated until the last flag in the array (FLT FLGS EQ E) has been checked.

After finding the fault flag (FLT FIND), the Fault Code display loop (FLT DCTL) is entered (Fig 40, TABLE VI) In this subroutine the fault flag pointer 50 (FLT NVM), the base address of the fault table (ADDR OF FLT TBL), and the address of the display (ADDR OF DISPLAY) are fetched and the display word (FC DIGIT) obtained.

As described, on entry into the fault scan routine (FLT SCAN) a check is made to determine of a jam exists in the machine paper path For this purpose the 55 paper jam sensors 133, 134, 139, 144, 176, 183, 179 and 194 are polled for the presence of a copy sheet 3.

Referring to the schematic routine of Fig 41 and TABLE VII, the jam switch bytes (JSW BYTE) are tested and a check made to determine if any jam switch bits (JSW BITS) are set If so, the address of the first jam flag is obtained (ADDR OF 60 JAM FLAG) and the bit counter (B) set If any bits remain (B 0), the bit is obtained (GET BIT) and tested (TEST BIT) If set, the fault flag corresponding thereto is set The counter (B) is decremented and the address incremented The loop is repeated until the counter (B) reaches zero and the routine is exited.

As described, on a fault, one of the status lamps 851 (PRESS FAULT CODE), 65 I 1,571,230 852 (CHECK STATUS) and 853 (CHECK DOORS) on console 800 is lit In the lamp selection routine (FLT LAMP) of Fig 41 and TABLE VIII, a check is made to determine if the status panel flag is set (STATUS PNL FLG) If so, a check is made to determine if the fault is a processor jam (PROC JAM) and if not, the fault panel lamp routine (FLT SPNL) of Fig 43 is entered If the jam is a processor jam, 5 the routine is exited.

If the status panel flag (STATUS PNL FLAG) is not set, a doors fault (CHECK DOORS FLAG) is looked for If a door fault is found, the lamp 853 (CHECK DOORS) is turned on If no door fault exists the routine is exited.

Where the jam or malfunction lies in the sheet transport path as indicated by 10 lighting of lamp 852 (CHECK STATUS) on console 800, individual lamps 903 on status panel 901 (see Fig 1) are lit to identify the point where the fault has occurred The fault panel lamp routine (FLT SPNL) of Fig 42 and TABLE IX is entered for this purpose In this routine, checks are made to determine if the jam flags for face up tray 195, fuser 150, sheet register 146, and transport 149 are set A 15 check is made to determine if duplex copies are programmed ( 2 SDC FLAG) and if so, inverter 184, return transport 182, and auxiliary transport 147, jam checks are made If duplex copies are not programmed, and the auxiliary tray is programmed (AX FLAG), auxiliary transport 147 is checked (B-X-JAM) A check is made for a jam at belt cleaning station 86 (SOS JAM) and the routine exited 20 To provide a permanent record of the number of times various faults occur in host machine 10, a portion of non-volatile memory 610 (Fig 23 a) is set aside for this purpose Each time a selected fault occurs, i e setting of the fuser overtemperature fault flag in response to an overtemperature condition in fuser 150 as responded to by sensor 174, a counter in non-volatile memory 610 set aside for this purpose is 25 incremented by one In this way, a permanent record of the total number of times the particular fault has occurred is kept in non-volatile memory 610 and is available for various purposes such as servicing host machine 10.

In addition to recording the number of times certain faults occur, nonvolatile memory 610 is used to store the number and type of copies made on host machine 30 as will appear It is understood that the type and number of fault occurrences stored in non-volatile memory 610 may be varied as well as the type of other machine operating information, and that the listing given herein is exemplary only.

As explained heretofore, on completion of a copy run or on detection of a fault, host machine 10 comes to a stop Stopping of host machine 10 may be 35 through a cycle down procedure wherein the various operating components of machine 10 come to a stop when no longer needed, as at the completion of a copy run, or through an emergency stop wherein the various operating components are brought to a premature stop, as in the case of a fault condition Conveniently, the routine for updating information stored in non-volatile memory may be entered at 40 that time.

Referring to Fig 44 A, 44 B and 44 C and TABLE X, on entry of the nonvolatile memory updating routine (HIST FLE), the address of the nonvolatile memory counters for recording paper path jams (NVM PAPER PATH FLT CONTROLS) and the address of the paper path fault flags (PAPER PATH FLT 45 TBL FLAGS) are obtained, and a loop through the paper path fault flags entered.

Each paper path fault flag is checked and if set a counter updating subroutine (HST BCNT) is called to update the count on the non-volatile memory counter for that fault The loop is exited when the last paper path fault flag has been checked and the non-volatile memory counter therefor updated (as appropriate) 50 In a similar manner, the non-volatile memory counters for reset and error faults, fuser and cleaning (SOS) station faults, sheet registration faults, and sorter faults are updated as appropriate.

Following updating of the non-volatile memory fault counters, counters associated with the copy production of host machine 10 are updated (HST DCNT) 55 For this, the non-volatile memory counters recording the number of sheets delivered to sorter 14, to face up tray 195, and to auxiliary tray 102 (when making duplex copies) are updated, followed by updating of the counters recording the number of times flash lamps 37 are operated, both as an absolute total and as a function of simplex (side 1) or duplex (side 2) copying Following this the routine is 60 exited.

In the fault counter updating routine (HSTBCNT Fig 45 and TABLE XI), the address of the counter is fetched (FETCH NVM COUNTER LS NIBBLE), updated and stored A check is made for overflow out of the counter LS Nibble, and the counter loaded to the new count 65 I 1,571,230 1 s 16 1,571,230 16 1 In the non-volatile memory digit counter updating routine (HST DCNT TABLE XII), the current count of the counter digit breakdowns (i e units, tens, hundreds, etc) are fetched, starting with the units digit and updated An overflow check is made with provision for carrying the overflow over into the succeeding digit grouping The non-volatile memory counters are then loaded with the new 5 number and the routine exited.

It is understood that the non-volatile memory fault and digit counters may be updated in different sequences and at different times from that described and that fault and machine operating conditions other than or in addition to those described in non-volatile memory 610 10 Referring particularly to the timing chart shown in Figure 46, an exemplary copy run wherein three copies of each of two simplex or one-sided originals in duplex mode is made Referring to Fig 32, the appropriate button of copy selector 808 is set for the number of copies desired, i e 3 and document handler button 822, sorter select button 825 and two sided (duplex) button 811 depressed The originals, is in this case, two simplex or one-sided originals are loaded into tray 233 of document handler 16 (Fig 14) and the Print button 805 depressed On depression of button 805, the host machine 10 enters the PRINT state and the Run Event Table for the exemplary copy run programmed is built by controller 18 and stored in RAM section 546 As described, the Run Event Table together with Background 20 routines serve, via the multiple interrupt system and output refresh (through D.M A) to olierate the various components of host machine 10 in integrated timed relationship to produce the copies programmed.

During the run, the first original is advanced onto platen 35 by document handler 16 where, as seen in Figure 46, three exposures (IST FLASH SIDE 1) are 25 made producing three latent electrostatic images on belt 20 in succession As described earlier, the images are developed at developing station 28 and transferred to individual copy sheets fed forward (IST FEED SIDE I) from main paper tray 100 The sheets bearing the images are carried from the transfer roll/belt nip by vacuum transport 155 to fuser 150 where the images are fixed Following 30 fusing, the copy sheets are routed by deflector 184 to return transport 182 and carried to auxiliary tray 102 The image bearing sheets entering tray 102 are aligned by edge patter 187 in preparation for refeeding thereof.

Following delivery of the last copy sheet to auxiliary tray 102, the document handler 16 is activated to remove the first original from platen 35 and bring the 35 second original into registered position on platen 35 The second original is exposed three times (FLASH SIDE 2), the resulting images being developed on belt 20 at developing station 28 and transferred to the opposite or second side of the previously processed copy sheets which are now advanced (FEED SIDE 2) in timed relationship from auxiliary tray 102 Following transfer, the side two images 40 are fused by fuser 150 and routed, by gate 184 toward stop 190, the latter being raised for this purpose Abutment of the leading edge of the copy sheet with stop causes the sheet trailing edge to be guided into discharge chute 186, effectively inverting the sheet know bearing images on both sides The inverted sheet is fed onto transport 181 and into sorter 14 where the sheets are placed in successive ones 45 of the first three trays 212 of either the upper of lower arrays 210, 211 respectively depending on the disposition of deflector 220.

Other copy run programs, both simplex and duplex with and without sorter 14 and document handler 16 may be envisioned.

I,71,57123 1,571,230 TABLE I

STATE CHECKER ROUTINE (STATCHK) INITIALIZATION STATE BACKGROUND PROLOG

001 D 6 INIT: EQU INITIALIZATION STATE BACKGROUND WHILE: LOOP

001 D 6 3 A 08 FE WHILE: XBYT,STATE:,EQ,O DO INIT LOOP WHILE COND EXISTS 001 D 9 FE 00 001 DB C 2 EE 01 001 DE CDF 305 CALL SELFTEST CALL CONTROLLER SELF TEST SUBR 001 E 1 78 IF: XBYT,B,EQ,O DID CONTROLLER PASS SELF TEST 001 E 2 FE 00 001 E 4 C 2 EB 01 001 E 7 2108 FEINCBYT STATE: YES, MOVE TO NOT-READY STATE 001 EA 34 ENDIF C 3 D 601 ENDWHILE INITIALIZATION 2184 F 7 LXI A MVI 1680 MVI 78 WHILE:

FE 00 CA 0102 72 MOV 23 INX DCR C 3 F 501 ENDWHILE LOOP TO SE 3 E 80 SFLG 325 FF 4 3 E 80 SFLG 3287 F 7 3 E 80 SFLG 3234 F 4 2106 FE LXI 360 A MVI 2120 F 8 LXI XRA ADI MVI WHILE MOV INX DCR ENDWHILE LXI SHLD SFLG LXI SHLD MVI STA El SOBIT STATE BACKGROUND EPILOG

H,RDYFLGS: H&L=ADDR OF FIRST RDY FLAG B,RDYFNUM: B=NUMBER OF RDY FLAGS D,X'80 ' D-REG TO SET FLAGS XBYT,B,NE,O DO LOOP = TO # IN B-REG M,D H B ET ALL RDY FLAGS DENAB PROGRDY DSPLSEL H,DIVD 10:

M,10 H,TMRBASE:

A TIMCNTI:+TIMCNT 2:

D,1 CCZ,C M,D H A H,FLTTB L FLTADDR FLTTOP H,EVSTBY:

EVPTR:

A,X'FO' RSINTFF:

PFO$OFF SET FLAG H&L=ADDR OF NEXT FLAG DECR LOOP COUNTER SET PROG ROUTINE READY INIT PROG TO DISPLAY QTY SELECT H&L=ADDR OF 100 MSEC CNTR PRESET TO 10 H&L=ADDR OF IST 10 MSEC TIMER A=O (SET 'Z' CONDITION CODE) A=TOTAL # OF TIMERS ( 10 & 100) SET ALL TIMERS TO TERMINAL CNT WHILE # TIMERSNE O HALT THE PRESENT TIMER MOVE TO NEXT TIMER LOC DECRM LOOP CNTR (# OF TIMERS) INITIALIZE WHERE FLT HANDLER STARTS TO LOOK FOR FAULTS USED TO INITIALIZE FAULT VALUE H&L=ADDR OF STBY EVENT TABLE SAVE FOR MACH CLK ROUTINE LOAD 'RESET INTERRUPTS' DATA RESET ALL INTERRUPT FLIP-FLOPS ENABLE INTERRUPT SYSTEM TURN OFF PITCH FADE-OUT LAMP 001 EB 001 EE 001 F 1 001 F 3 001 F 5 001 F 6 001 F 8 001 FB 001 FC 001 FD 001 FE 00201 00203 00206 00208 00208 D 00210 00213 00215 00218 00219 00218 0021 D 00220 00221 00222 00223 00226 00229 0022 C 0022 E 00231 00234 00237 00239 0023 C 0023 D AF C 1601 CA 2602 72 23 3 D C 31 D 02 2121 F 7 2279 F 8 3 E 80 325 EF 4 21 CB 01 2250 F 8 2 EF O 3200 E 6 FB 21 DCFF 1,571,230 3 E 20 F 3 B 6 77 FB 2131 FF SOBIT 3 E 20 F 3 B 6 77 FB 3 E 47 STIM 322 FF 8 24 V$SPL ILKTIME,7000 TURN ON 24 VOLT SUPPLY SET BLOWER START-UP DELAY 00254 C 9 RET RETURN TO STATE CHECKER SYSTEM NOT-READY STATE BACKGROUND PROLOG

0032 C DC 5 C 03 NRDY: CALL NRDY:SSL DO SLW-SCAN BKGDAT LEAST ONCE SYSTEM NOT-READY STATE BACKGROUND WHILE: LOOP

00255 3 A 08 FE NRDY: WHILE: XBYT,STATE:,EQ,1 DO NRDY LOOP WHILE COND EXISTS FE 01 C 28002 CD 2 C 06 CALL CD 4 B 06 CD 0000 CD 0000 CD 0000 CD 0000 CD 205 CALL CALL CALL CALL CALL CALL 3 A 09 F 4 IF:

07 D 27 D 02 2108 FE INCBYT STBYBKG:

DELAY FLTDISP REDBGND SOSSUS BLKNRDY RDYTEST:

FLG,ALLRDY,T STATE:

CALL COMMON STBY BKGND SUBRIS DISPLAY FAULT CODE CONTROL LENS IN NRDY: STATE SOS JAM DETECTION BLINK THE WAIT LAMP CALL READY CONDITION TEST SUBR ARE ALL READY CONDITIONS OK YES, MOVE TO RDY STATE ENDIF C 35502 ENDWHILE SYSTEM NOT-READY STATE BACKGROUND EPILOG

21 E 9 FF COBIT WAIT$ TURN OFF WAIT LAMP 3 EFE FE A 6 77 FB C 9 RET RETURN TO STATE CHI SYSTEM READY STATE BACKGROUND PROLOG

21 E 7 FF RDY: SOBIT READY$ TURN ON READY LAMI 3 E 01 F 3 B 6 77 FB AF CFLG STRT:PRT DISALLOW PRINT UNTI CKER IL SWSK CALLS 324 EF 4 SYSTEM READY STATE BACKGROUND WHILE: LOOP

3 A 08 FE WHILE: XBYT,STATE:,EQ,2 DO RDY LOOP WHILE COND EXISTS FE 02 C 2 C 602 CD 2 C 06 CALL 002 A 2 CD 4 B 06 CALL 002 A 5 CD 0000 CALL STBYBKG:

DELAY SFTCALC CALL COMMON STBY BKGND SUB RIS CALC SHIFTED IMAGE VALUES 18 0024 D 00242 00243 00244 00245 00246 00249 0024 B 0024 C 0024 D 0024 E 0024 F 00251 00258 A D 00260 00263 00266 00269 0026 C 0026 F 00272 00275 00276 00279 0027 C 0027 D 00280 00283 00285 00286 00287 00288 00289 0028 A 0028 D 0028 F 00290 00291 00292 00293 00294 00297 0029 A 0029 C 0029 F 19 1571230 19 002 A 8 CDD 205 CALL 002 AB 2108 FE 002 AE 3 A 09 F 4 LXI IF:

RDYTEST:

H,STATE:

FLG,ALLRDY,F CALL READY CONDITION TEST SUBR H&L=ADDR OF STATE:

ARE ALL READY CONDITIONS OK MVI ELSE:

IF:

M,1 FLG,STRT:PRT,T NO, LOAD I INTO STATE: (NRDY) ALL READY CONDITIONS MET HAS 'START PRINT' BEEN PUSHED 3603 MVI M,3 YES, LOAD 3 INTO STATE:

ENDIF ENDIF C 39702 ENDWHILE SYSTEM READY STATE BACKGROUND EPILOG

21 E 7 FF COBIT READY$ TURN OFF READY LAMP 3 EFE F 3 002 CC A 6 002 CD 77 002 CE FB 002 CF C 9 002 D O AF 002 D I 47 002 D 2 2100 F 8 002 D 5 FE 20 002 D 7 D 2 E 002 002 DA 70 002 DB 23 002 DC 3 C 002 DD C 3 D 502 002 EO 3 E 80 002 E 2 3260 F 4 002 E 5 3 E 80 002 E 7 321 CF 4 002 EA AF 002 EB 3207 FE 002 EE 3205 FE 002 F 1 3 E 03 002 F 3 320 AFE 002 F 6 CDOOO( RET PRINT STATE PRINT: XRA MOV LXI WHILE:

MOV INX INR ENDWHILE SFLG SFLG XRA STA STA MVI STA ) CALL ) CALL STIM SOBIT F COBIT CFLG CFLG (PRINT) RETURN TO STATE CHECKER BACKGROUND PROLOG I

A CLR A-REG FOR USE AS CN 3 R B,A CLR B-REG (O'S INTO SHIFTREG) H,SHIFTREG H&L= START ADDR OF SHIFTREG XBYT,A,LT,32 WHILE STILL IN SR (CLR SR) M,B H A 910 DONE SRSKFLG A CYCUPCT:

SRVALU:

A,3 NOIMGCT:

SRSK TBLDPRT SYS:TIMR,800 PRNT$RLY PFO$OFF NORMDN:

SKIDLY CLR PRESENT SR LOCATION MOVE TO NEXT SR LOCATION INCRM LOOP CNTR ALLOW FIRST PITCH RESET SIGNAL NEW SR VALUE REQ'D INIT CYCLE-UP CNTR TO O INIT 'NEW SR VALUE' TO 0 INIT 'NO IMAGE CNTR' TO 3 SHIFT REG SCHEDULER (INIT SR#0) BUILD NEW PITCH TABLE INIT 'OVER-RUN EVENT' TIMER TURN ON PRINT RELAY (PRINT) TURN ON FADE-OUT LAMP CLR NORMAL SHUTDOWN REQUEST CLR SIDE I DELAY FLAG 07 DABA O 3601 C 3 C 302 3 A 4 EF 4 07 D 2 C 302 002 B I 002 B 2 002 B 5 002 B 7 002 BA 002 BD 002 BE 002 C 1 002 C 3 002 C 6 002 C 9 002 CB )000 c 51 1 F 8 ? 5 FF:

)8 DCFI DF 002 F 9 CD 002 FC 3 E.

002 FE 322 00301 21 F 00304 3 E( 00306F 3 00307 B 6 00308 77 00309FB A 21 E D 3 E 1 F F 3 00310 A 6 00311 77 00312FB 00313 AF 00314 00317 00318 3210 F 4 AF 3216 F 4 1.571 230 0031 B AF CFLG 0031 C 0031 F 00320 00323 00324 00327 00328 0032 B 0032 C 0032 F 00339 0033 C 0033 F 324 BF 7 AF 320 FF 4 AF 3249 F 7 AF 324 AF 7 AF 3207 F 4 AF CD 0000 CD 0000 CD 0000 00342 CD 0000 00345 00348 0034 B 0034 E 00350 00353 00356 00358 00358 D 00360 00363 00365 00368 0036 B 0036 C 0036 F 00370 00373 00376 00377 0037 A 0037 D 00380 00389 0038 C 0038 F 00392 00395 00398 0039 B 003 A 1 003 A 4 003 A 7 003 AA 003 AD 003 B O 003 B 3 003 B 6 003 B 9 CD 0000 CD 0000 CFLG CFLG CFLG CFLG CFLG CALL CALL CALL CALL CALL CALL CALL 1,571,230 TIMEDN:

IMGMADE:

CYCLDN:

IMEDDN:

SD 1 ITIM O CLR TIMED SHUTDOWN REQUEST FLAG CLR 1st IMAGE MADE FLAG CLR CYCLE-DOWN REQUEST FLAG CLR IMMED SHUTDOWN REQUEST FLAG CLR SIDE 1 TIME OUT FLAG PROCJAM CLEAR IN CASE THERE WAS A JAM PAPSIZE CHECK PAPER WIDTH FOR FUSER PROGUP PROG INITIALIZATION SUBR CLBKSPR COLOR BKGRD HI BIAS AT SRT PRT SETUP INITIALIZE ITEMS FOR PAPER PATH FDRPRT CHECK FEEDER SELECTION TO EDGEFB MUST BE AFTER CALL TO PAPSIZE EDGEFO DETERMINE WHICH EDGE FADE OUT PRINT STATE BACKGROUND WHILE: LOOP

3 A 08 FE WHILE: XBYT,STATE:,EQ,3 DO PRINT WHILE COND EXISTS FE 03 C 27404 3 A 07 FE IF: XBYT,CYCUPCT:,EQ,3 IS CYCLE-UP CNTR= 3 FE 03 C 26303 3 E 80 SFLG PRTPRO 2 YES, SET 'PRINT PROLOG 2 ' FLA 3220 F 4 C 37 D 03ORIF: XBYT,A,EQ,4 NO, IS CYCLE-UP CNTR= 4 FE 04 C 27 D 03 3 A 20 F 4 ANDIF: FLG,PRTPRO 2,T YES, AND IS PROLOG 2 FLAG SE' 07 D 27 D 03 AF CFLG PRTPRO 2 YES, DO PROLOG 2 AND CLR FL 3220 F 4 PRINT STATE 3 AOFF 4 IF:

07 D 27 D 03 CD 0000 CALL ENDIF ENDIF CD 0000 CALL CD 0000 CALL CD 4 B 06 CALL CD 0000 CALL CD 0000 CALL CD 0000 CALL CD 0000 CALL CD 0000 CALL CD 0000 CALL CD 0000 CALL CD 0000 CALL CD 0000 CALL CD 0000 CALL CD 0000 CALL CD 0000 CALL CD 0000 CALL CD 0000 2108 FE LXI BACKGROUND PROLOG 2

FLG,IMGMADE:,T HAS IST IMAGE BEEN MADE PROGUP SRSK PRTSWS DELAY READYCK DSPLCTL RLTIMD O FUSRDUT OILMSFD SOSJMDT MANLDN NMELVP TONDIS DVLMBJM SETJ 6 TOG FDRBKR FDRBKF 1 H,STATE:

G r T YES, CALL PROG INITIALIZATION SHIFT REG SCHEDULER SUBR PRINT SWITCH SCAN SUBR CONTROL READY LAMP IN PRINT CONTROL DIGITAL DISPLAY COMPLETE PROG PITCH EVENTS TEST FUSER FOR UNDER-TEMP STOP OIL IF MISFEED SOS PRT JAM CHECK CHECK MANUAL DN SW MONITOR MAIN TRAY IN PRINT TONER DISPENSE ROUTINE DVL OPERATION IF MISFEED CHECK JAM 6 FOR EXIT OF COPY RESET FEEDER HARDWARE 1ST SHEET FAULT DETECT (FDR) H&L= ADDR OF STATE: BYTE AG 3 A 4 AF 7IF:

07 D 2 C 703 34 INI C 34 B 04EL 3 AOAFELD 47 MC 3 A 49 F 7IF:

07 D 2 F 803 3 AOFF 4IF:

07 DADD 03 34 IN C 3 F 503OF 3 A 07 F 4 07 D 2 EE 03 78 IF:

FE 10 DAEB 03 34 IN El N C 3 F 503OF 78 FEOD DAF 503 34 IN El" C 34 B 04OF 3 A 10 F 4 07 D 20 A 04 3 AOFF 4Al 07 DAOA 04 34 IN C 34 B 0401 3 A 07 F 4 07 D 22 C 04 3 A 39 F 4IF 07 DA 2204 78 IF FE 24 DAIF 04 34 IN El C 32904EL 78 IF FE 10 DA 2904 34 IN El El C 34 B 0401 3 A 39 F 4 1,571,230 FLG,IMEDDN: T R SE:

)A )V R IF:

R NDIF RIF:

R IDIF U.F:

4 DIF:

R UIF:

R JDIF -SE:

R NDIF NDIF RIF:

M NOIMGCT:

B.A FLG CYCLDN:,T FLG,IMGMADE:,F M FLG,SD I TIMEO,T XBYT,B,GE 16 M XBYT,B,GE,13 M FLG,NORMDN:,T FLG,IMGMADE:,F M FLG,SD I TIMOT FLGADHMUTFF XBYT,B,GE,36 M XBYT,B,GE,16 M FLGADHMUTF,F IS IMMED SHUTDOWN REQUESTED YES, MOVE TO RUNNPRT: STATE IMMED SHUTDOWN NOT REQUESTED PREPARE TO TEST 'NO IMAGE CNTR' B=(NO IMAGE CNTR) IS CYCLE-DOWN REQUESTED YES HAS 1ST IMAGE BEEN MADE NO, MOVE TO RUNNPRT: STATE IS PROC MAKING SIDE I'S DUPLEX YES, WERE THERE'15 NO IMAGES YES, MOVE TO RUNNPRT: STATE WERE THERE)12 NO IMAGES YES, MOVE TO RUNNPRT: STATE IS A NORMAL SHUTDOWN REQUESTED YES, AND ARE 0 IMAGES FLASHED YES, MOVE TO RUNNPRT: STATE IS PROC MAKING SIDE I'S DUPLEX YES IS ADH IN MULT FEED MODE NO, WERE THERE)35 NO IMAGES YES, MOVE TO RUNNPRT: STATE WERE THERE> 15 NO IMAGES YES, MOVE TO RUNNPRT: STATE IS ADH NOT IN MULTIPLE FEED 003 BC 003 BF 003 C 0 003 C 3 003 C 4 003 C 7 003 CA 003 CB 003 CE 003 CF 003 D 2 003 D 5 003 D 6 003 D 9 003 DA 003 DD 003 E O 003 El 003 E 4 003 E 5 003 E 7 003 EA 003 EB 003 EE 003 EF 003 FI 003 F 4 003 F 5 003 F 8 003 FB 003 FC 003 FF 00402 00403 00406 00407 A D E 00411 00414 00415 00418 00419 00418 0041 E 0041 F 00422 00423 00425 00428 00429 0042 C 0042 F 22 1,571,230 22 00430 DA 4404 00433 3 A 38 F 4 00436 07 00437 DA 4404 0043 A78 0043 B FE 15 0043 D DA 4104 0044034 00441 00444 00445 00447 C 34 B 04 78 FEOD DA 4 B 04 ANDIF:

IF:

INR ENDIF ELSE:

IF:

FLG,ADHSINF,F XBYT,B,GE,21 M XBYT,B,GE,13 YES, AND IS IT NOT IN SINGLE NO, WERE THERE)20 NO IMAGES YES, MOVE TO RUNNPRT: STATE ADH IS SELECTED WERE THERE>)12 NO IMAGES 0044 A 34 INR M YES, MOVE TO RUNNPRT: STATE ENDIF ENDIF PRINT STATE BACKGROUND-EPILOG

0044 B 3 A 10 F 4 IF: FLG,NORMDN:,F IS NORMAL SHUTDOWN REQUESTEI 0044 E 07 0044 F DA 6304 00452 3 A 49 F 7 00455 07 00456 DA 6304 00459 3 A 16 F 4 C 07 D DA 6304 00460 C 37104 00463 3 E 02 00465 3207 FE ANDIF:

ANDIF:

ELSE:

MVI STA 00468 21 DAFF COBIT 0046 B 3 EF 7 0046 D F 3 0046 E A 6 0046 F77 00470FB 00471 C 34 B 03 00474 21 F 5 FF 00477 3 EF 7 00479F 3 0047 A A 6 0047 B77 0047 CFB 0047 D AF 0047 E 325 DF 4 00481 21 CB 01 00484 2250 F 8 00487 21 DCFF 0048 A 3 EDF 0048 C F 3 0048 D A 6 0048 E 77 0048 F FB 00490 21 EEFF 00493 3 EF 7 00495F 3 00496 A 6 00497 77 00498FB 00499 21 D 9 FF ENDIF ENDWHILE COBIT CFLG LXI SHLD COBIT COBIT FLG,CYCLDN:,F FLG,SDIDLY,F A,2 CYCUPCT:

ILLM$SPL PRNT$RLY TBLDFIN H,EVSTBY:

EVPRT:

PFO$OFF EFO$ 11 NO, IS CYCLE-DOWN REQUESTED NO, IS PROC DEAD CYCLING 1 OR BOTH COND'S REQUESTED LOAD 2 INTO CYCLE-UP CNTR TO FORCE THE CYCLE-UP MODE AGAII ILLM SPL OFF DURING DEAD CYCL TURN OFF PRINT RELAY SIGNAL NEW PITCH TABLE REQ'D H&L= ADDR STBY EVENT TABLE SAVE FOR MACH CLK ROUTINE TURN OFF FADE-OUT LAMP CLEAR 11 IN EDGE FADE-OUT LAM CLEAR 12 5 IN EDGE FADE-OUT 1,571,230 COBIT EFO$ 12 $ 5 i,571,230 0049 C 3 EF 7 0049 E F 3 0049 F A 6 004 A O 77 004 A I FB 004 A 2 CD 0000 CALL 004 A 5 CD 0000 CALL 004 A 8 21 EEFF COBIT 004 AB 3 EBF 004 AD F 3 004 AE A 6 004 AF 77 004 B O FB 004 B 1 21 F 6 FF COBIT 004 B 4 3 EBF 004 B 6 F 3 004 B 7 A 6 004 B 8 77 004 B 9 FB 004 BA 21 FOFF COBIT 004 BD 3 EDF 004 BF F 3 004 C 0 A 6 004 C 1 77004 C 2 FB 004 C 3 21 F 3 FF COBIT 004 C 6 3 EFD 004 C 8 F 3 004 C 9 A 6 004 CA 77 004 CB FB 004 CC 21 F 4 FF COBIT 004 CF 3 EFD 004 D 1 F 3 004 D 2 A 6 004 D 3 77 004 D 4 FB 004 D 5 21 FBFF COBIT 004 D 8 3 EFD 004 DA F 3 004 DB A 6 004 DC 77 004 DD FB 004 DE 21 FAFF COBIT 004 E 1 3 EFD 004 E 3 F 3 004 E 4 A 6 004 E 5 77 004 E 6 FB 004 E 7 21 DAFF COBIT FUSNTRDY SOSSTBY DTCK$EDG XER$CURR XER$LOAD AX$WT MN$WT AXFD$INT MNFD$INT ILLM$SPL TURN OFF FUSER STUFF CLEAR SOS ENABLE TURN OFF TRANSFER CIRCUIT RELEASE TRANSFER ROLL TURN OFF AUXILIARY TRAY WAIT TURN OFF MAIN TRAY WAIT TURN OFF AUXILIARY FEEDER TURN OF MAIN FEEDER TURN OFF ILLUMINATION LAMP SUPPLY 004 EA 3 EF 7 004 EC F 3 004 ED A 6 004 EE 77 004 EF FB 004 F 0 CD 0000 CALL DVLNRDY TURNS OFF DVL IFJAM 004 F 3 C 9 RET RETURN TO STATE CHECKER SYSTEM RUNNING, NOT PRINT STATE BACKGROUND WHILE: LOOP

1,571,230 3 A 08 FE FE 04 C 28805 CD 0000 CD 0000 CDOO 00 CD 0000 CD 0000 CD 0000 CD 0000 CD 0000 CD 0000 CD 0000 3 A 58 F 4 07 D 23205 3 A 6 EF 4 07 DA 3205 3 A 6 CF 4 07 DA 3205 RUNNPRT WHILE: XBYT,STATE:,EQ,4 CALL CALL CALL CALL CALL CALL CALL CALL CALL CALL IF:

ANDIF:

ANDIF:

ALL TESTS C 38505 ORIF:

3 A 59 F 4 07 D 24 A 05 3 A 6 EF 4 ANDIF:

07 DA 4 A 05 3 A 6 CF 4 ANDIF:

07 DA 4 A 05 C 38505 READYCK DSPLCTL RLTIMD O ILKCK RILKCK FUSRDUT MANLDN MNELVS DELAY SETJ 6 TOG FLG,SRTSETF,T FLG,SRTCOPY,F FLG,SRTJAM,F DO RUNNPRT WHILE COND EXISTS CONTROL READY LAMP IN RUNNPRT:

CONTROL DIGITAL DISPLAY COMPLETE PROG PITCH EVENTS TEST FUSER FOR UNDER-TEMP CHECK MANUAL DN SW MONITORS MAIN TRAY IN SDBY CHECK JAM 6 SW FOR EXIT OF COPY IS.SRT SELECTED (SETS MADE) YES, AND ARE SRT COPIES NE O YES, AND IS SRT JAM-FREE PASSED STAY IN RUNNPRT: STATE FLG,SRTSTKF,T IS SRT SELECTED (STKS MODE) FLG,SRTCOPY,F FLG,SRTJAM,F YES, AND ARE SRT COPIES,NE O YES, AND IS SRT JAM-FREE ALL TESTS PASSED STAY IN RUNNPRT: STATE ORIF: FLG,SDITIMO,T ARE SIDE I COPIES GOING TO AUX 3 A 07 F 4 07 D 25 C 05 3 AFIFF ANDIF:

00554 E 608 00556 CA 5 C 05 00559 C 38505 C 3 A 1 FF 4 F07 00560 D 27305 00563 3 A 21 F 8 00566 D 601 00568 C 27005 0056 B 3 E 01 0056 D 3208 FE 00570 C 38505 00573 3 A 0036 00576 E 610 00578 CA 8505 00578 3 El F 0057 D 3221 F 8 OBIT,RET$MOT,T YES, AND IS RETURN PATH MOTOF 01 l ALL TESTS PASSED STAY IN RUNNPRT: STATE ORIF: FLG,SYS:TIME,T HAS TIMER BEEN INITIATED (PLL IF:

TIM,SYS:TIMR,L MVI STA ENDIF ORIF:

STIM A,l STATE:

UNLOCKED LAST TIME THRU) YES, IS TIMER TIMED OUT YES, LOAD 1 INTO STATE:

*FORCING MOVE TO NRDY STATE XBYT,RIS#BYT,AND,PLL,NZ TIMER NOT USED: IS PULL LOCKEE SYS:TIMR,300 NO, SET TIMER TO 300 MSEC 004 F 4 004 F 7 004 F 9 004 FC 004 FF 00502 00505 00508 00508 E 00511 00514 00517 0051 A 0051 D 0051 E 00521 00524 00525 00528 0052 B 0052 C 0052 F 00532 00535 00536 00539 0053 C 0053 D 00540 00543 00544 00547 0054 A 0054 D 0054 E 00551 1571230 25 3 EXO SFLG SYS:TI M F SET'TIMER IN I'SE' FLAG ENDIF ENDWHILE SYSTEM RUNNING, NOT PRINT STATE BACKGROUND-EPILOG

CALL DELCK CALC COPIES DELIVERED INFO COBIT FUS$TRAP INSURE FUSER TRAP SOL OFF RET RETURN TO STATE CHECKER TECH REP STATE BACKGROUND WHILE: LOOP

TECHREP: WHILE XBYT,STATE:,EQ,5 DO TECHREP WHILE COND EXISTS CALL CALL MVI STA ENDWHILE RET ILKCK NRILKCK A,I STATE:

LOAD I INTO STATE: TO FORCE A CHANGE TO NRDY STATE RETURN TO STATE CHECKER TABLE II

SCAN FAULT FLAGS/LOOP FLTSCAN IF: FLG,PROCJAM,F CALL ENDIF LXI LDA MOV MVI MOV WHILE:

INR MOV INX RLC IF:

INR IF:

CALL ENDIF ENDIF DCR ENDWHILE IF:

JAMSCAN H,FLTTB L FLTCNT B,A E,O D,E VBYT,BNZ D A,M H CCC S E XBYTFLTCDPL,GE,D FLTLAMP B VBYT E,NZ CHECK FOR PROCESSOR JAM LOOK FOR PAPER ON SWITCHES GET STARTING ADDR OF FLAG ARRAY GET NO OF FLAGS ZERO FAULT COUNTER ZERO CASE COUNTER SCAN FLAGS INCREMENT COUNTER GET FLAG POINT TO NEXT FLAG TEST FLAG FLAG IS SET, COUNT IT ARE BOTH CODE AND LAMPS REQD DETERMINE WHICH LAMPS DECREMENT FLAG COUNT ARE ANY FLAGS SET 00580 00582 00585 00588 00588 0058 E 00590 00591 00592 00593 00594 00595 00598 0059 A 0059 D A 0 A 3 A 5 A 8 AB 3 E 80 321 FF 4 C 3 F 404 CD 0000 21 F 3 FF 3 EDF F 3 A 6 77 FB C 9 3 A 08 FE FE 05 C 2 AB 05 CD 0000 CD 0000 3 E 01 3208 FE C 39505 C 9 01008 01008 C F 01012 01015 01018 01019 01018 IC 01010 IF 01022 01023 01024 01025 01026 01029 0102 A 0102 D 0102 E 01031 01034 01035 01038 01039 3 A 4 CF 7 07 DA 1210 CDCB 10 2121 F 7 3 A 0210 47 I E 00 53 78 FE 00 CA 3810 14 7 E 23 07 D 23410 IC 3 A 0110 BA DA 3410 CD 0000 C 31 C 10 7 B FE 00 1.571,230 % 261,571,230 26 PRESS FAULT CODE LAMP ON RESET FLAG, INDICATE FAULT NO FLAGS SET PRESS FAULT CODE LAMP OFF SET FLAG, NO FAULT PRESENT YES SAVE NO OF FLAGS SET TABLE III

DISPLAY FAULT CODE/LOOP NOT READY 02 B 09 3 A 32 F 4 FLTDISP IF:

02 BOC 02 BOD 02 B 10 02 B 13 02 B 15 02 B 18 02 B IA 02 B 1 D 02 B 20 07 D 24 C 2 B 3 A 22 FE FE 00 CA 3928 2 E 6 A CD 0000 D 2392 B 3 AOEF 4 02 B 23 07 02 B 24 DA 362 B 02 B 27 CD 952 B 02 B 2 A CDOA 2 C 02 B 2 D AF 02 B 2 E 02 B 31 02 B 33 02 B 36 02 B 39 02 B 3 C 02 B 3 D 02 B 40 02 B 41 02 B 44 02 B 45 02 B 48 02 B 49 3231 F 4 3 E 80 320 EF 4 C 34 C 2 B 3 A 6 FF 4 07 DA 4 C 2 B AF 3231 F 4 AF 3232 F 4 AF 320 EF 4 02 B 4 C C 9 IF:

ANDIF:

IF:

CALL CALL CFLG SFLG ENDIF ELSE:

IF:

CFLG CFLG CFLG ENDIF ENDIF ENDIF RET FLG,DSPLFLT,T VBYT,FLTTOT,NZ IBIT,FAULT#CD,T FLG,FLTSHOW,F FLTFIND FLTDCTL DSPL 1 ST FLTSHOW DISPLAY FLT CODE WAS PUSHED FAULTS EXIST BUTTON STILL PUSHED CHECK IF CODE ALREADY DISPLAYEI LOOK FOR NEXT FAULT IN TABLE GET FAULT CODE, PREP FOR DISPLA' REQUEST DISPLAY OF FAULT CODl FAULT CODE READY FOR DISPLA' FLG,FLTCSHW,F DSPL 1 ST DSPLFLT CALL FOR OLD DISPLAY DO NOT DISPLAY FAULT CODE FLTSHOW 01038 01038 01041 01043 01044 01045 01046 01047 01048 0104 B 0104 E 01051 01053 01054 01055 01056 01057 01059 C D 01060 CA 4810 2181 FF 3 E 01 F 3 B 6 77 FB AF 328 BF 7 C 35 C 10 21 FIFF 3 EFE F 3 A 6 77 FB 3 E 80 328 BF 7 7 B 321 DF 8 C 9 SOBIT CFLG ELSE:

COBIT SFLG ENDIF MOV STA RET PRES$FCD FLTRDY PRES$FCD FLTRDY A,E FLTTOT 1,571,230 TABLE IV

FAULT DISPLAY TOP COVER CONTROL/LOOP NOT READY 02 B 4 D 3 AOEF 4 FLTCOVR IF: FLG,FLTSHOW,F 07 DA 942 B 3 A 7 CF 7 IF:

07 D 2812 B 2 EF 9 AN CD 0000 D 2812 B 3 A 6 FF 4 IF:

07 DA 7 E 2 B CD 8 B 2 B CA CDOA 2 C CA 3 F 80 SFI 326 FF 4 3 E 80 SF 1 FLG,PROCJAM,T DIF:

IBITTCVR#OPNT FLG,FLTCSHW,F LL:

LL:

LG LG CFLG ENDIF ELSE:

IF:

CFLG CFLG CFLG FLTCFND FLTDCTL FLTCSHW DSPLFLT CHECK IF DISP FAULT CODE PUSHED CHECK FOR PROCESSOR JAM CHECK IF TOP COVER IS OPEN CHECK IF DISPLAY REQ BY COVER FIND WHICH FLAG IS SET GET FAULT CODE REQUEST DISPLAY OF FAULT CODE DSPL 1 ST FLG,FLTCSHW,T FLTCSHW CHECK IF DISPLAY NOT REQUIRED CLEAR FLAGS DSPL 1 ST DSPLFLT ENDIF ENDIF ENDIF RET TABLE V

DETERMINE WHICH FAULT IS TO BE DISPLAYED / SUBR 02 B 95 3 E 80 FLTFIND SFLG FLTWILE 02 B 97 3205 F 4 02 B 9 A 2 A 79 F 8LHLD FLTADDR 02 B 9 D 3 A 05 F 4WHILE: FLG,FLTV 02 BAO 07 02 BAI 02 EA 2 B 02 BA 4 3 A 5 EF 4IF: FLG,FLTT 02 BA 7 07 02 BA 8 D 2 B 32 B 02 BAB AF CFLG FLTTOP 02 BAC 325 EF 4 02 BAFAF XRA A VILE,T ?OP,T SET WHILE: LOOP CONTROL FLAG GET ADDRESS OF FLAG CHECK IF AT TOP OF TABLE 02 B 50 02 B 51 02 B 54 02 B 57 02 B 58 02 B 58 02 B 5 D 02 B 60 02 B 63 02 B 66 02 B 67 02 B 6 A 02 B 6 D 02 B 70 02 B 72 02 B 75 02 B 77 02 B 74 02 B 7 B 02 B 7 E 02 B 81 02 B 84 02 B 85 02 B 88 02 B 89 02 B 8 C 02 B 8 D 02 B 90 02 B 91 3232 F 4 AF 3231 F 4 C 3942 B 3 A 7 FF 4 07 D 2942 B AF 326 FF 4 AF 3231 F 4 AF 3232 F 4 02 B 94 C 9 1,571,230 v V,71-3 28 02 BB O C 3 B 62 B 02 BB 3 3 A 34 FE 3234 FE F 7 E 23 07 D 2 D 92 B AF 3205 F 4 7 B ELSE:

LDA ENDIF INR STA MOV MOV INX RLC IF:

CFLG IF:

FLTNUM A FLTNUM E,A AM, H CC,C,S FLTWILE XBYT,E,EQ,FLTFLGS GET FAULT POINTER INCREMENT FAULT CODE STORE IT GET FLAG INCREMENT FLAG ADDRESS TEST FLAG RESET LOOP CONTROL FLAG CHECK FOR END OF FAULT ARRAY 02 BC 6 FE 50 02 BC 8 C 2 D 32 B 02 BCB 3 E 80 02 BCD 325 EF 4 02 BD O 2121 F 7 02 BD 3 2279 F 8 02 BD 6 C 3 E 72 B 02 BD 9 7 B 02 BDA FF 50 02 BDC C 2 E 72 B 02 BDF 3 F 80 02 BEI 325 FF 4 02 BE 4 2121 F 7 02 BE 7 C 39 D 2 B 02 BEA C 9 SFLG LXI ENDIF SHLD ELSE:

IF:

SFLG LXI ENDIF ENDIF ENDWHILE RET FLTTOP H,FLTTBL FLTADDR XBYT,E,EQ,FLTFLGS GET STARTING ADDR OF ARRAY SAVE IT CHECK FOR END OF TABLE FLTTOP H,FLTTBL POINT TO TOP OF ARRAY TABLE Vi

GET DISPLAY DATA FROM TABLE / SUBR 017 D 1 3 AD 017 017 D 4 3 D 017 D 5 07 017 D 6 1600 017 D 8 5 F 017 D 9 218818 017 DC 19 017 DD 7 E 017 DE 3276 F 8 017 BI 23 017 82 7 E 017 83 1176 F 8 017 B 6 017 B 7 12 017 88 3 E 07 017 EA 3278 F 8 017 BD C 9 FLTDCTL DCR RLC MVI MOV LXI DAD MOV STA INX MOV LXI INX STAX MVI STA RET LDA FLTNUM A D,O E,A H,FLTDTBL D A,M FLTDSPL H A,M D,FLTDSPL D D A,7 FCDIGIT GET FLAG NO, USE AS POINTER DECREMENT DOUBLE RESULTANT POINTER SET UP INDEX GET BASE ADDR OF DATA TABLE ADD INDEX GET LSD STORE IN DISPLAY WORD (LSD) GET MSD STORE IN DISPLAY WORD (MSU) USE 100 'o S, 10 'S, I'S DIGITS SAVE DIGIT BLANKING BITS 02 BB 6 02 BB 7 02 BBA 02 BBB 02 BBC 02 BBD 02 BBE 02 BCI 02 BC 2 02 BC 5 1,571,230 8 R TABLE VII

LOOK FOR PAPER ON JAM SWITCHES STANDBY / SUBR 02 D 30 2 ED 7 JAMSCAN RIBYT JSWBYTE 02 D 32 CD 0000 02 D 35 3233 FESTA JSWBITS 02 D 38 FE 00IF: VBYT,A,NZ LXI MVI WHILE:

LDA RRC STA IF:

MVI MOV ENDIF DCR INX ENDWHILE ENDIF RET H,FLTTRL B,7 VBYT, B,NZ JSW B ITS JSWBITS CC,C,S A,X'80 ' M,A B H TEST PAPER PATH JAM SWITCHES SAVE CONTENTS OF BYTE CHECK IF ANY BITS ARE SET GET ADDR OF IST JAM FLAG SCAN 7 BITS CHECK IF MORE BITS TO SCAN GET BIT TEST BIT LOAD MASK SET FLAG DECREMENT BIT COUNT INCREMENT ADDR TABLE VIII

TURN ON LAMPS ASSOCIATED WITH FAULT CODES / SUBR 02 C 20 E 5 FLTLAMP PUSH H 02 C 2 A 7 A IF: XBYT,D,LE,10 02 C 2 B FEOA 02 C 2 D DA 332 C 02 C 30 C 23 D 2 C 02 C 33 3 A 7 CF 7 ANDIF: FLG,PROCJAM,T CALL ENDIF IF:

SOBIT ENDIF POP RET SAVE H AND L REGISTERS CHECK IF STATUS PANEL FLAG SET CHECK FOR PROCESSOR JAM FLTSPNL XBYTD,GE,22 C$DOORS H LOOK FOR CHECK DOORS FAULT TURN ON CHECK DOORS LAMP GET H AND L REGISTERS 02 D 3 A 02 D 3 D 02 D 40 02 D 42 02 D 43 02 D 45 02 D 48 02 D 4 B 02 D 4 C 02 D 4 F 02 D 52 02 D 54 02 D 55 02 D 56 02 D 57 02 D 5 A CA 5 A 2 D 2121 F 7 0607 78 FF 00 CA 5 A 2 D 3 A 33 FE OF 3233 FE D 2552 D 3 E 80 23 C 3422 D C 9 02 C 36 02 C 37 02 C 3 A 02 C 3 D 02 C 3 E 02 C 40 02 C 43 02 C 46 02 C 48 02 C 49 02 C 4 A 02 C 4 B 07 D 23 D 2 C CD 4 E 2 C 7 A FE 16 DA 4 C 2 C 213 FFF 3 E 01 F 3 B 6 77 FB 02 C 4 C E 1 02 C 4 D C 9 1,571,230 1,571,230 TABLE IX

TURN ON STATUS PANEL LAMPS / SUBR 01817 21 BAFF FLTSPNL SOBIT C$STATUS 0181 A 3 E 01 0181 C F 3 0181 D B 6 0181 E 77 0181 F FB 01820 210000 SOBIT FACE$JAM 01823 3 E 00 01825 F 3 01826 B 6 01827 77 01828 FB 01829 21 B 2 FFSOBIT FUS$JAM 0182 C 3 E 20 0123 E F 3 0182 F B 6 01830 77 01831 FB 01832 21 F 7 FFSOBIT REG$JAM 01835 3 E 20 01837 F 3 01838 B 6 01839 77 0183 A FB 0183 B21 B 4 FFSOBIT C$X$JAM 0183 E 3 E 20 01840 F 3 01841 B 6 01842 77 01843 FB 01844 3 A 13 F 4IF: FLG,2 SDFLAG,T 01847 07 01848 D 26718 0184 B21 EBFF SOBIT INVT$JAM 0184 E 3 E 20 01850 F 3 01851 B 6 01852 77 01853 FB 01854 3 A 14 F 4IF: FLG,SIDEI,T 01857 07 01858 D 26418 B21 BOFF SOBIT RETX$JAM E 3 E 20 01860 F 3 SOBIT B$X$JAM 01861 B 6 01862 77 01863 FB ENDIF 01864 C 37718 ELSE:

01867 3 A 15 F 4IF: FLG,AXFLAGF 0186 A 07 B DA/718 0186 E21 E 8 FFSOBIT B$X$JAM 01871 3 E 20 CHECK STATUS PANEL FACE UP FUSER REGISTRATION C TRANSPORT CHECK FOR 2 SIDED COPY INVERTER RETURN TRANSPORT B TRANSPORT CHECK FOR AUX TRAY SELECT B TRANSPORT 1,571,230 31 FLG,SOSJAM,T SOS$JAM CHECK FOR SOS JAM SOS TABLE X

HISTORY FILE 00019 2110 E 2 0001 C 1121 F 7 0001 F 3 F 2 A 00021 00022 00028 0002 A 0002 D 00033 00036 00039 0003 C 0003 E 00041 BB DA 2 D 00 CD 0000 3 E 2 A C 32100 2124 E 2 114 FF 7 3 F 52 BB DA 4100 CD 0000 3 E 52 C 33500 2140 E 2 00044 1148 F 7 00047 00049 0004 A 0004 D 00052 3 F 48 BB DA 5500 CD 0000 3 F 48 C 34900 HISTFLE LXI LXI H,NVTAB I D,FLTTAB I MVI A,FLTTB IF WHILE:

CALL MVI ENDWHILE LXI LXI MVI WHILE:

CALL MVI ENDWHILE LXI LXI MVI WHILE:

CALL MVI ENDWHILE XBYT,A,GE,E HSTBCNT A,FLTB IF H,NVTAB 2 D,FLTTAB 2 A,FLTTB 2 F XBUT,A,GE,F HSTBCNT A,FLTTB 2 F H,NVTAR 4 D, FLTTAB 4 A,FLTTB 4 F XBYT,A,GE,F LOAD MEM POINTER WITH BEGINING PATH JAM COUNTERS LOAD POINTER WITH BEGINING OF PAPER PATH FAULT TABLE LOAD ACCUM WITH LSBYTE OF THE END OF THE PAPER PATH FAULT TABLE LOOP UNTIL THROUGH FAULT TABLE

CALL ROUTINE TO UPDATE A COUNTER NUMEM DEPENDING ON D 7 BIT OF MEMORY PREPARE FOR END OF TABLE TEST LOAD POINTER WITH START OF RESET AND COUNT ERROR COUNTERS LOAD POINTER WITH START OF RESET AND COUNT ERROR FAULT TABLE LOAD ACCUM WITH END OF 2ND FAULT LOOP UNTIL THROUGH 2ND FAULT TABLE

LOAD PNT WITH STRT OF FUSER UNDER TEST AND CLEAN SOS COUNTERS LOAD PNTR WITH STRT OF FUS UNDER TEST AND CLN SOS FAULT TABLE SET UP END OF FAULT TABLE LOOP UNTIL THROUGH FAULT TABLE

HSTBCNT A,FLTTB 4 F 31 01873 01874 01875 01876 01877 0187 A 0187 B 0187 E 01881 01883 01884 01885 01886 01887 ENDIF ENDIF IF:

SOBIT F 3 B 6 77 FB 3 A 2 CF 7 07 D 28718 21 F 4 FF 3 E 20 F 3 B 6 77 FB C 9 ENDIF RET 1,571,230 2142 E 2 00058 1158 F 6 B 3 F 5 A LXI LXI MVI 1,571,230 H,NVTAB 5 D,FLTTAB 5 A,FLTTB 5 F START PRINTER AT BEG OF FEEDER STRT PNTR AT BEG OF FEEDER FLT SET UP END OF FEEDER FLT TABLE BR WHILE:

DA 6900 CD 0000 CALL OF 5 A MVI C 35 D 00 ENDWHILE 3 A 74 F 4 IF:

07 07 BF 6 LXI 3 F 5 CMVI BB WHILE:

DA 8100 CD 0000 CALL 3 F 5 CMVI C 37500 ENDWHILE ENDIF AF XRA 2 AB 3 F 8 I HLD B 5 ORA B 4 ORA CA 9300 IF:

114 CE 2 LXI CD 0901 CALL 22 B 3 F 8 SHLD ENDIF 2 AB 5 F 8 LHLD B 5 ORA B 4 ORA CAA 400 IF:

1152 E 2 LXI CD 0901 CALL 22 B 5 F 8 SHLD ENDIF 2 AB 7 F 8 LHLD B 4 ORA B 5 ORA CAB 500 IF:

1158 E 2 LXI CD 0901 CALL 22 B 7 F 8 SHLD ENDIF 2 A 89 F 8 LHLD B 4 ORA B 5 ORA CACF 00 IF:

EE 2 LXI CD 0901 CALL 2 AB 9 F 8 LHLD 1,571,230 XBYT,A,GE,F HSTBCNT A,FLT 185 F FLG,SRTSFI,T D,FLTTAB 6 A,FLTTB 6 F XBYT,A,GE,F HSTBCNT A,FLTTB 6 F A SDFLHST 1 H CC,Z,C D,NVCNT I HSTDCNT SDFLHST FDFLHST L H CC,Z,C D,NVCNT 2 HSTDCNT FDELHST ADFLHST H L CC,Z,C D,NVCNT 3 HSTDCNT ADELHST TFLHHST H L CC,Z,C D,NVCNT 4 HSTDCNT TFLHHST LOOP UNTIL THROUGH FAULT TABLE

COUNT SORTER JAMS IF SELECTED SET PNT TO STRT OF SRT JAM FLAG CLEAR ACCUM FOR ZERO TEST FETCH BCD CNT OF SHEETS DELIVERED DO NOT UPDATE NVCOUNTER OF NO SHEETS DELIVERED TO SRT DURING LAST JOB SET POINTER TO SORTER NV COUNTER CALL ROUTINE TO UPDATE 6 DIGIT CLEAR BCD CNT OF SHEETS DELIVERED BCD COUNT OF SHEETS DEL TO FACE UP TR CHECK FOR ZERO COUNT IN LAST JOB SET POINTER TO FACE UP NV COUNTER UPDATE NV COUNTER WITH CURRENT COUNT CLEAR FACEUP COUNT FROM LAST JOB BCD COUNT OF AUX TRAY DELIVERED SKIP UPDATE IF COUNT IS ZERO SET POINTER TO AUX TRAY NV COUNTER UPDATE NV COUNTER WITH CURRENT COUNT CLEAR CURRENT AUX TRAY COUNT BCD COUNT OF TOTAL FLASHES NVCOUNTER OF TOTAL FLASHES 33 D E 00061 00064 00064 00069 0006 C 0006 D 00073 00076 00079 0007 C 0007 E 00081 00082 00086 00087 0008 A 0008 D 00093 00096 00097 00098 0009 B 0009 E 000 A I 000 A 4 000 A 7 000 A 8 000 A 9 000 AC 000 A F 000 B 2 000 B 5 000 B 8 000 B 9 000 BA 000 BD 000 C O 000 C 3 1,571,230 1),NCNTF HSTDCNT TFL HlH-ST 2 FLHHST H L CC,z,C 1 D,NVCNT 5 HSTDCNT 2 FLHHST NYCOUNTER OF TOTAL FLASHES ON BCD CNTR OF TOTAL SIDE 2 FLSH UPDATENVCNTR IF CURRENT CNT N 000 C 6 000 C 9 000 CC OOOCF 000 D 2 000 D 3 000 D 4 000 D 7 OOODA OOODD OOOEO 11 70 E 2 CD 0901 22 B 9 F 8 2 ABBF 8 B 4 B 5 CAEOOO 1 164 E 2 CD 0901 22 BBF 8 C 9 LXI CALL SHLD ENDIF LHLD ORA ORA IF:

LXI CALL SHLD ENDIF RET 1,571,230 TABLE XI

HISTORY B COUNTER ROUTINE 00000 00001 00002 00003 00006 00007 00008 0000 B 0000 C 0000 D 0000 E IA HSTBCNT 1 DAX D 07 7 E CF 00 77 BE 23 CA 1600 34 AF BF C 21600 RLC MOV ACI MOV CMP INX IF:

INR XRA CMP IF:

000112 F CMA 0001277 MOV 000132 B DCX 0001477 MOV 0001523 INX ENDIF ENDIF 0001623 INX 0001713 INX 00018C 9 RET A,M 0 M,A M H CC,Z,C M A M CC,Z,S FETCH FLAG TO ACCUM SET/CLEAR CARRY BIT FETCH LSNIBBLE OF COUNTER UPDATE WITH CARRY STORE UPDATED NIBBLE CHECK FOR OVERFLOW MOVE POINTER TO MSNIBBLE IF OVERFLOW OUT OF LSNIB B LE INCREMENT MSNIBBLE TEST MSNIBBLE FOR ZERO IF ZERO THE COUNTER OVERFLOWED LOAD MSNIBBLE WITH 'F' M,A H M,A H LOAD LSNIBBLE WITH 'F' RESTORE NV POINTER H MOV POINTER TO LSNIBBLE OF NEXT FLAG MOV POINTER TO NEXT FLAG D TABLE XII

HISTORY D COUNTER ROUTINE 00109 EB HSTDCNT XCHG A 7 B MOV A,F B C D 86 ADD 27 DAA 77 MOV E D 21201 0011114 IF:

INR ENDIF 00112AF XRA 00113CD 4101 CALL 00116CAIA 01 IF:

0011937 STC 0011 A 7 A 0011 B23 0011 C 8 E 0011 D 001 IE 0011 F 00122 27 77 D 22401 EF 01 ENDIF MOV INX ADC DAA MOV IF:

XRI M M,A CC,C,S D M HSTDCTS CC,Z,C A,D H M M,A CC,C,S ENDIF SWAP CURRENT CNT AND POINTER TO LOAD UNIT/TENS DIGITS OF CURRENT UPDATE UNITS DIGITS(LSNIB) OF NV CHECK FOR OVERFLOW INC HUND/THOU DIGIT IF OVERFLOW MASK OF UPDATED CURRENT TENS DIGIT UPDATE TENS DIGIT AND SET OVERFLOW INDICATE OVERFLOW BY SETTING CA FETCH CURRENT HUND/THOU DIGIT MOVE POINTER TO HUNDREDS NIBBLE UPDATE WITH CURRENT+ OVERFLOW STORE UPDATE CHECK FOR OVERFLOW COMPLEMENT DO BIT TO SET OVERFLOW 00124 AF XRA M MASKOFF 1000 'S NIB/SET OVERFLOW CD 4101 CALL HSTDCTS UPDATE THOU DIGIT AND SET OVERFLOW 00128 CD 4101 CALL HSTDCTS UPDATE 10 K DIGIT WITH OVERFLOW 0012 B CD 4101 CALL HSTDCTS UPDATE 100 K DIGIT WITH OVERFLOW 0012 E CA 3 E 01 IF: CC,Z,C CHECK FOR OVERFLOW FROM K DIGIT 00131 2 F CMA 00132 77 MOV M,A LOAD 100 KDIGIT WITH'F' 00133 2 B DCX H 00134 77 MOV M,A LOAD 10 K DIGIT WITH'F' 2 B DCX H 00136 77 MOV M,A LOAD 1 K DIGIT WITH'F' 00137 2 B DCX H 00138 77 MOV M,A LOAD 100 DIGIT WITH 'F' 00139 2 B DCX H 0013 A 77 MOV M,A LOAD 10 DIGIT WITH'F' 0013 B 2 B DCX H 0013 C 77 MOV MA LOAD UNIT DIGIT WITH 'F' 0013 D AF XRA A CLEAR ACCUM TO CLEAR REG PAIR ENDIF 0013 E 67 MOV H,A SET UP REGISTER PAIR TO CLEARC 0013 F 7 F MOV L,A C 9 RET This application is divided from copending application 15487/77 (Serial No.

1571229) and the reader is directed to the claims thereof.

Claims (9)

WHAT WE CLAIM IS:-

1 A reproduction system comprising a plurality of copy processing components cooperable to produce copies and a controller for operating said components in accordance with a program to produce copies, said program 5 incorporating a fault flag array, each flag of said fault flag array being associated with an individual fault, plural fault sensors for detecting faults during operation of said copy processing components, each of said fault sensors being associated with a predetermined one of said fault flags in said fault array, each of said fault sensors setting the fault flag associated therewith in response to detection of a fault by said 10 sensor means to initiate scanning of said array of fault flags; means for generating a preset fault signal for each fault flag, and display means responsive to said preset fault signals to identify the fault represented by any fault flag in said array that has been set.

2 A system as claimed in claim I including means to selectively actuate said 15 display means.

3 A system as claimed in claim 1 or claim 2 including means responsive to a fault condition in said system to generate a fault signal.

4 A system as claimed in any one of claims 1 to 3 including control means effective for periodically actuating said scanning means to scan said fault flag 20 array; and flag detection means responsive to detection of a set fault flag by said scanning means to actuate said display means and to identify the fault represented by said set flag.

A system as claimed in claim 4 wherein said scanning means is adapted, following actuation of said display means and identification of said fault to resume 25 scanning of said fault flag array.

6 A system as claimed in claim 4 or claim 5 comprising means forming a processing path for said copies, said fault sensors including processing path sensors disposed at preset points along said processing path to detect faults in said processing path, said fault flag array including processing path fault flags associated 30 I 1,571,230 with said processing path sensors, said display means including a map representative of said processing path, said map having lamps correlated with the position of said processing path sensors along said processing path said flag detection means responding to setting of at least one of said processing path fault flags to actuate the lamp associated with said fault flag flags to actuate the lamp 5 associated with said fault flag whereby to identify the location of the fault in said processing path on said map.

7 A system as claimed in claim 6 comprising a cover operable to allow access to the processing path, said map being disposed on said cover.

8 A system as claimed in claim 7 comprising means responsive to the opening 10 of the cover to actuate the lamp associated with said fault flag.

9 A system as claimed in any one of claims 1 to 8 wherein said display means in arranged to identify said faults by displaying numerical codes.

For the Applicants:

A POOLE & CO, Chartered Patent Agents, 54 New Cavendish Street, London, WIM 8 HP.

Printed for Her Majesty's Stationery Office by the Courier Press, Leamington Spa, 1980.

Published by the Patent Office, 25 Southampton Buildings, London, WC 2 A l AY, from which copies may be obtained.

I 1,571,230