GB1569773A - D.c. voltage transformer - Google Patents

Description

(54) D.C. VOLTAGE TRANSFORMER (71) We, INTERNATIONAL STANDARD ELECTRIC CORPORATION, a Corporation organised and existing under the Laws of the State of Delaware, United States of America, of 320 Park Avenue, New York 22, State of New York, United States of America, de hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement: This invention relates to D.C.-to-D.C. converter circuits.

As is well known, D.C. voltage transformers or D.C. converters consist of a chopper, a transformer and a rectifier. The voltage from the direct power supply is periodically switched on and off or chopped with the aid of semiconductor devices and is transformed to the desired voltage value. A rectifier circuit following the transformer into a direct output voltage.

In order to obtain constant output voltages, there is usually effected a regulation. In dependence upon the output error, the switch-on times for the semiconductor devices are varied, for which purpose there is preferably used a pulse-width modulator.

Unbalances may be caused by different saturation voltages, different control signals, and differences in the switching times of the semiconductors. These unbalances cause deviations in two successively following voltagetime areas which, in turn, lead to an asymmetrical controlling of the power transformer. This may result in different loads upon the semiconductors and, consequently, in a thermal overloading. In the case of greater unbalances, saturation phenomena may occur in the transformer. The peak currents appearing in the course of this, may lead to a destruction of the semiconductor devices.

Such unbalances can be minimised by selecting the components, i.e. in such a way, for example, that only semiconductors with closely similar characteristics are used. Such a procedure, however, is time consuming and costly.

According to the invention there is provided a direct current to direct current converter of the type in which a direct current supply is chopped and applied, via first and second transistors, as a square wave alternating voltage to a primary winding of a transformer, the converter including a pulse width modulator adapted to provide a pulse output, a clock oscillator coupled to the modulator for determining the pulse frequency, a drive circuit coupled to the pulse output of the modulator and whereby the transistors are provided with base current pulses, a rectifier coupled to a secondary winding of the transformer, an amplifier coupled in a feedback loop between the rectifier and the modulator for providing to the modulator signals indicative of the output voltage of the rectifier, and an adjustable direct voltage source coupled to the modulator, in which the modulator is so arranged as to drive the transistors in antiphase via the drive circuit, in which, in response to the amplifier feedback signal, the pulse width modulator controls the width of the output pulses so as to stabilise the rectifier output voltage at a predetermined value, and in which said pulse width modulator is so controllable via the adjustable voltage source as to equalise substantially the mean currents carried by the transistors.

With such an arrangement it is not necessary to select the semiconductor devices for the purpose of avoiding unbalance. As the sum of the voltage-time areas is constant there will not appear any influencing of the existing control circuit for controlling a constant output voltage, so that there will also be no tendency towards oscillations in the control circuit. The unbalances occurring on account of the controlled semiconductor devices are thus completely eliminated by involving only a very small investment in components.

The signal additionally affecting the control, is adjustable. In this way it is possible to in dude also variations caused e.g. by the aging of the semiconductor devices. The signal is dependent upon the difference of the output currents of the controlled semiconductor device. In this way there is achieved a continuous readjustment of signal variations which are due to temperatures, aging, and the like, without affecting the existing control circuit aimed at regulating the output voltage.

The control is suitable for use with push-pull type transformers, bridge circuits, for driving two parallel-operating single-ended transformers or choppers with a symmetrical current distribution and for the parallel operation of two power stages in low-frequency switching network parts.

An embodiment of the invention will now be described with reference to the accompanying drawings, in which: Fig. 1 shows the block diagram of a pushpull d.c. voltage transformer (=dc-to-dc conver ter), Fig. 2 shows the block diagram the pulsewidth modulator controlling the chopper switches, Fig. 3 shows pulse trains as functions of time at different discrete points of the circuit, and Fig. 4 shows part of the block diagram according to Fig. 1.

Referring to Fig. 1, the converter is driven from a d.c. supply 1, and includes a chopper constituted by the transistors 2 and 3, a transformer 4 and a rectifier 5. The primary windings 4.1 and 4.2 of the transformer are arranged in series, with the primary winding 4.1 being arranged in the emitter-collector circuit of transistor 2 and the primary winding 4.2 being arranged in the emitter-collector circuit of transistor 3. To the d.c. supply 1 there is connected a filter 6 which suppresses interference from the chopper circuit. The d.c. voltage, from which noise is suppressed by the filter 6, is connected to the two primary windings 4.1 and 4.2 of the transformer. The secondary winding 4.3 of which, for effeciency, is designedto- gether with the rectifier 5 in a centre tap arrangement. The rectifier 5 is provided with RFI suppression elements as well as with smoothing filters for smoothing the rectified output voltage. The rectified, smoothed and noise-suppressed output voltage is applied to the output terminals 7 and 8.

The transistors are controlled by a pulsewidth modulator 9 via pulse-amplifying driver stages 10 connected to the points of the circuit 9.1 and 9.2. The pulse-width modulator 9 is clocked by an oscillator 11 connected to the point 9.3 of the circuit. The d.c. voltage applied to the output of the rectifier 5, is fed back (circuit point 9.4) via a control amplifier 12 to the pulse-width modulator 9. For safety reasons, a protective circuit 13 is connected to the pulse-width modulator 9 at the point 9.5 of the circuit, serving to disconnect the d.c. voltage transformer electronically in the event of a malfunction. An external source of d.c. voltage 14 whose voltage values are adjustable, is connected to the point 9.6 and 9.7 of the pulsewidth modulator 9.

The pulse-width modulator 9 shown in Fig.

2 includes a differential amplifier 15 whose one input 15.1 is driven by sawtooth pulses from an external RC-circuit 16. To the other input 15.2 there is applied the d.c. voltage fed back from the output of the rectifier 5 of the d.c. voltage transformer via the control amplifier 12 (circuit point 9.4). The output 15.3 of the amplifier 15 is connected to two AND gates 17, 18 whose outputs for the circuit points 9.1 and 9.2. The pulse-width modulator 9 has a further differential amplifier 19 whose inputs are connected to the circuit points 9.6 and 9.7. The outputs thereof are each followed by a monostable multivibrator 20 and 21. The output of the multivibrator 20 is connected to the gate 17 and the output of the multivibrator 21 is connected to the gate 18. The two multivibrators 20 and 21 are clocked by the oscillator 11 (circuit point 9.3). The oscillator 11 is connected via the circuit point 9.3 to a frequency divider 22. This frequency divider 22 is connected with its output to the AND gates 17 and 18. The frequency divider supplies pulse signals which are each inverse in relation to the AND gates 17 and 18. A further monostable multivibrator 23, likewise clocked by the oscillator 11 (circuit point 93) is connected with its output end likewise to the two AND gates. Moreover, it is connected with its output to the input 15.1 of the differential amplifier 15 conducting the sawtooth pulse from the Circuit 16.

The mode of operation of the circuit arrangement of Figs. 1 and 2 is as follows: The D.C. voltage from the power supply 1, noise-suppressed by the filter 6, is chopped by the periodic on-off switching of the transistors 2 and 3 operated in anti-phase, then transformed by the primary windings 4.1 and 4.2 to the secondary winding 4.3 of the converting transformer 4, and rectified by the rectifier 5, smoothed, and noise-suppressed, and is available at the output terminals 7 and 8 of the d.c.

voltage transformer. The transistors 2 and 3 are controlled by the pulse-width modulator 9.

For stabilising the output voltage of the d.c.

voltage transformer voltage regulation is provided such that the voltage at the output of the rectifier 5 is fed back via the control amplifier 12 and the circuit point 9.4 to the input 15.2 of the amplifier 15 of the pulse-width modulator 9. The second input 15.1 of the differential amplifier 15 is acted upon by the sawtooth pulses suppled by the RC-circuit 16. The pulse sequence supplied by the oscillator 11 and appearing at the circuit point 9.3, is shown in Fig.

3a. The monostable multivibrator 23 as clocked by the oscillator 11, supplies the synchronizing pulses shown in Fig. 3b, serving to synchronize the sawtooth pulses from the external RC-circuit 16. The pulse train shown in Fig. 3c appears at the input of the differential amplifier 15, at which the sawtooth pulses as synchronized by the synchronizing pulses from the multivibrator 23, are superimposed by a d.c.

voltage which is in proportion to the fed back output voltage. Accordingly, at the output of the differential amplifier 15 there will then appear a pulse train as shown in Fig. 3d. This pulse train is fed to the AND gates 17 and 18.

The pulse width of the output pulses at the differential amplifier 15 is dependent upon the output error (deviation) of the d.c. voltage at the output of the d.c. voltage transformer. The synchronizing pulses as shown in Fig. 3b are also applied to the AND gates 17 and 18. By means of these pulses overlapping is avoided since, at a maximum width of the controlling output pulses, one transistor is already turned off before the other one is turned on.

By the frequency divider 22, the oscillator pulses as shown in Fig. 3a are stepped down and each time inversely fed to the AND gates 17 and 18; the pulse train applied to the AND gate 17 is shown in Fig. 3e, and the pulse train applied to the AND gate 18 is shown in Fig. 3j.

To the inputs of the differential amplifier 19 (circuit points 9.6, 9.7) forming part of the pulse-width modulator 9, there is applied the d.c. voltage from the source of d.c. voltage 14. This d.c. voltage is adjustable. The adjusted d.c. voltage value is so high as to correspond to the transistor output current difference. In dependence upon this d.c. voltage, the pulse widths at the outputs of the multivibrators 20 and 21 as connected to the outputs of the differential amplifier 19, are controlled so as to equalise the mean currents carried by the transistors.

The pulse train as appearing at the output of the multivibrator 20, is shown in Figs. 3f and 3h, i.e. Fig. 3f shows the pulse train when at balance, i.e. the difference of the output currents equals zero, and Fig. 3h shows the pulse train when at unbalance, i.e. the difference of the output currents is unequal to zero. The pulse train as appearing at the output of the multivibrator 21 is shown in Figs. 3k and 3m.

Fig. 3k shows the pulse train when at balance, which is equal to the pulse train shown in Fig.

3f. Fig. 3m shows the pulse train when at unbalance. Compared to the pulse trains shown in Figs. 3f and 3k, the voltage-time areas of the pulse train according to Fig. 3h are exactly by the same amount larger, by which they are smaller in the pulse train 3m, so that the existing voltage regulating circuit will not be affected.

The pulses are processed by the AND gates 17, 18. The output pulses of the gates are produced in the following way: The beginning of the period is each time predetermined by the oscillator signal. The right-hand pulse edge is respectively determined by the pulses of the pulse train (Fig. 3d) as formed by the pulse, width modulator. The left-hand pulse edge is respectively determined by the pulses of the pulse train as formed by the monostable multivibrator 20, 21. The pulse trains as appearing at the output of the conjunction element 17 are shown in Figs. 3g and 3i, i.e. in Fig. 3g when at balance, and in Fig. 3i when at unbalance. The pulse trains appearing at the output of the conjunction element 18 are shown in Figs. 31 and 3n, i.e. in Fig. 31 when at balance, and in Fig. 3n when at unbalance.

The output pulses of the gates 17 and 18 control the transistors 2 and 3 such that the voltage-time areas thereof are equal.

To the monostable multivibrator 23, via the circuit point 9.5 of the pulse-width modulator 9, there is also connected the protective circuit 13, so that in the event of any trouble, the pulse-width modulator 9 can be switched off by the multivibrator 23.

Fig. 4 shows a variant form of Fig. 1. In this case the output current difference of the transistors 2 and 3 is dealt with by means of an add itional transformer 24.

The primary winding 24.1 of this additional transformer 24 is connected between the primary windings 4.1 and 4.2 of the converting transformer 4. The secondary winding 24.2 of this additional transformer 24 is arranged with two valves 25 and 26 in a centre-point connection, with the cathodes of the valves being connected to the centre point via each time one capacitor 27 and 28. This centre-point arrangement is connected instead of the adjustable d.c.

voltage source 14 to the circuit points 9.6 and 9.7 of the pulse-width modulator 9. In this way it is possible to deal with any variations of the output currents caused by temperature response, aging, and the like, and to effect a balance (symmetry) control without affecting the existing control circuit provided for regulating the d.c. voltage transformer (dc-to-dc converter).

WHAT WE CLAIM IS: 1. A direct current to direct current converter of the type in which a direct current supply is chopped and applied, via first and second transistors, as a sqaure wave alternating voltage to a primary winding of a transformer, the converter including a pulse width modulator adapted to provide a pulse output, a clock oscillator coupled to the modulator for determining the pulse frequency, a drive circuit coupled to the pulse output of the modulator and whereby the transistors are provided with base current pul, ses, a rectifier coupled to a secondary winding

**WARNING** end of DESC field may overlap start of CLMS **.

Claims (5)

**WARNING** start of CLMS field may overlap end of DESC **. amplifier 15 is acted upon by the sawtooth pulses suppled by the RC-circuit 16. The pulse sequence supplied by the oscillator 11 and appearing at the circuit point 9.3, is shown in Fig. 3a. The monostable multivibrator 23 as clocked by the oscillator 11, supplies the synchronizing pulses shown in Fig. 3b, serving to synchronize the sawtooth pulses from the external RC-circuit 16. The pulse train shown in Fig. 3c appears at the input of the differential amplifier 15, at which the sawtooth pulses as synchronized by the synchronizing pulses from the multivibrator 23, are superimposed by a d.c. voltage which is in proportion to the fed back output voltage. Accordingly, at the output of the differential amplifier 15 there will then appear a pulse train as shown in Fig. 3d. This pulse train is fed to the AND gates 17 and 18. The pulse width of the output pulses at the differential amplifier 15 is dependent upon the output error (deviation) of the d.c. voltage at the output of the d.c. voltage transformer. The synchronizing pulses as shown in Fig. 3b are also applied to the AND gates 17 and 18. By means of these pulses overlapping is avoided since, at a maximum width of the controlling output pulses, one transistor is already turned off before the other one is turned on. By the frequency divider 22, the oscillator pulses as shown in Fig. 3a are stepped down and each time inversely fed to the AND gates 17 and 18; the pulse train applied to the AND gate 17 is shown in Fig. 3e, and the pulse train applied to the AND gate 18 is shown in Fig. 3j. To the inputs of the differential amplifier 19 (circuit points 9.6, 9.7) forming part of the pulse-width modulator 9, there is applied the d.c. voltage from the source of d.c. voltage 14. This d.c. voltage is adjustable. The adjusted d.c. voltage value is so high as to correspond to the transistor output current difference. In dependence upon this d.c. voltage, the pulse widths at the outputs of the multivibrators 20 and 21 as connected to the outputs of the differential amplifier 19, are controlled so as to equalise the mean currents carried by the transistors. The pulse train as appearing at the output of the multivibrator 20, is shown in Figs. 3f and 3h, i.e. Fig. 3f shows the pulse train when at balance, i.e. the difference of the output currents equals zero, and Fig. 3h shows the pulse train when at unbalance, i.e. the difference of the output currents is unequal to zero. The pulse train as appearing at the output of the multivibrator 21 is shown in Figs. 3k and 3m. Fig. 3k shows the pulse train when at balance, which is equal to the pulse train shown in Fig. 3f. Fig. 3m shows the pulse train when at unbalance. Compared to the pulse trains shown in Figs. 3f and 3k, the voltage-time areas of the pulse train according to Fig. 3h are exactly by the same amount larger, by which they are smaller in the pulse train 3m, so that the existing voltage regulating circuit will not be affected. The pulses are processed by the AND gates 17, 18. The output pulses of the gates are produced in the following way: The beginning of the period is each time predetermined by the oscillator signal. The right-hand pulse edge is respectively determined by the pulses of the pulse train (Fig. 3d) as formed by the pulse, width modulator. The left-hand pulse edge is respectively determined by the pulses of the pulse train as formed by the monostable multivibrator 20, 21. The pulse trains as appearing at the output of the conjunction element 17 are shown in Figs. 3g and 3i, i.e. in Fig. 3g when at balance, and in Fig. 3i when at unbalance. The pulse trains appearing at the output of the conjunction element 18 are shown in Figs. 31 and 3n, i.e. in Fig. 31 when at balance, and in Fig. 3n when at unbalance. The output pulses of the gates 17 and 18 control the transistors 2 and 3 such that the voltage-time areas thereof are equal. To the monostable multivibrator 23, via the circuit point 9.5 of the pulse-width modulator 9, there is also connected the protective circuit 13, so that in the event of any trouble, the pulse-width modulator 9 can be switched off by the multivibrator 23. Fig. 4 shows a variant form of Fig. 1. In this case the output current difference of the transistors 2 and 3 is dealt with by means of an add itional transformer 24. The primary winding 24.1 of this additional transformer 24 is connected between the primary windings 4.1 and 4.2 of the converting transformer 4. The secondary winding 24.2 of this additional transformer 24 is arranged with two valves 25 and 26 in a centre-point connection, with the cathodes of the valves being connected to the centre point via each time one capacitor 27 and 28. This centre-point arrangement is connected instead of the adjustable d.c. voltage source 14 to the circuit points 9.6 and 9.7 of the pulse-width modulator 9. In this way it is possible to deal with any variations of the output currents caused by temperature response, aging, and the like, and to effect a balance (symmetry) control without affecting the existing control circuit provided for regulating the d.c. voltage transformer (dc-to-dc converter). WHAT WE CLAIM IS:

1. A direct current to direct current converter of the type in which a direct current supply is chopped and applied, via first and second transistors, as a sqaure wave alternating voltage to a primary winding of a transformer, the converter including a pulse width modulator adapted to provide a pulse output, a clock oscillator coupled to the modulator for determining the pulse frequency, a drive circuit coupled to the pulse output of the modulator and whereby the transistors are provided with base current pul, ses, a rectifier coupled to a secondary winding

of the transformer, an amplifier coupled in a feedback loop between the rectifier and the modulator for providing to the modulator signals indicative of the output voltage of the rectifier, and an adjustable direct voltage source coupled to the modulator, in which the modulator is so arranged as to drive the transistors in antiphase via the drive circuit, in which, in response to the amplifier feedback signal, the pulse width modulator controls the width of the output pulses so as to stabilise the rectifier output voltage at a predetermined value, and in which said pulse width modulator is so controllable via the adjustable voltage source as to equalise substantially the mean currents carried by the transistors.

2. A converter as claimed in claim 1, in which the modulator includes a first differential amplifier to one input of which the feedback amplifier is coupled, the other input being coupled to a sawtooth generator, a second dual output differential amplifier to the inputs of which the adjustable voltage source is coupled, monostable multivibrators respectively clocked by the oscillator and coupled one to each output of the second differential amplifier, and first and second output AND gates, in which the output pulses of the multivibrators are applied to a said respective AND gate, and in which frequency divided clock pulses from the oscillator and the modulator pulses for driving the transistors are applied to both said AND gates.

3. A converter according to claim 2, in which a further oscillator controlled, monostable multivibrator is provided whose output pulses are applied to the AND gates for avoiding the overlapping of pulses.

4. A converter according to any one of claims 1 to 3, in which the output current difference of the controlled semiconductor devices is coupled to further transformer whose primary winding is connected between the primary windings of the transformer, and whose secondary winding is arranged with two rectifiers in a centre-point circuit, with the cathodes of the rectifiers being connected to the centre point via respectively one capacitor.

5. A D.C. to D.C. converter substantially as described herein with reference to the accompanying drawings.