GB1569180A

GB1569180A - Integrated circuit and their manufacture

Info

Publication number: GB1569180A
Application number: GB5406176A
Authority: GB
Original assignee: Philips Electronic and Associated Industries Ltd
Current assignee: Philips Electronics UK Ltd
Priority date: 1975-12-29
Filing date: 1976-12-24
Publication date: 1980-06-11
Also published as: FR2337431A1; NL7614428A; JPS5283081A; FR2337431B1; DE2656962A1; JPS5544462B2

Description

(54) INTEGRATED CIRCUITS AND THEIR MANUFACTURE (71) We, PHILIPS ELECTRONICS AND ASSOCIATED INDUSTRIES LIMITED of Abacus House, 33 Gutter Lane, London, EC2V 8AH a British Company, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement: The present invention relates to integrated circuits comprising at least a first bipolar vertical transistor and further relates to a method of manufacturing such integrated circuits.

Integrated circuits having bipolar transistors are products which nowadays are frequently used in several fields of electronics and there exists a large number of variations.

A particularly important field of application of the invention relates to the circuit arrangements of the family of products which are termed "integrated injection logic" and which are also known by the abbreviation "I2L", which abbreviation will hereinafter be used to indicate said products. A detailed description of the said "12 L" circuits can be found, for example, in published French Patent Application No. 2,138,905.

This type of integrated circuit usually comprises bipolar transistors having a vertical structure which in general have several surface collectors and in which the base regions are coupled to the collector zones of complementary transistors which provide an adjusting current.

The methods generally used for the manufacture of "I2 L" devices have so far been substantially the same as those which serve to manufacture families of bipolar logic integrated circuit according to known techniques, for example, logic with transistors and resistors which is known by the abbreviation "T2 L" (or "TTL"), which is derived from the English expression "transistor-transistor logic".

These methods comprise in particular the combination of steps such as: the growth or deposition from the vapour phase of an insulating protecting layer on the surface of a semiconductor body which generally is of silicon, the provision of apertures in said layer by photoetching, the local diffusion of impurities, the growth of epitaxial layers, ion implantation, and the connection of several elements of the circuit by means of vapour-deposited metal layers which have been converted into a network of connections by photoetching, in which the said network may be provided at a single level or also at several levels if the complicated character of the circuit necessitates this.

One of the main reasons for using substantially the same methods as for the conventional bipolar devices is that in this manner it is possible to integrate peripheral parts of the electronic circuit in the same semiconductor body, which Darts consist of elements of the said families made by known techniques. As a result of this the input and/or output signals of the circuit may be compatible with those of other known circuits.

However, by using such conventional methods for the manufacture of circuits of the "IZL" type which are just designed with a view to the compatibility with other families, a number of drawbacks arise: the number of manufacturing steps is high, for example ten, and often even a larger number of different photoetching masks are necessary for the manufacture of the device.

It is easy to understand that the manu facturing efficiency of an integrated circuit is influenced considerably by the number of operations necessary for its manufacture.

This is the more emphasized because complex integrated circuits or so-called LSIcircuits are concerned, that is comples circuits having a very large number of elements in which the circuits each occupy a comparatively large area of the semiconductor body. The possibility of causing an error which is destructive for the operation of the circuit actually increases rapidly with the number of operations and with the area occupied by the circuit.

From this it follows that the development of integrated circuits having bipolar transistors with an ever increasing complexity is inhibited by technical and economical restrictions which are related to too low manufacturing yields.

Although the object of the introduction of the logic "I2L" technique has been especially the improvement of this situation and in particular the further shifting of the complexity limit of integrated circuits having bipolar transistors, the fact remains that the use of conventional structures of integrated circuits which necessitate methods including a large number of steps involves a practical and economical limitation on large scale integration of even more complex functions.

One may have recourse to the mutual connection of the elements of the circuit with a network at different levels, which, due to the resulting wiring facilities, usually permits a certain reduction of the area occupied by the circuit. The potential gain of the manufacturing yield which may be attained, however, is in practice substantially off-set by the addition of extra steps to the method. These extra steps are particularly delicate because they contribute to the augmentation of the relief of the surface of the circuit, which relief involves an increased risk of defects as a result of breaks in the metal track, for example at the area where parts of the metal track are at different heights.

These drawbacks which are cited with reference to the logical circuits of the "I2L" type, are characteristic of all integrated circuits having bipolar transistors.

According to a first aspect of the invention, there is provided an integrated circuit comprising a semiconductor body having a substrate region of a first conductivity type which supports a number of local regions of the second conductivity type which is opposite to the first, which local regions have substantially the same thicknesses, domains of insulating material being present which adjoin the local regions, and a semiconductor layer configuration of the first condictivity type being present, the integrat ed circuit comprising at least a first bipolar.

vertical transistor having three zones in which a first of said zones belongs to the substrate region and a second of said zones which forms the base of the first transistor belongs to one of the said local regions, and in which the semiconductor layer configuration extends partly over the insulting domains to form connection tracks and partly over the said local region to which the base of the first transistor belongs, which is characterizec in that a part of the semiconductor layer configuration which is situated on the said local region to which the base zone of the first transistor belongs is mainly mono crystalline and forms a third zone of the first transistor.

It is of advantage to deposit the said semiconductor layer in such circumstances that the growth occurs mainly monocry stalline on the surface parts which are not occupied by the insulating domains so that after providing the said configuration the monocrystalline third zone or third zones of the first transistor(s) and polycrystalline conductor tracks which are elements of the first interconnection level are simultaneously obtained. The said tracks are then connected to a complementary interconnection network via suitable apertures in an insulating layer which separates said network from the polycrystalline conductor tracks.

A circuit arrangement in accordance with the first aspect of the invention presents the advantage that the structure thereof is suitable to be manufactured according to a simplified method with a small number of steps.

According to a further aspect of the invention there is provided a method of manufacturing an integrated circuit, which is characterized in that on a surface part of a substrate, which surface part is of a first conductivity type, a number of local regions of the second conductivity type and domainS of insulating. material adjoining said local regions are provided, after which a semiconductor layer is deposited from the vapour phase on at least a part of the said regions and the said domains under such conditions that the layer grows mainly monocrystalline on semiconductor surfaces exposed to the vapour phase, impurities which are characterisitc of t:e first condictivity type being incorpooatec in the layer, and the said semiconductor layer configuration to which belongs the said layer portion which forms the third region of the first transistor being formed from the said layer.

The wiring facilities of a double layer inter connection, for example, are obtained sub stantially by means of a method in accordance with the invention by using processes which normally result in a circuit having a single interconnection level. Because the number of manufacturing steps has been reduced, the tolerances between the elements may also be reduced and a more compact circuit be obtained. From this it follows in particular that the manufacturing yield of an integrated circuit in accordance with the invention is higher and its cost-price is lower. The danger of incorporating manufacturing defects has been minimized, for which reason the invention serves as a base for the manufacture of more complex monolithic integrated circuits, that is to say with a larger number of elements and this in favourable economical conditions.

An integrated circuit in accordance with the first aspect of the invention has the additional advantage that the third zone of the first transistor has a connection which is more reliable and can be obtained in a simple manner.

An important form of an integrated circuit in accordance with the first aspect of the invention is characterized in that two adjacent zones of the local regions form the emitter and collector zones of a second horizontal bipolar transistor, in which the first and the second transistors are complementary to each other and in which the emitter and collector zones of the second transistor are separated from each other by an intermediate region of the first conductivity type which forms the base of the second transistor, and in which the part of the substrate region which supports the emitter and collector zones of the second transistor extends up to said zones and has an impurity doping concentration which is larger than that of the region of the first conductivity type.

A preferred form of an integrated circuit in accordance with the first aspect of the invention is characterized in that the said local regions of the second conductivity type are bounded laterally at least partly by a band of insulating material which forms at least a part of the domains of insulating material and which extends in the depth up to the substrate region, the said conductor track which belongs to the semiconductor layer configuration extending mainly over the insulating band.

By using this form of an integrated circuit one benefits not only by the advantages which are inherent in said isolation technique but also by a great simplification during the manufacture of the circuit.

According to a further aspect of the invention there is provided an integrated circuit comprising a semiconductor body having a substrate region of a first conductivity type which supports a number of local regions of the second conductivity type which is opposite to the first, in which the said local regions have substantially the same thickness, domains of insulating material being present which adjoin the said local regions, and a semiconductor layer configuration of the first conductivity type being resent, the circuit comprising at least a first bipolar vertical transistor having three zones, in which a first of the three zones belongs to the substrate region, a second of the said zones which forms the base of the said transistor belongs to one of the said local regions, and a third of the said zones which is of the first conductivity type is situated on the same local region which separates the said third zone from the substrate region, in which the local regions of the second conductivity type are bounded at least partly by a band of insulating material and the said band forms at least a part of the said domains of insulating material, which is characterized in that the said semiconductor layer configuration extends partly over the said insulating domains to the said base zone of the first transistor being situated in contact with the said third zone, the said band of insulating material extending in depth down to a highly doped part of the substrate region.

The invention is not restricted to circuit arrangements of the 12 L type, but also includes within its scope other bipolar transistor circuits.

Embodiments of the invention will now be described, by way of example, with reference to the accompanying drawings.

Figure 1 is a plan view of a part of an integrated circuit in accordance with the invention.

Figure 2 is a diagrammatic sectional view of the same part of the integrated circuit taken on the line AA of Figure 1.

Figure 3 is a sectional view of another detail of the same part of the integrated circuit in accordance with the invention taken on the line BB of Figure 1.

Figures 4a to 4dl show diagrammatically the principal steps of a method of manufacturing an integrated circuit in accordance with the invention and; Figure 4b2 to 4d2 illustrate a modified method of manufacturing another form of integrated circuit in accordance with the invention.

Figure 1 relates to an integrated circuit of the "I L" type a part of which is shown in plan view. In this example the semiconductor substrate is monocrystalline silicon of the n-type having a high concentration of doping impurities. In the proximity of the active or major surface, the semiconductor body has a number of local regions of substantially the same thickness the conductivity type of which is opposite to that of the substrate, so in this example of the type. Two of these local regions are denoted by 11 and 12 in Figure 1.

The local region 11 is isolated electricaiiy from the remainder of the circuit, first of all by the p-n junction which the region 11 forms with the adjoining part of the semiconductor substrate of the n-type which underlies the region 11 and which is not visible in the plane of Figure 1, secondly by the p-n junction between the regionl 1 and the n-type region 13 situated beside said region 11, and thirdly by the laterally insulating bands 14 which in this example are of silicon oxide and which extend in the depth down to the substrate region 27.

In a corresponding manner the local region 12 is isolated electrically by p-n junctions with the substrate region 27 and the region 13 which are both n-type, and by the insulating bands 14.

A first bipolar npn transistor has a first zone which in this case forms the emitter and which belongs to the substrate region 27 (Figure 2).

The second zone which forms the base of the npn transistor belongs to the local region 11.

Said transistor has two collectors which are formed by the n-type zones 15 and 16 extending over the local region 11.

In accordance with the invention, the conductor tracks 17 and 18 are parts of a semiconductor layer configuration, in this case a thin layer of n-type silicon, which extends over the domains of insulating material which are formed by the insulating bands 14.

In accordance with the first aspect of the invention, the conductor tracks 17 and 18 continue into the collector zones 15 and 16, respectively, which themselves are also formed by layer portions of the said semiconductor layer configuration.

Figure 1 also shows a second transistor which is complementary to the first transistor, namely a pnp transistor. In this example the emitter of said second transistor is formed by the local region 12. The collector belongs to the local region 11. This region 11 thus is common to the collector of the second transistor and the base zone of the first transistor.

The base zone of the pnp transistor is formed by the region 13 which is situated as a band between the emitter and the collector. The pnp transistor is a socalled lateral transistor.

Figure 1 also shows part of a complementary connection network, which network is formed by metal tracks of, for example, aluminium, the thickness of which is approximately one micrometre. The track 19 is connected to the local region 12 in the contact aperture 20. The track 21 is connected to the local region 11 in the aperture 22, and the track 23 is connected to the track 17 in the aperture 24. The said apertures 20,22 and 24 are provided in a layer of insulating material 30 in Figures 2 and 3. In the present example the layer 30 consists of silicon oxide and extends over the surface of the whole wafer or slice below the network of metal tracks, except in the places of the contact apertures. The track 23 crosses the semiconductor track 18 without contacting same in the region 25.

Figure 2 is a diagrammatic sectional view of the part of the integrated circuit of Figure 1 taken on the line AA. In this example the local regions 11 and 12 are islands which are doped with boron and which have a thickness of approximately 0.6 micrometre. Provided on the n-type silicon substrate is an epitaxial layer of the same conductivity type and of a resistivity in the order of 0.5 to 1 ohm. cm and a thickness which is substantially equal to the thickness of the local regions 11 and 12. What remains of said epitaxial layer after the formation of the local regions 11 and 12 is only the band-like region 13 adjoining said regions. The insulating band 14 is situated around the local regions 11 and 12 and adjoins same except at the area where the region 13 is present. The thickness of the insulating band 14 is larger than that of the said regions 11 and 12. An isolation with sunken or inset oxide of this type can be obtained by means of the known method of local oxidation of silicon, according to which method a silicon nitride mask is used against the thermal oxidation, while via apertures in the mask the oxidation is obtained in the areas where this is desired.

In accordance with the first aspect of invention which presents the advantage that a large number of elementary regions can be formed which have different functions and for which the same number of operations is used, the collector zones 15 and 16 of the npn transistor are each formed in a monocrystalline layer portion of the said semiconductor layer configuration, which layer portion is situated on and directly adjoins the region 11.

Outside the parts which form the zones 15 and 16, the semiconductor layer configuration is supported by the thick oxide bands 14 so thai due to the manner of providing which will be explained hereinafter the material of the said layer is generally polycrystalline at that area.

Figure 2 shows the metal tracks 19 and 21 at the area where they contact the local regions 12 and 11, respectively, via the apertures 20 and 22 which are provided in the insulating laye layer 30, said insulating layer in this example being a 0.1 it thick silicon oxide layer.

Figure 3 is a sectional view of a part of the circuit arrangement shown in Figure 1 taken on the line BB. The semiconductor tracks 17 and 18 are supported by the thick oxide band 14 at the level of said section BB. Figure 3 shows both a contact between a metal track 23 and a semiconductor track 17 and an isolated crossing of connections or cross-over. The insulating layer 30 insulates the metal track 23 electrically from the semiconductor track 18 so that an isolated crossing of connections is formed. On the other hand, an aperture 24 is provided in the insulating layer 30 so as to obtain a conductive connection between the metal track 23 and the semiconductor trackl7.

It is to be noted that the emitter of the npn transistor can be connected directly to a large number of other emitters of similar npn transistors. This can be realized with the substrate which, for example, may be connected to a reference potential. In the example the base of the pnp transistor is also connected to said potential because the band-like region 13 is con nected directly to the substrate region 27.

It is to be noted that many variations may bt applied to the circuit arrangement described without departing from the scope of this invention.

For example, the values of the thickness and of the resistivity of the epitaxial layer may be changed and adapted to the desired electrical properties of the circuit. In addition, the local regions 11 and 12 can be obtained in a manner differing from local doping. The n-type sub strate, for example, may be covered with an epitaxial p-type layer instead of with an n-type layer and the region 13 (Figures 1 and 2) be tween the local regions 11 and 12 may then be obtained by means of, for example, ion implantation of an n-type impurity succeeded by annealing under usual conditions. The ion implantation is carried out under such conditions that the epitaxial layer which is of the p-type is converted throughout the depth thereof into the n-type and that the width and the impurity concentration of the region 13 enable the pnp transistor to have a proper gain. Preferably, the impurity concentration of the region 13, at least in certain places, is lower than that of the part of the substrate region 27 adjoining the local regions, so that the injection of the emitter will occur mainly in a lateral direction towards the collector.

The example described has a homogeneous substrate 27, which presents the advantage of simplicity. Alternatively, only the surface parts of the substrate may be of the n-type in which the remainder of the substrate may be of the p-type or in which said surface parts may be isolated by a layer of insulating material. The said surface parts of the substrate which then form the substrate region, may be obtained by means of a homogeneous layer, or a double layer- or a multi-layer structure- which permits particular requirements to be satisfied as regards the operation and performance of the circuit and of applying different reference potentials to components or parts of the circuit.

Figure 1 shows semiconductor tracks 17 and 18 which continue into the layer portions 15 and 16, respectively, which is a particularly simple embodiment of the invention. Interrupt ing said tracks and replacing a part thereof by a metal track would be within the scope of this invention. However, the semiconductor layer configuration forms at least a connection track on the insulating domains and at least a third zone of the npn transistor on a local region.

An example of isolated crossing at two con nection levels has been described with reference to Figure 3 in which a semiconductor track is present at the first level. Said semiconductor track may be connected, for example, at both ends to a metal track of the complementary net work to form an isolated crossing with another metal track of the said network.

As regards the means which are used to iso late the local regions 11 and 12, a p-n junction might be used, instead of a thick oxide, to lat erally bound the said regions. The isolating bands of the n-type which are situated outside said local regions are then covered with an insulating layer in the areas occupied by the tracks of the semiconductor layer configuration in such manner that said configuration is isolated from the n-type material froming the said bands, and the insulating layer adjoins the local regions.

The insulating layer 30 shown in Figures 2 and 3 may consist, of an insulating material othe than silicon, for example silicon nitride or aluminium oxide, or be composed of several successive layers of different insulating materials.

The network of metal tracks to connect the elements of the circuit which is complementary to the semiconductor layer configuration, may also consist of a suitable material other than aluminium.

The integrated circuit described has a single level of metal connections and, taking into account the layer configuration, presents integration possibilities for complex functions which are comparable to those which are coupled to the use of interconnections at two levels, no extra operations being necessary to obtain the second level.

However, without departing from the scope of this invention, the integrated circuit may alternatively have several levels of metal tracks so that even more complicated circuits can easily be connected together.

Finally, as regards the transistors described, the invention may of course also be applied if the collector zone of the pnp transistor is not formed in the same local region as the base zone of the npn transistor. Furthermore, the polarities of the transistors need not be as indicated in the example and they may be re versed by reversing the conductivity types of all zones of the device. Finally the example described has been chosed from the "12 L" family of circuits but an integrated circuit in accordance with the invention is more gener ally suitable for circuits having complementary bipolar transistors.

Figures 4a to 4dl relate to a preferred method of manufacturing an integrated circuit in accordance with the invention.

The preparatory stage of a method in accor dance with the invention consists of obtaining a number of local regions of the p-type and domains of insulating material adjoining said regions on or in a substrate ofwhich at least a surface part is of the n-type semiconductor material.

In the first example a slice of n-type silicon having a resistivity of from 8 to 14.10-3 ohm.

cm is covered with an epitaxial layer also of the n-type whose resistivity is between 0.5 and 1 ohm.cm and whose thickness is approximately 0.6 micrometre. In Figure 4a the surface part of the slice which serves as a substrate region is referenced 54. The local regions 55 and 56 which are of the p-type are simultaneously dif fused in the epitaxial layer, a band-shaped regior region 58 of the original material of the epitaxial n-layer remaining, which region separates the said local regions 55 and 56 from each other. The remaining part of the circum ference of said regions 55 and 56 adjoins the band 57 of thick oxide which is obtained with the known and already mentioned technique of local oxidation of the silicon. A structure which is analogous to that of Figure 4a can be obtained obtained, for example, by forming the region 58 by implantation of n-type impurity ions in an epitaxial p-type layer. The local regions 55 and 56 then consist of separate parts of the p-type epitaxial layer.

Finally, the local regions 55 and 56 alterna tively may be isolated from the remainder of the circuit by a p-n junction. In this case it is preferable to provide the isolating bands of the n-type in the same manner as the region 58 and simultaneously therewith. In this case the num ber of operations is comparatively small and the overall number of necessary masks is then only four.

In the latter case, by choosing a sufficiently large width for the isolating bands, the gain of the parasitic horizontal pnp transistor which is formed between two local regions which should be isolated from each other may be small as compared with the gain of the desired lateral transistor. With each of these possibilities of manufacturing an integrated circuit in accor dance with the invention the local regions are exposed at least partly, the bands adjoining the said regions being formed from or being covered with a layer of insulating material.

In a method in accordance with the inven tion, a thin silicon layer of the n-type is deposi ted on the whole surface of the body and, for example has a resistivity in the order of 2 to 4.10- ohm.cm and a thickness of 0.5 to 0.8 micrometer. The said layer is deposited in such conditions that the growth thereof is mainly monocrystalline on the free semicon ductor surface areas. For this purpose the depo sition temperature is sufficiently high, for example 1050 C or more if silane (SiH4) is used as a silicon source, or 1100 C or more if trichlorosilane (SiHCl4) is used. Said silicon layer proves to have a polycrystalline or amorphous structure in the areas where the layer is deposited on material having a less organized structure, for example that of silicon oxide.

The deposited layer is subjected to a photolithographic and etching treatment in a manner known in semiconductor technology, the des ired configuration remaining.

The said configuration comprises on the one hand polycrystalline connection tracks which are supported by thick oxide bands, for example the track 61 in Figure 4b 1, and on the other hand monocrystalline layer portions which are supported by local regions, for example the layer portion 62 which is supported by the local region 55.

In the example, region 55.

A thermal treatment is then carried out, for example, at 10000C, so that a part of the impurities diffuses from the part 71 into the local region 55 and an n-type region is formed which in Figure 4c2 is denoted by 72. The duration of the treatment is adjusted so that the depth of the diffusion is approximately 0.4,um.

An insulating layer 73 is then provided on the surface of the slice and the aperture 74 and 75 necessary for the contacts with the complementary network of metal tracks are provided in said layer.

Figure 4d2 finally shows the device as it is obtained after providing the aluminium con nection network of which the track 76 is con nected to the local region 55 and the track 77 is connected to the local region 56.

Figure 4d2 shows an npn transistor having a surface collector and an emitter zone which belongs to the surface part 54 of the substrate, and a base zone which belongs to the local region 55. The collector zone is formed by the region 72 which underlies and is in direct contact with the layer portion 71.

The structure also comprises a lateral pnp transistor of which the emitter zone is formed by the local region 56, the base zone is formed by the band 58 and the collector zone is formed by a part of the local region 55. For the satisfactory operation of this lateral pnp transistor is of importance that the isolation bands 57 extend down to or into the more highly doped substrate region and the emitter and collector zones 56, 57 are separated from each other laterally by a less highly doped region 58. The zones 55,56 and 58 of the transistor thus are situated collectively within a common isolating ring 57.

The invention is not restricted to the embo diments described. Many variations are pos sible to those skilled in the art without depart ing from the scope of this invention. For example, instead of silicon other semiconductor materials, for example germanium or AIIIBV compounds, may alternatively be used.

WHAT WE CLAIM IS: 1. An integrated circuit comprising a semi conductor body having a substrate region of a first conductivity type which supports a number of local regions of the second conductivity type which is opposite to the first, which local regions have substantially the same thicknesses, domains of insulating material being present which adjoin the local regions, and a semi conductor layer configuration of the first conductivity type being present, the integrated circuit comprising at least a first bipolar vertical transistor having three zones, in which a first of the said zones belongs to the substrate region and a second of the said zones which forms the base of the first transistor belongs to one of the said local regions, in which the semi conductor layer configuration extends partly over the said insulating domains to form connection tracks and partly over the said local region to which the base of the first transistor belongs, characterized in that a part of the semiconductor layer configuration which is situated on the said local region is mainly monocrystalline and forms a third zone of the first transistor.

2. An integrated circuit as claimed in Claim 1, characterized in that two adjacent zones of the local regions form the emitter and collector zones of a second horizontal bipolar transistor, in that the first and the second bipolar transistors are transistors which are complementary to each other and in which the emitter and collector zones of the second transistor are separated from each other by an intermediate region of the first conductivity type which forms the base of the second transistor, and in that the part of the substrate region which supports the emitter and collector zones of the second transistor extends up to said zones and has an impurity doping concentration which is larger than that of said region of the first conductivity type.

3. An integrated circuit as claimed in Claim 1 or Claim 2, characterized in that the said local regions of the second conductivity type are bounded laterally at least partly by a band of insulating material which forms at least a part of the said insulating domains and which extends in the depth down to the substrate region, the said connection track which belongs to the semiconductor layer configuration extending mainly over the insulating band.

4. An integrated circuit as claimed in any of Claims 1 to 3, characterized in that at least a complementary network of conductor tracks is present which is separated from the said semiconductor configuration by at least one insulating layer in certain areas, in which a track of the said semiconductor layer configuration which is supported entirely by one of the said domains of insulating material is connected in two places to the complementary network of conductor tracks so as to form a crossing connection with a track of the cm.- plementary network.

5. An integrated circuit comprising a semiconductor body having a substrate region of a first conductivity type which supports a number of local regions of the second conductivity type which is opposite to the first, in which the said local regions have substantial;y the same thickness, domains of insulating material being present which adjoin the said local regions, and a semiconductor layer con figuration of the first conductivity type being present, the circuit comprising at least a first bipolar vertical transistor having three zones, in which a first of the three zones belongs to the substrate region, a second of the said zones which forms the base of the said transistor belongs to one of the said local regions, and a third of the said zones which is of the first

**WARNING** end of DESC field may overlap start of CLMS **.

Claims

**WARNING** start of CLMS field may overlap end of DESC **. region 55. A thermal treatment is then carried out, for example, at 10000C, so that a part of the impurities diffuses from the part 71 into the local region 55 and an n-type region is formed which in Figure 4c2 is denoted by 72. The duration of the treatment is adjusted so that the depth of the diffusion is approximately 0.4,um. An insulating layer 73 is then provided on the surface of the slice and the aperture 74 and 75 necessary for the contacts with the complementary network of metal tracks are provided in said layer. Figure 4d2 finally shows the device as it is obtained after providing the aluminium con nection network of which the track 76 is con nected to the local region 55 and the track 77 is connected to the local region 56. Figure 4d2 shows an npn transistor having a surface collector and an emitter zone which belongs to the surface part 54 of the substrate, and a base zone which belongs to the local region 55. The collector zone is formed by the region 72 which underlies and is in direct contact with the layer portion 71. The structure also comprises a lateral pnp transistor of which the emitter zone is formed by the local region 56, the base zone is formed by the band 58 and the collector zone is formed by a part of the local region 55. For the satisfactory operation of this lateral pnp transistor is of importance that the isolation bands 57 extend down to or into the more highly doped substrate region and the emitter and collector zones 56, 57 are separated from each other laterally by a less highly doped region 58. The zones 55,56 and 58 of the transistor thus are situated collectively within a common isolating ring 57. The invention is not restricted to the embo diments described. Many variations are pos sible to those skilled in the art without depart ing from the scope of this invention. For example, instead of silicon other semiconductor materials, for example germanium or AIIIBV compounds, may alternatively be used. WHAT WE CLAIM IS:

1. An integrated circuit comprising a semi conductor body having a substrate region of a first conductivity type which supports a number of local regions of the second conductivity type which is opposite to the first, which local regions have substantially the same thicknesses, domains of insulating material being present which adjoin the local regions, and a semi conductor layer configuration of the first conductivity type being present, the integrated circuit comprising at least a first bipolar vertical transistor having three zones, in which a first of the said zones belongs to the substrate region and a second of the said zones which forms the base of the first transistor belongs to one of the said local regions, in which the semi conductor layer configuration extends partly over the said insulating domains to form connection tracks and partly over the said local region to which the base of the first transistor belongs, characterized in that a part of the semiconductor layer configuration which is situated on the said local region is mainly monocrystalline and forms a third zone of the first transistor.

conductivity type is situated on the same local region which separates the said third zone from the substrate region, in which the local regions of the second conductivity type are bounded at least partly by a band of insulating material and the said band forms at least a part of the said domains of insulating material, characterized in that the said semiconductor layer configuration extends partly over the said insulating domains to form at least a connection track and partly over the local region, the said base zone of the first transistor being situated in contact with the said third zone, the said band of insulating material extending in depth down to a highly doped part of the substrate region.

6. A method of manufacturing an integrated circuit as claimed in any of Claims 1 to 4, characterized in that on a surface part of a substrate, which surface part is of a first conductivity type, a number of local regions of the second conductivity type and domains of insulating material adjoining said local regions are provided, after which a semiconductor layer is deposited from the vapour phase on at least a part of the said regions and the said domains under such conditions that the layer grows mainly monocrystalline on semiconductor surfaces exposed to the vapour phase, impurities which are characteristic of the first conductivity type being incorporated in the layer, and the said semiconductor layer configuration to which belongs the said layer portion which forms the third region of the first transistor being formed from the said layer.

7. A method as claimed in Claim 6 of manufacturing the integrated circuit as claimed in Claim 2, characterized in that the said local regions are formed by providing on the surface part of the substrate an epitaxial layer of the first conductivity type, in that the impurity concentration of said epitaxial layer is lower than that of the surface part of the substrate, in that local regions of the second conductivity type are obtained by locally overdoping the epitaxial layer with impurities which are characteristic of the second conductivity type down to a depth which is at least equal to the thickness of the epitaxial layer, and in that at least a number of said regions adjoin and are separated from each other by an intermediate region of the first conductivity which still consists mainly of the original material of the epitaxial layer.

8. A method as claimed in Claim 6 of manufacturing an integrated circuit as claimed in Claim 2, characterized in that the said local regions are manufactured by providing an epitaxial layer of the second conductivity type on at least the surface part of the substrate, an intermediate region of the first conductivity type which separates two adjacent local regions from each other is formed by ion implantation of impurities which are characteristic of the first conductivity type, and that the epitaxial layer is overdoped locally throughout its thickness and in which the impurity concentration in the overdoped region is maintained lower than the concentration of the surface part of the substrate.

9. An integrated circuit manufactured by a method claimed in any of Claims 6 to 8.

10. An integrated circuit substantially as herein described with reference to Figures 1 to 3 of the accompanying drawings.

11. A method of manufacturing an integrated circuit substantially as herein described with the reference to Figure 4a and Figures 4bl to 4dl or Figures 4b2 to 4d2.