GB1568501A - Field-effect transistors - Google Patents
Field-effect transistors Download PDFInfo
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- GB1568501A GB1568501A GB5640/78A GB564078A GB1568501A GB 1568501 A GB1568501 A GB 1568501A GB 5640/78 A GB5640/78 A GB 5640/78A GB 564078 A GB564078 A GB 564078A GB 1568501 A GB1568501 A GB 1568501A
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- 230000005669 field effect Effects 0.000 title description 3
- 239000011159 matrix material Substances 0.000 claims description 40
- 239000000758 substrate Substances 0.000 claims description 18
- 238000000034 method Methods 0.000 claims description 8
- 239000004065 semiconductor Substances 0.000 claims description 8
- 230000008901 benefit Effects 0.000 claims description 7
- 238000002347 injection Methods 0.000 claims description 6
- 239000007924 injection Substances 0.000 claims description 6
- 210000000352 storage cell Anatomy 0.000 claims description 6
- 230000000903 blocking effect Effects 0.000 claims description 5
- 238000009792 diffusion process Methods 0.000 claims description 5
- 239000012212 insulator Substances 0.000 claims description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- 239000004411 aluminium Substances 0.000 claims description 3
- 230000005684 electric field Effects 0.000 claims description 3
- 230000006698 induction Effects 0.000 claims description 3
- 230000004048 modification Effects 0.000 claims description 2
- 238000012986 modification Methods 0.000 claims description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 2
- 229920005591 polysilicon Polymers 0.000 claims description 2
- 210000000582 semen Anatomy 0.000 claims 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000009877 rendering Methods 0.000 description 2
- 206010022998 Irritability Diseases 0.000 description 1
- 235000013290 Sagittaria latifolia Nutrition 0.000 description 1
- 230000009471 action Effects 0.000 description 1
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- 230000015556 catabolic process Effects 0.000 description 1
- 235000015246 common arrowhead Nutrition 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
- G11C16/0416—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
- H01L29/7881—Programmable transistors with only two possible levels of programmation
- H01L29/7884—Programmable transistors with only two possible levels of programmation charging by hot carrier injection
- H01L29/7885—Hot carrier injection from the channel
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Non-Volatile Memory (AREA)
- Electrodes Of Semiconductors (AREA)
- Read Only Memory (AREA)
Description
(54) IMPROVEMENTS IN OR RELATING TO
FIELD-EFFECT TRANSISTORS
(71) We, SIEMENS AKTIEN
GESELLSCHAFT, a German Company of
Berlin and Munich, German Federal Republic, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed to be particularly described in and by the following statement:
The present invention relates to storage field-effect transistors (FETs) and is an improvement in or modification of the invention described and claimed in our co-pending Application No 36983/75 (Serial
No 1,517,927 Our co-pending Application No 36983/75 (Serial No 1,517,927) claims an n-channel storage FET having a source and a drain formed in a p-type substrate, a channel zone in said substrate extending between said source and drain and having a length of less than 10F, and a floating storage gate entirely surrounded by an insulator on said substrate, wherein said channel zone and said storage gate are so constructed and arranged that said storage gate can be programmed in use by negatively charging it by channel electron injection, and the negative charge so produced on said storage gate can act to reduce the source-drain current of said transistor by electrostatic induction.
The charging of the storage gate is effected by channel injection of electrons, i.e. by electrons which are strongly accelerated and thereby heated in their own conductive channel between the source and drain of the
FET, and which, on account of their heating by an electric field acting in the source-drain direction, overcome the energy threshold of the conductivity band of the insulator and thus are able to reach the storage gate. Such a channel injection is employed for the programming of the FET (i.e. charging of the storage gate) so that, after such charging, the storage gate has a restricting action on the source-drain path because of its negative charge which--ts o reduce the source-drain current of the transistor, and usually to eliminate it completely. With a storage FET of this type, in the unprogrammed state the channel is of the depletion type.
As described in Application No 36983/75 (Serial No. 1,517,927), the storage FET may comprise an additional, controllable control gate which possesses a connecting terminal and which exerts a capacitive influence upon the storage gate. The storage FET of Application No 36983/75 (Serial No. 1,517,927 is particularly suitable for use in the programme stores of a telephone exchange system.
It is an object of the present invention to provide a storage FET which possesses a storage gate and a control gate which is so constructed that only extremely low operating voltages are required, that the electric programmability is maintained, and that the programming voltage which, as is known, is required for programming and which must be higher than the normal operating voltage. does not entail any risk of breakdown occurring along the source-drain path of the
FET under the influence of this higher voltage. The FET should also possess a high operating speed, and should be suitable for use in a telephone exchange system.
Double-diffused MOS-FETs are already known in which the channel length is determined by the thickness of a P-doped zone which is formed by means of doublediffusion in an N-doped substrate so as to be located immediately beside and below an
N±doped zone (see "Electronics', Feb.
1971, pages 99 to 104). Such D-MOS-FETs, as they are called, can be produced with a channel length of about 1 micron. They also have a high operating speed. The known
D-MOS-FETs, however, have the disadvantage that they possess only one gate and are therefore not suitable for use as storage
FETs, if the storage cell which must in each case accommodate one bit, has to consist of one storage FET only. Moreover, these known D-MOS-FETs cannot be used to construct stores which are electrically programmable. It is a further object of the invention to provide a storage transistor of the kind referred to above which can be made using the known technique for the construction of D-MOS-FETs.
According to the invention there is provided an N-channel storage FET comprising a source and a drain formed in a substrate, a floating storage gate entirely surrounded by an insulator on said substrate, and an additional controllable control gate provided with a connecting terminal whereby a potential can be applied to said control gate to capacitively influence said storage gate, the arrangement being such that in use said storage gate is programmed by negatively charging it by channel injection using electrons which are heated by being strongly accelerated in an electric field in a conductive channel between said source and drain, the negative charge thus produced on said storage gate, after charging and in particular at the time of read-out acting by electrostatic induction on the channel of said FET to reduce or wholly inhibit the drain-source current of the transistor, wherein said storage FET is formed as a D-MOS-FET: wherein said source and drain are formed by respective N±doped zones in an N-doped substrate, and the N±zone forming said source is surrounded by a P-doped zone extending below and beside said source zone. the channel length of the FET being determined by the width of said P-doped zone at the substrate surface; and wherein said drain zone is spaced from said P-doped zone by a distance which forms a drift path and is at least equal to the width of said
P-doped zone in the substrate surface adjacent said drift path.
Owing to the fact that the storage FET of the invention is constructed as a D-MOS
FET with two gates, the desired advantages of D-MOS-FETs are achieved, so that a channel length of the order of 1 micron can be achieved, resulting in advantages in respect of the operating voltages required and operating speed. Because of the presence of two gates, one of which is a floating storage gate, the D-MOS-FET can be used
as a programmable storage FET which can
by itself form a storage cell. Finally. because
of the presence of the drift path between the
P-zone and the drain terminal, a break
through along the source-drain path is un
likely despite loading by the programming
voltage which is somewhat higher than the
normal operating voltage. It will be under
stood that a read-out source-drain voltage of
about 5 V is sufficient for read-out, whereas a programming source-drain voltage of about 12 V is required for programming.
A storage FET according to the invention can conveniently be erased by irradiation with ultraviolet light. This is also the case when a plurality of such storage FETs are arranged on a common semiconductor carrier. This is facilitated if the storage gate of each FET extends beyond the control gate terminal by which it would otherwise be covered. It is then ensured that the ultraviolet light acts upon the appropriate zones of the FET, and that the time required for erasure is kept short. It has been found that it is sufficient for this purpose if the storage gate extends beyond the control gate terminal only on the side facing the source terminal. It can then also be arranged that the storage gate does not cover the major part of the drift path. This has the advantage of avoiding the danger of a charged storage gate being undesirably discharged when a programming sequence is carried out on an adjacent FET located on the side of the drain terminal. So-called "neighbouring word disturbance" can thus be avoided within a store having a plurality of FETs according to the invention. The storage
FETs in accordance with the invention can be arranged on a semiconductor carrier in the form of a matrix, and can thus provide an electronic store produced using the integrated technique.
The invention will now be further described with reference to the drawings, in which :
Figure 1 is a schematic side-sectional view of one form of storage FET in accordance with the invention;
Figure 2 is a schematic plan view of the
FET of Figure 1;
Figure 3 is a schematic plan view of part of a store using storage FETs in accordance with the invention; and
Figure 4 is a circuit diagram of a store using storage FETs in accordance with the invention, and the associated control components.
In the storage FET illustrated in Figure 1, a double-diffusion process is used to produce by diffusion in an N-doped substrate a source in the form of an N±doped zone, and a P-doped zone P which immediately surrounds the source N+. The channel length of the FET is set at a value of 1 micron by the thickness of the zone P. A drain zone is also produced by diffusion as an N±doped zone in the surface of the substrate. The distance r between the channel constituted by the thickness of the zone
P and the drain zone, and which indicates the length of the drift path between the
channel and the drain, is considerably greater than the thickness of the P zone. A storage gate G1 and a control gate G2 are arranged in an insulated layer of silicon dioxide above the surface of the N-doped substrate.
In the FET shown in Figure 1, the storage gate G1 is designed to be relatively large.
On both the source side and the drain side it projects beyond the control gate which lies above it and by which it would otherwise be covered. However, if desired, the storage gate G1 can be made considerably smaller, as already explained above. For example, it is sufficient for it to extend only over the length indicated by the reference gl. In this case, it projects beyond the control gate G2 only on the side facing towards the source zone and covers only a very small part of the drift path r. In this way the advantages referred to above are achieved.
Figure 2 shows in plan view the position of the gates G1 and G2 shown in Figure 1, and also of other terminals. It will be seen that the storage gate G1 projects beyond the control gate G2 on both the source and drain sides, but is otherwise covered by the gate G2. Finally the drift path R is also shown.
When a FET as shown in Figures 1 and 2 is arranged with further such FETs on a semiconductor carrier in the form of a matrix, a store arrangement, as illustrated in
Figure 3, can be formed. The source zones are connected in rows by matrix lines Z1 and Z2 which are in each case diffused into the substrate, and are arranged in parallel.
The control gates G2 are also connected in rows by parallel matrix lines W1....W4 which consist of polysilicon. The storage gates G1 are indicated by the type of shading indicated at G1 in the key given in the lower left-hand corner of the Figure. The drain zones are connected in columns via contact areas H by means of matrix lines bl and b2 which consist of aluminium and intersect the other matrix lines at right-angles. The areas at which diffused-in layers are arranged to form the lines Z1 and Z2 are indicated bv the shading indicated by Di in the key. The position of the matrix lines hl and b2 consisting of aluminium is indicated by broken lines, as indicated by the symbol Al in the key. For further details of the arrangement of such a matrix, see Siemens
Forsch. -und Entwickel-Ber., Vol. 4 (1975)
No 6, pages 345 to 351, in particular pages 350 and 351.
It is already known to construct a store from storage cells which are arranged in matrix formation and which each contain only a single FET, the control gate of which is in each case connected to a control line in a first matrix dimension, and the drain terminal of which is in each case connected to a control line in a further matrix dimension, and in which all the source terminals of the storage FETs are connected to a common circuit point (see German Patent Specification No 2,445,078). Expediently, in addition to the storage FETs, the associated control component is also arranged on the same semiconductor carrier. Data words comprising a plurality of bits are read out with the aid of decoders. By means of a decoder for the first matrix dimension, a single control line is selected for word selection. By means of a decoder for the further matrix dimension. in the word selection in respect of each bit position, one of a plurality of control lines provided for the bit positions in the word line selected is simultaneously selected (see IEEE Journal of
Solid-State Circuits, Vol. SC-11. No 5,
October 1976, pages 614 to 621, in particular page 617). The bits belonging to a word are in each case supplied via output terminals which are individually assigned to the bit positions of the words and which are each connected to the control lines associated with the particular bit position via decoupling switching means. An electronic store of this type can be constructed using storage
FETs in accordance with the invention, which are constructed in the D-MOStechnique and which are employed as storage cells; in this case, a store is formed which has all the advantages of the storage
FETs according to the invention.
In the example of such a store using storage FETs in accordance with the invention, which is illustrated in Figure 4, the output terminals are additionally used for the write-in of data words. The control lines via which the data words are supplied on read-out are connected to the output terminals via respective transistors serving for decoupling purposes and via transistor amplifiers. For the introduction of a data word, the transistor amplifiers are blocked by means of blocking circuits, whereas on read-out, additional transistors specifically provided for the introduction of data words are blocked. The blocking circuits are provided for each bit position of the data words and are constructed using transistors each of which is connected to an additional line corresponding to the control lines of the further matrix dimension. The additional exploitation of the output terminals in this manner has the advantage that the number of terminals required on the same semiconductor carrier is not increased.
The electronic store illustrated in Figure 4 comprises a plurality of sub-circuits whose circuit elements are fundamentally interconnected in a manner which is known per se.
The sub-circuit SP contains as storage components. storage FETs which are produced in accordance with the invention using the
D-MOS technique. and are used as storage cells. One of these transistors T11 will be considered as a typical example. The control gates of these transistors are connected to control lines sx1. . .sx256 in a first matrix dimension, to which lines an operating voltage U is connected via respective series resistors, the line sx1 in which the control gate of the transistor T11 is connected being connected to the operating voltage through a series resistor Tx1. The drain terminals of the storage FETs are connected to the control lines syl...sy256 to which the operating voltage U is likewise connected via respective series resistors, including the series resistor Tyl for the line syl in which the drain terminal of the transistor T11 is connected. The source terminals of all the storage FETs are connected to earth potential Um, as indicated for the transistor T11.
A further sub-circuit constitutes a decoder
Dx, by means of which one of the control lines sx1...sx256 is selected. This circuit Dx is assembled in known manner employing
D-MOS-FETs and is provided with input terminals A0...A7 via which a word address composed of eight bits can in each case be supplied. Each of these bits is assigned two lines, shown as extending vertically of this decoder which are connected to the gates of the FETs. The drain terminals of these FETs are connected to control lines in the first matrix dimension.
Earth potential Um is connected to all the source terminals. Each bit of a word address is assigned two of the aforementioned vertical lines, e.g. the bit supplied via the input terminal AOfs supplied with the two lines referenced aO and aO. Between each of these two lines and the input terminal A0 a respective D-MOS-FET is inserted, so that the one line is fed with the bit supplied in amplified form whilst the other line is fed with the bit supplied in amplified and inverted form. The remaining input terminals are similarly connected to the other vertical lines of the decoder Dx via respective FETs. A decoder Dy is also provided, which is also fundamentally assembled in known manner from D-MOS-FETs and which, in word selection. simultaneously selects one of a plurality of control lines in the further matrix dimension which are provided for each bit position, i.e. one of the control lines syl...sy256. The decoder
Dy consists of eight sub-decoders DyO...Dy7. When a word address is supplied to the input terminals A8...A12 of the decoder Dy, each of the sub-decoders selects one of the control lines Syl...sy256, so that a total of eight of these control lines is selected. These two decoders are used for the read-out and write-in of data words. The storage FETs. the control gates of which are connected to one and the same control line of the first matrix dimension. e.g. to the control line sxl, can therefore each accommodate a total of 32 data words each comprising 8 bits. Each of the sub-decoders DyO...Dy7 must select one from 32 control lines of the further matrix dimension. Thus the decoder DyO, for example, must select from the control lines syl...sy32. In the case of the decoder Dy, the input terminals
A8...A12 are connected via additional D
MOS-FETs to the associated control lines, similar to the arrangement in the decoder
Dx. The D-MOS-FETS which belong to the decoder Dy are inserted into the circuit in the same way as those of the decoder Dx.
The bits which in each case belong to a word are supplied via the output terminals BO. . .B7 which are individually assigned to the bit positions of the word. The output terminal B0 is assigned to the first bit position of the word and so on. A selection is made from the associated control lines syl...sy32 by means of the sub-decoder
Dyl. The bits to be supplied are forwarded by means of D-MOS-FETs T11...T132. each of which is individually connected by its gate to one of these control lines, and the drain terminals of which are connected together and to the operating voltage U via a series resistor. The interconnected drain terminals are connected via a transistor amplifier VO to the output terminal B0. The transistors Tl1. . .Tl32 serve as decoupling switching means. The transistor amplifier VO serves for additional amplification. It is constructed in known manner. It has a tri-state output connected to the output terminal BO.
The other bits of data words are supplied correspondingly via transistors and transistor amplifiers which include the transistors Tl224...Tl256 for the last bit and the transistor amplifier V7, the tri-state output of which is connected to the output terminal
B7. With the aid of a sub-circuit Q, which in the Figure is only shown very schematically, the operating potential U can be arranged to have a value corresponding either to the read-out voltage Ul or to the programming voltage Us. The read-out voltage Ul can, for example, be 5 V, and the programming voltage Us, for example 12 V. This subcircuit Q forms an electronic switch-over device which can be connected in known manner. However, it is unnecessary for this switch-over device to be arranged on the semiconductor carrier itself.
The key given at the left-hand side of
Figure 4 shows the circuit symbols conventionally used for D-MOS-FETs. The source terminals which are in all cases indicated by an arrow-head are always connected to earth potential Um. The key also indicates the symbol used for planar enhancement transistors employed in the circuit. The series resistors of the control lines and other lines, such as the series resistors Tyl, Tx1 and Tsx, can also be formed by depletion transistors with their gate connected to the source in each case. The circuit symbol employed for this purpose is also indicated in Figure 4.
The additional components of the store shown in Figure 4 which must be used for the read-out of data words have already been described above. The storage FETs which contain a data word are partially programmed and partially unprogrammed as described in Application No 36983/75. In the case of a programmed storage FET, the floating storage gate is negatively charged; it is thus not rendered conductive during a read-out process. The read-out voltage Ul connected to the control lines sxl and syl via the series resistors Tx1 and Tyl respectively for the read-out of data words therefore remains on the control line syl during the read-out of the storage FET T11 only when this storage FET T11 is programmed.
Otherwise, i.e. when it is not programmed, the FET is conductive and the read-out voltage Ul connected to the control line syl is discharged via the main current path of the storage FET T11, since the source terminal of the latter is connected to earth potential Um. If, on the other hand, the storage FET T11 is programmed, the readout voltage Ul supplied to the control line syl is maintained and acts via the decoupling transistor Tl1 and the transistor amplifier V0 on the output terminal B0 in a corresponding way. This is conditional upon none of the D-MOS-FETs connected to the control line syl being driven into the conductive state by the decoder DyO, which is the case when the decoder Dy has selected this control line. It is also conditional upon none of the D-MOS-FETs connected to the control line sxl being driven into the conductive state by the decoder Dx, which is the case when this control line has been selected by the decoder Dx. In this case, the other control lines sx2...sx256 are each conductively connected via the main current path of at least one D-MOS-FET of the decoder Dx to its source terminal which is connected to the earth potential Um. so that the read-out voltage Ul is discharged from these control lines. The discharge of the read-out voltage Ul from the relevant control lines in each case does not cause a short-circuit because of the presence of the associated series resistors. The read-out voltage thus only affects an output terminal in a specific way during the read-out of a word when the relevant storage FET is programmed. Otherwise the path leading to the relevant output terminal is connected to earth which results in a different voltage to normal being connected to the relevant output terminal. The transistor T11 which is being considered as an example is assigned to the first bit of a data word. The storage
FETs belonging to the other bits of the particular data word are dealt with by the other sub-decoders of the decoder Dy.
During read-out of the data word, therefore, the other output terminals, including the output terminal B7 are likewise subjected in a specific manner either to the read-out voltage or to earth potential so that the read-out data word is present at the output terminals BO. . .B7. In the case of the store circuit shown in Figure 4, on the read-out of a programmed storage FET, the associated decoupling transistor, e.g. the decoupling transistor T11. is blocked, which results in the associated transistor amplifier (in this case, the transistor amplifier V0) being controlled in such a way that the read-out voltage Ul occurs across the relevant output terminal, in this particular case the output terminal B0. If, on the other hand, the particular storage FET is programmed. the associated decoupling transistor is not blocked and the associated transistor amplifier therefore connects earth potential to the relevant output terminal.
In order to be able to write-in data words into the store correctly. the control lines syl...sy256 are connected to the drain terminals of additional control D-MOS-FETs
Tsl...Ts256. the source terminals of which are connected to earth potential Um. The gates of the control D-MOS-FETs
Tsl...Ts32 are interconnected. since the associated control lines syl...sy32 are assigned to the same bit position. The operating voltage U is also connected to the gates via a series resistor Tsx1. Similarly, the gates of the other control D-MOS-FETs are interconnected and the operating voltage U is connected thereto. as also indicated for the control D-MOS-FETs Ts224...Ts256 with the associated series resistor Tsx7. On the write-in of a data word. for programming purposes the operating voltage is supplied at the value of the programming voltage Us. The decoders Dx and Dy are used for word selection during write-in as during read-out. This results in the control lines to which a storage FET belonging to a selected data word is connected. being supplied with the programming voltage Us. since the D-MOS-FETs connected to the decoders Dx and Dy are not rendered conductive. Therefore, without additional measures. all the storage
FETs belonging to a selected word would be programmed. This is assuming that the store is in its original or erased state during the write-in of data words. However, generally speaking. not all the storage FETs assigned to a storage word need to be programmed.
This is achieved in the present example. by rendering conductive the control D-MOS
FETs of those bit positions whose storage
FETs are not to be programmed during the write-in of a data word. The rendering conductive of these FETs is expediently achieved via the output terminals B0...B7.
For this purpose, the output terminal BO, for example, is connected via a decoupling transistor Tv0 to the line leading to the series resistor Tsxl. Similarly, the other output terminals, including the output terminal B7, are connected to the other corresponding lines via respective transistors. The gate of a decoupling transistor is connected to the relevant output terminal. its drain terminal to the gates of the relevant control
D-MOS-FETs. and its source terminal to earth potential. Thus, the output terminal
B7 is also connected via a decoupling transistor Tv7 to the line leading to the series resistor Tsx7. If the decoupling transistors Tvo...Tv7 were not provided. the data word to be written-in could be connected in unmodified form to the output terminals B0...B7, and then the control
D-MOS-FETs of those bit positions whose storage FETs were not to be programmed during the write-in of data words. would be rendered conductive. Because of the presence of the decoupling transistors Tv0...Tv7 however, a data word to be written-into the store must be fed in inverted form to the output terminals
B0...B7. The decoupling transistors Tv0...Tv7 prevent any disturbance of the state in which the outputs of the transistor amplifiers are blocked in high-ohmic fashion.
It is also necessary that the circuit components specifically provided for the read-out of data words and the write-in of data words should not undesirably affect one another.
For this purpose, the amplifier stages VO...V7 are blocked when a data word is written-in; on the other hand. the control
D-MOS-FETs Ts1...Ts256 are blocked when a data word is read out. For this purpose, in respect of each bit position.
there are provided blocking circuits which include D-MOS-FETs Trw TwO...Tw8.
These FETs are connected to an additional line sxs which corresponds to the control lines of the further matrix dimension and to which the operating voltage U is connected via a series resistor. On read-out of a stored word, the FETs TwO...Tw7 are rendered conductive via a control terminal C and the
FET Trw. so that the control D-MOS-FETs Tsl...Ts256 are blocked. For the write-in of data words, the FETs Tw0...Tw7 are blocked via the terminal C and the FET Trw. and, in the transistor amplifiers V0...V7 which are likewise connected to the control terminal C, the tri-state outputs are blocked in a high-ohmic manner. This prevents the write-in of data words being disturbed by these amplifier stages.
In the case of the store illustrated in
Figure 4, storage FETs which possess a floating gate and which are constructed using the D-MOS technique, are combined in a novel fashion in a matrix. Most of the
FETs which belong to the control components are D-MOS-FETs, as indicated in
Figure 4 by the appropriate c
Claims (14)
1. An N-channel storage FET comprising a source and a drain formed in a substrate, a floating storage gate entirely surrounded by an insulator on said substrate. and an additional controllable control gate provided with a connecting terminal whereby a potential can be applied to said control gate to capacitively influence said storage gate. the arrangement being such that in use said storage gate is programmed by negatively charging it by channel injection using electrons which are heated by being strongly accelerated in an electric field in a conductive channel between said source and drain. the negative charge thus pro duced on said storage gate, after charging and in particular at the time of read-out acting by electrostatic induction on the channel of said FET to reduce or wholly inhibit the drain source current of the transistor. wherein said storage FET is formed as a D-MOS-FET: wherein said source and drain are formed by respective N±doped zones in an N-doped substrate,
the N±zone forming said source is surrounded by a P-doped zone extending below and beside said source zone, the channel length of the FET being determined by the width of said P-doped zone at the substrate surface; and wherein said drain zone is spaced from said P-doped zone by a distance which forms a drift path and is at least equal to the width of said P-doped zone in the substrate surface adjacent to said drift path.
2. A storage FET as claimed in Claim 1 wherein said storage gate is mostly covered by said control gate but projects beyond said control gate, at least at the source side, whereby said FET can be erased by irradiation with ultraviolet light.
3. A storage FET as claimed in Claim 2, wherein said storage gate projects beyond said control gate only on the said adjacent to said source.
4. A storage FET as claimed in any one of the preceding Claims, wherein said storage gate covers at most only a minor part of said drift path.
5. A storage FET substantially as hereinbefore described with reference to and as illustrated in Figures 1 and 2 of the drawings.
6. A storage matrix comprising a plurality of FETs, as claimed in any one of the preceding Claims, arranged in matrix form in a semiconductor carrier, wherein the source terminals of said FETs are connected by parallel matrix lines produced by diffusion in said carrier; wherein the control gates of said FETs are connected by parallel matrix lines consisting of polysilicon on said carrier; and wherein the drain terminals of said FETs are connected by matrix lines consisting of aluminium which intersect the other two sets of matrix lines at right-angles.
7. A storage matrix substantially as hereinbefore described with reference to and as illustrated in Figure 3 of the draw ings.
8. A storage arrangement comprising a storage matrix as claimed in Claim 6, wherein each of the storage cells of the matrix comprises a single storage FET: wherein the control gate of each FET is connected to a control line in a first matrix dimension, and the drain terminal of each
FET is connected to a control line in a further matrix dimension; wherein the source terminals of all said storage FETs are connected to a common circuit point; wherein associated control components of said storage arrangement are arranged on said semiconductor carrier; wherein means are provided for the electrical programming of said storage FETs for the write-in of data words into the store in the original or erased state and for the read-out of stored words each comprising a plurality of bits. said means comprising a first decoder comprising a plurality of D-MOS-FETs for the first matrix dimension which decoder is adapted to select a single control line for word selection, and a second decoder comprising a plurality of D-MOS-FETs for said further matrix dimension which, in respect of each bit position, is adapted to simultaneously select one of a plurality of control lines provided in respect of each bit position for word selection, the bits which form a word being supplied in each case via output terminals which are individually assigned to the respective bit positions of the words and which are each connected to the control lines associated with the respective bit position via decoupling switching means, the arrangement being such that for the readout of data words, the source terminals of said FETs are connected to earth potential, and the control lines are connected via series resistors to a read-out voltage, and, at the same time, of the FETs forming the decoders which are connected to the control lines of storage FETs not selected for read-out. at least one is rendered conductive in respect of each control line, whereas, of the FETs forming the decoders which are connected to control lines of the storage
FETs selected for read-out. none is rendered conductive: and for the write-in of data words, the control lines of said further matrix dimension. are connected to additional control D-MOS-FETs, the source terminals of which are connected to earth potential. the gates of those of said additional control FETs whose control lines are assigned to the same bit position being interconnected. and connected to the operating voltage via a respective series resistor, and the operating voltage for write-in having the programming value; said decoders being used for word selection in write-in as in read-out; and the control FETs of those bit positions whose storage FETs are not to be programmed during write-in being rendered conductive.
9. A storage arrangement as claimed in
Claim 8. wherein said output terminals are arranged to be additionally employed for the write-in of data words, by connecting them to the corresponding interconnected gates of said control FETs, whilst the corresponding control lines are connected to said output terminals via D-MOS-FETs which serve for decoupling. and via transistor amplifiers. said amplifiers being blocked when a data word is written-in. whilst, when a data word is read out. said control FETs are blocked. the blocking circuits provided in respect of each bit position comprising
D-MOS-FETs which are connected to an additional line corresponding to the control lines of said further matrix dimension.
10. A storage arrangement as claimed in
Claim 9. wherein said transistor amplifiers are provided with tri-state outputs wherein between each output terminal and the gates of the associated control FETs there is inserted a decoupling transistor, the gate of which is connected to the corresponding output terminal, the drain terminal of which is connected to the gates of the corresponding control FETs, and the source terminal of which is connected to earth, the arrangement being such that a data word to be written into the store is always fed in inverted form to said output terminals.
11. A storage arrangement as claimed in any one of Claims 8 to 10, wherein the drain terminals and gates of said control FETs are arranged to correspond to the drain terminals and control gates of said storage FETs.
12. A storage arrangement as claimed in any one of Claims 8 to 11. wherein said series resistors are formed by integrated depletion transistors, the gates of which are connected to their sources.
13. A modification of the storage arrangement claimed in any one of Claims 8 to 12, wherein some of the D-MOS FETs used are replaced by MOS-FETs as claimed in co-pending Application No 36983/75 (Serial No 1517927).
14. A storage arrangement substantially as hereinbefore described with reference to and as shown in Figure 4 of the drawings.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE19772706205 DE2706205A1 (en) | 1977-02-14 | 1977-02-14 | N-CHANNEL MEMORY FET |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| GB1568501A true GB1568501A (en) | 1980-05-29 |
Family
ID=6001161
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB5640/78A Expired GB1568501A (en) | 1977-02-14 | 1978-02-13 | Field-effect transistors |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JPS53117982A (en) |
| DE (1) | DE2706205A1 (en) |
| GB (1) | GB1568501A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS582439B2 (en) * | 1978-11-27 | 1983-01-17 | 富士通株式会社 | bootstrap circuit |
| DE3435355A1 (en) * | 1984-09-26 | 1986-04-03 | Siemens AG, 1000 Berlin und 8000 München | Memory arrangement with memory cells of the floating-gate type |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5223530B2 (en) * | 1971-08-31 | 1977-06-24 | ||
| JPS542052B2 (en) * | 1973-02-21 | 1979-02-01 | ||
| JPS5612956B2 (en) * | 1975-09-01 | 1981-03-25 | ||
| JPS51102477A (en) * | 1976-02-02 | 1976-09-09 | Tdk Electronics Co Ltd | HANDOTAI MEMORIS OCHI |
-
1977
- 1977-02-14 DE DE19772706205 patent/DE2706205A1/en not_active Ceased
-
1978
- 1978-02-13 GB GB5640/78A patent/GB1568501A/en not_active Expired
- 1978-02-14 JP JP1582978A patent/JPS53117982A/en active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| DE2706205A1 (en) | 1978-08-17 |
| JPS53117982A (en) | 1978-10-14 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PS | Patent sealed | ||
| PE20 | Patent expired after termination of 20 years |
Effective date: 19950908 |