GB1567990A - Digital transmission of pictures - Google Patents

Abstract

The digital signals of each series, which are to be reordered, are supplied to one input connection (10) of the device. From the input connection, the digital signals pass to a reference signal generator (20), a comparator (30) and a control logic (200). The reference signal generator is a simple delay circuit which is sufficient for storing the digital signals of one of the series. In the comparator, the incoming digital signals are compared with the reference signals output by the reference signal generator. The reference signals are also supplied to a write address memory (300). The output signal of the write address memory is connected to the write input of a dual memory (55, 65). Depending on the type of the said output signal, the signals generated by the comparator are read into one or other of the memories of the dual memory in the dual memory. The dual memory comprises an output selector (70), controlled by the control logic (200), for providing the reordered digital signals. The reordered digital signals have a lower number of groups having identical digital signals. This device is used for better utilisation of transmission lines, for example in image transmission systems. <IMAGE>

Description

(54) IMPROVEMENTS IN AND RELATING TO DIGITAL TRANSMISSION OF PICTURES (71) We, WESTERN ELECTRIC COMPANY, INCORPORATED, of 222 Broadway, New York City, New York State, United States of America, a Corporation organized and existing under the laws of the State of New York, United States of America, do hereby declare the invention for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the followmg statement: This invention relates to digital transmission of pictures, e.g. facsimile and video.

In conventional facsimile and video systems, a picture image includes a plurality of lines, each line having a plurality of picture elements. Usually within a facsimile system transmitter for example, a coder digitally encodes a voltage which varies in amplitude with the level of brightness of sequentially scanned picture elements (pels). The encoded voltage, hereinafter called the pel signal, is transmitted to a receiver where it is decoded and a facsimile of the picture image assembled.

Often, sequential picture elements are the same, e.g. having the same brightness level.

As a result, the corresponding sequential pel signals are identical. Hence, an identical signal is repetitively transmitted. The resultant repetition of signals, known in the art as a run, leads to inefficient use of the transmission link between transmitter and receiver. To mitigate against the inefficient use, various run-length coding arrangements are known. A typical run-length coder extends two quanta of data to the receiver: one, the brightness level and the other, the length of the run, e.g., a count of the number of sequential picture elements having the same brightness level. Of course, the count could be one, but as the run-length increases, more efficient use of the transmission link is possible.

In accordance with one aspect of the invention there is provided apparatus for processing digital coded picture element signals, comprising; means for obtaining from past coded picture element input signals, data related to the neighborhood of the picture element providing a current coded picture element input signal; and means for reordering coded picture element signals in a line by gouping together in the reordered line, signals for which the neighborhood data is the same.

In accordance with another aspect of the invention there is provided processing digital coded picture element signals by obtaining from past coded picture element input signals, data related to the neighborhood of the picture element providing a current coded picture element input signal; and reordering coded picture element signals in a line by grouping together in the reordered line, signals for which the neighborhood data is the same.

Preferred embodiments of the invention will now be described with reference to the accompanying drawings, in which: Figure I is a schematic block diagram of an illustrative embodiment of a processor embodying the invention.

Figure 2 summarizes an example of a process followed within the processor of Figure 1.

Figure 3 is a schematic block diagram of another illustrative embodiment of the invention; Figure 4 illustrates a neighbor of a picture element and includes information useful in describing an example of a process followed within the processor of Figure 3; and Figure 5 illustrates the results of a survey to obtain a predictor and a reference signal generator usable in the processor of Figure 3.

The processor 100 schematically shown in Figure 1 is used to increase the length of a run.

The run-length of digital signal is increased by reordering a coded pel signal responsive to a reference signal. The reference signal contains data related to the neighborhood of the picture element providing a current coded pel input signal at terminal 10. In this embodiment the illustrative reference signal is the pel signal so occuring during the immediately prior reordering interval.

During a first reordering interval, each pel signal provided to input terminal 10 is temporarily buffered by being written in a cell of either random access memory 55 or 65. The cell address theefor, is provided over lead 356 by a buffer address generator, here write address generator 300. Generator 300 does not usually provide contiguous addresses, but rather provides a write address which is permuted responsive to the reference signal extended thereto over lead 21 from reference signal generator 20. As a result, the input pel signal is written in the memory in reordered fashion. Later, during a second reordering interval, the reordered signal is sequentially read from the memory, the consecutive cell addresses being provided over lead 456 by read address generator 400. The read reordered signal is then supplied to output terminal 80 for extension to the state-of-the-art run-length encoder.

Referring to Figure 2, let a reordering interval be taken as one line of the picture.

Further, let the illustrated picture line consist of eight picture elements. Also, let each memory consist of eight cells, one cell for buffering one pel signal. Illustrative pel signals, columned left to right in the usual manner of a picture line, are identified by pel numbers one through eight. The invention applies equally well to a multibit pel signal. However, for simplicity a bi-level facsimile system is described. Exemplary of a bi-level system is one for communicating a bi-level weather map. The descriptive convenience comes in part because bi-level brightness signals are explainable in terms of a single bit for each pel, typically a logic zero or logic one signal corresponding to a black or white brightness level, respectively.

Returning to Figure 2, rows one and two, labeled respectively "refernce signal" and "input signal", include bi-level pel signals for the previous line and the current line of the picture respectively. The third and fourth rows include reordered bi-level signals for two respective examples. In describing the first example, switch 40 of processor 100 is at position S1. In addition, we find it convenient to assume each memory 55 and 65 to be an eight-cell memory and to think of the memory as a row of eight cells. That then allows us to speak of writing a pel signal in the left or right end of the memory, responsive to the reference signal on lead 21. In particular, if the bi-level reference signal is a logic one, the input pel signal is written commencing at the right end of the memory; if the reference signal is a logic zero, the input pel signal is written commencing at the left end of the memory. The writing continues from the left or right end of the memory toward its opposite end, i.e., toward the right or left end, respectively.

Thus, in Figure 1, input signal bit one, appearing in the second row as a logic one, responsive to reference signal bit one, seen in the first row to be a logic one, is written in the right end, i.e., in cell eight of the memory as shown in the third row. In analogous fashion, inasmuch as the writing commences at the right end for a logic one reference signal and continues toward the left end, input signal bit two, here also a logic one, is written in cell seven of the memory. However, since reference signal bit three is a logic zero, input signal bit three, also a logic zero, is written, commencing at the left end of the memory, i.e., in all one. The writing continues for each input pel signal detected during the reordering interval. Progressively, the memory is loaded from its ends toward its respective opposite end. The reordered signal shown in row three has only three changes in logic stage vis-a-vis the four state changes present in the input pel signal. The reordered signal thus includes a concomitant increase in run-length. Generally, because of the usual similarity of signals in successive picture lines, use of the aforedescribed reordering scheme results in a better grouping together of signals of equal value.

With multi-level brightness signals, the same reordering scheme is used, except that, for example, the memories 55 and 65 are sub-divided into a multiple number of sections corresponding to the number of possible brightness levels, each measure signal thus being directed to the particular memory section corresponding to the particular brightness level of the "directing" reference signal.

Referring again to Figure 1, each pel signal detected at input terminal 10 is jointly provided to an input of reference signal generator 20, an input of control logic 200, and, in this example, through the S1 position of switch 40 over lead 556 to the IN inputs of memories 55 and 65. Reference signal generator 20 can be a simple delay circuit sufficient to store one picture line.

Hence, the previous line reference signal output of generator 20 is extended over lead 21 to write address generator 300 and therewithin jointly to a first input of AND gate 330 and an inverting first input of AND gate 310. A second input of each AND gate is provided by control logic 200 over lead 210. The second input is a timing signal logic one provided responsive to the detection at terminal 10 of each input pel signal; otherwise, a logic zero is so provided. Thereafter, if the bi-level reference signal is a logic one down-counter 340, initialized over cable 220 at the start of the reordering interval to contain the cell address for the right-end of the memory, is decremented. On the other hand, if the reference signal is a logic zero, up-counter 320, initialized over cable 220 also at the start of the reordering interval to contain the left-end memory cell address, is incremented. The left or right cell address is supplied from an output of counter 320 or 340, respectively, to a L or R input of selector 350. The left or right cell address is selected by selector 350 responsive respectively to the detection of a logic zero or logic one reference signal at a SELECT input thereof, the SELECT input signal illustratively being the reference signal. Thereby, the write address is permuted. The permuted write address is thereafter supplied over lead 356 jointly to a write (W) input of each of selectors 50 and 60 for extension to an ADDRESS input of one of memories 55 and 65.

As to which memory the permuted write address is extended, a memory is written or read during alternate reordering intervals.

Specifically, during a first reordering interval, memory 55, for example, is written while memory 65 is read; then, during the next interval, the memory roles are reversed. The memory to be written or read is enabled for writing or reading responsive to a binary signal provided by control logic 200 over lead 230 jointly to each RIW memory input. Of course, to eliminate writing or reading the improper memory cell, the signal timing at the inputs thereof must be consistent with the requirements of the standard random access memory that is used. Such signal timing, here provided over lead 240 to an input of OR gates 51 and 61, is well known. A memory is enabled for writing responsive to the detection of a logic one at the R/W input thereof and for reading responsive to a logic zero thereat.

Thus to use alternating memories, the RIW input of one memory, here memory 65, is inverted by way of a second input of OR gate 61. Coincidentally, the binary signal on lead 230 is jointly extended to a SELECT input of each of selectors 50, 60 and 70.

Thereby, a logic one signal on lead 230 enables selector 50 to extend the write address provided over lead 356 to the ADDRESS input of memory 55 and enables memory 55 by way of a logic otq at its R/W input to write the pel signal on lead 556 in a cell at the appropriate end of a memory.

Concurrently, and pointing out the alternating memory roles during alternate reordering intervals, the logic one signal on lead 230 is also extended to the SELECT input of selector 70. Responsive thereto, an output of memory 65, the memory then being read, is extended through input M2 of selector 70 to output terminal 80. In that respect, the read address is provided by up-counter 410 of generator 400 over lead 456 through selector 60 to the ADDRESS input of memory 65. Specifically, at the start of the reordering interval, up-counter 410 is initialized over conductor 220 to contain the address of the cell at the left-end of the memory to be read and is thereafter incremented responsive to each logic one timing signal extended thereto over lead 210. Thus, in our first illustrative embodiment, although the write address is permuted for loading the input pel signal in the memory, the read address is not so permuted. Rather, the reordered signal is read sequentially from the memory and provided to output terminal 80. Thereby, the input pel signal is reordered responsive to the reference signal to increase the run-length.

In a second example an error signal is reordered. The error signal indicates a difference between the reference signal and the input pel signal. The second example becomes functional with switch 40 at position S2. In that position, signals at input terminal 10 and on lead 21 are provided to respective first and second inputs of exclusive OR gate 30. Write address generator 300 provides a permuted address as described above. However, rather than extend the input signal from terminal 10 over lead 556 to the IN inputs of memories 55 and 65, the error signal is so supplied. In particular, by way of exclusive OR gate 30, a logic zero is supplied to be written in a memory cell if the current and reference pel signals are identical, otherwise a logic one is supplied.

Referring to row 4 of Figure 2, the resultant reordered signal, has only two changes in logic state vis-a-vis the three-state changes present when processed in the first example and the four-state changes present in the input pel signal. The reordered signal thus contains an increase in run-length.

In facsimile systems using predictive coding, a predictor error signal, rather than the current pel signal, is transmitted. One method of predictive coding is disclosed in J. S. Wholey, "The Coding of Pictorial Data", IRE Transactions on Information Theory, Vol. IT-7, No. 2 (April, 1961), pp 99-104. According to the prior art, a survey of pictures representative of the class of pictures to be coded is made. One class might include pictures of circuit diagrams; a second class might include pictures of singlespaced, typed manuscripts, etc. The purpose of the survey is to ascertain for each class the relative frequency that a pel signal will be a particular level of brightness, given the brightness level of each pel in a neighborhood thereof. The neighborhood is usually a prefixed set of nearby, prior pels.

For example, in a class of bi-level pictures, the survey may ascertain the relative frequency that a black pel follows a particular neighborhood. Exemplary of a bi-level picture is a typed manuscript. Bi-level facsimile systems allow a descriptive convenience arising in part because bi-level brightness levels may be coded and explained in terms of a single bit for each pel, typically a logic zero or logic one signal for coding a black or white brightness level, respectively. As a consequence of the survey, given a neighborhood of a pel, the most likely brightness level is assigned as a unique prediction of the current pel. In the prior art, the prediction is compared with the current pel signal.

If the prediction and pel signal are identical, then a first logic signal, e.g., a logic zero, is transmitted to the receiver; otherwise a second logic signal, e.g., a logic one, is so transmitted. Inasmuch as the prediction is usually correct, a sequence of logic zeros is transmitted by run length encoding.

Referring to the first row of Figure 4, a previous line of eight picture elements is assumed to include, from left to right. pel signals labelled A, B, and C having logic signal values zero, one, and one respectively. As to the current line shown in the second row, we assume X to be the current pel and the pel labelled D to be the immediately prior pel. For purposes of illustration, we select as the neighborhood of current pel X, the nearby, prior pels A, B, C and D. Accordingly. for each current pel X in a picture, a neighborhood may be taken as a four-tuple (A, B. C, D). Each neighborhood four-tuple represents one of up to 16 four-tuple states. A survey of pictures representative of the class to be coded leads to the determination of the relative frequency that a current pel X will be a particular brightness level given the state of its neighborhood. In statistical terms, the relative frequency is an estimator of the probability of the current pel X being that level. Figure 5 includes exemplary results of a survey of single-spaced typed manuscripts. The left column includes a row number, zero through 15, for each of the 16 four-tuple states identified in the second column. Column 3 includes the predicted value of the current pel X given the state of the neighborhood shown in the second column. The fourth column includes the relative frequency of the predicted brightness level of column 3 given the state shown in column 2. That is, column 4 includes an estimate of the probability that the predipel.

Therected signal is correct given the state in column 2. In addition. for the respective end points of a picture line, the current pel is transmitted, hence its probability of being correct is unity. Accordingly, returning to Figure 1, predictor 15 of processor 100 may then include a standard tapped, delay line to obtain the prior pel signals A, B, C and D for defining a state and a random access memory responsive to the state for extending the prediction to output lead 16.

Again referring to Figure 5, the probability estimate illustrated in column 4 includes a range of estimates between 0.55 and 1.0.

Certainly, the higher the probability, the more confidence is to be expected in the correctness of the prediction, or stated alternatively, the less likely the current pel signal and its predictor will differ. Hence, our reference signal is a measure of confidence in correctly predicting the current pel.

Therefore, the reference signal is a calibration signal. Although many calibration levels are clearly possible, e.g., consider as four calibration levels an "excellent" level, a "good" level, a "fair" level, and a "bad" level; for purposes of illustration we discuss only two calibration levels, called "good" and "bad" respectively. Illustratively, if the estimate of the probability of a correct predictor exceeds a prefixed threshold, say 0.85, the predictor is considered a "good" predictor; otherwise the predictor is considered a "bad" predictor. The bi-level calibration signal is codable as a logic zero, if "good", a logic one if a "bad" predictor.

Acordingly, returning to Figure 1 reference signal generator 20 may then also include a standard tapped, delay line to obtain the prior pel signals A, B, C and D for defining a state and a random access memory responsive to the state for extending the bi-level calibration signal to output lead 21 thereof.

Inasmuch as the prior pel signals will usually have been transmitted to the receiver before or during the current reordering interval, the reference signal can be recovered at the receiver to enable the original order to be reconstructed so that additional control signals need not be transmitted to the receiver.

Broadly, during a first reordering interval, each pel signal provided to input terminal 10 in Figure 3 is compared by way of exclusive OR gate with a prediction thereof supplied by predictor 15. If in the comparison, the current and predicted signals are identical, a logic zero error signal is extended over lead 556 from gate 30; otherwise, a logic one is so extended. The error signal is temporarily buffered by being written in either random access memory 55 or 65.

In Figure 4, let a reordering interval be taken as one line of the picture. Further, let the illustrated picture line consist of eight picture elements. The corresponding pel signals. columned left to right in the usual manner of a picture line, are identified by pel numbers one through eight. Rows one and two, labeled respectively "previous line" and "current line" include bi-level pel signals for, respectively, the previous line and the current line of the picture. The third row includes a prediction of the current pel signal using the aforedescribed process in connection with the survey results illustrated in Figure 3. The fifth row includes an error signals for each pel. It is noteworthy that, but for pel numbers 2, 5 and 7, the prediction is correct for all picture elements.

If the bi-level reference signal is a logic one, the error signal is written commencing at the right end of the memory; if the reference signal is a logic zero, the error signal is written commencing at the left end of the memory. The writing continues from each end of the memory toward its opposite end, i.e., toward the left or right end, respective- ly. Arbitrarily, we assume the prefixed threshold for our bi-level calibration signal to be 0.85. That is, if the probability of correct prediction exceeds 0.85, the predictor is "good" and a logic zero calibration signal is provided to lead 21 by reference signal generator 20 otherwise, a logic one "bad" calibration signal is so provided.

Thus, in Figure 2, prediction error bit one, appearing in the fifth row as a logic zero, responsive to a "good" logic zero calibration signal bit one, is written in the left end, i.e., in cell one of the memory as shown in the sixth row. However inasmuch as the writing commences at the right end for a "bad" logic one calibration signal and continues toward the left end, error signal bit two, here a logic zero, is written in cell eight of the memory. The writing continues for each prediction error signal during the reordering interval. Progressively the memory is loaded from the respective ends toward the respective opposite end. The length of a run within the current line has been increased from a length three in the second row to a length four in the sixth row.

Now we return to the description of our illustrative embodiment in Figure 1 which incorporates the aforedescribed process for reordering the error signal. Each pel signal detected at input terminal 10 is jointly provided to an input of reference signal generator 20, an input of exclusive OR gate 30, an input of control logic 200 and an input of predictor 15. An output of predictor 15 is extended to a second input of exclusive OR gate 30. The error signal output of exclusive OR gate 30 is provided over lead 556 to the IN inputs of memories 55 and 65. As previously mentioned, reference signal generator 20 and predictor 15 can include common simple tapped, delay line, random access memory apparatus to provide, responsive to a neighborhood state, a calibration signal and a predictor signal, respectively. Hence, the calibration signal output of generator 20 is extended over lead 21 to write address generator 300 and therewithin jointly to a first input of AND gate 330 amd an inverting first input of AND gate 310. If the bi-level calibration signal is a logic one, down-counter 340 is decremented. On the other hand, if the calibration signal is a logic zero, up-counter 320 is incremented. The left or right address is supplied from an output of counter 320 or 340, respectively, to a L or R input of selector 350. The left or right address is selected by selector 350 responsive respectively to the detection of a logic zero or logic one calibration signal at a SELECT input thereof. Thereby, the write address is permuted. The permuted address is thereafter supplied over lead 356 jointly to a write (W) input of each of selectors 50 and 60 for an extension to an ADDRESS input of one of memories 55 and 65.

WHAT WE CLAIM IS: 1. Apparatus for processing digital coded picture element signals, comprising: means for obtaining from past coded picture element input signals, data related to the neighborhood of the picture element providing a current coded picture element input signal; and means for reordering coded picture element signals in a line by grouping together in the reordered line, signals for which the neighborhood data is the same.

2. Apparatus as claimed in claim 1, wherein the means for reordering is operative to reorder the coded picture element input signals themselves.

3. Apparatus as claimed in claim 1, including an arrangement for subtracting one from the other, a current coded picture element input signal and a coded picture element input signal from the next previous line and having the same line position, to produce a difference coded picture element signal, and wherein the means for reordering is operative to reorder the difference coded picture element signals.

4. Apparatus as claimed in any preceding claim, wherein said data comprises a picture element signal from the next previous line and having the same line position.

5. Apparatus as claimed in claim 1, wherein the data comprises a plurality of past picture element signals from the neighborhood of the current picture element.

6. Apparatus as claimed in claim 1 or 5, including a predictive encoding arrangement for subtracting one from the other a current picture element input signal and a predicted picture element signal, to produce a predictively coded picture element signal, and wherein the means for reordering is operative to reorder the predictively coded picture element signals.

7. Apparatus as claimed in claim 6,

**WARNING** end of DESC field may overlap start of CLMS **.

Claims (9)

**WARNING** start of CLMS field may overlap end of DESC **. manner of a picture line, are identified by pel numbers one through eight. Rows one and two, labeled respectively "previous line" and "current line" include bi-level pel signals for, respectively, the previous line and the current line of the picture. The third row includes a prediction of the current pel signal using the aforedescribed process in connection with the survey results illustrated in Figure 3. The fifth row includes an error signals for each pel. It is noteworthy that, but for pel numbers 2, 5 and 7, the prediction is correct for all picture elements. If the bi-level reference signal is a logic one, the error signal is written commencing at the right end of the memory; if the reference signal is a logic zero, the error signal is written commencing at the left end of the memory. The writing continues from each end of the memory toward its opposite end, i.e., toward the left or right end, respective- ly. Arbitrarily, we assume the prefixed threshold for our bi-level calibration signal to be 0.85. That is, if the probability of correct prediction exceeds 0.85, the predictor is "good" and a logic zero calibration signal is provided to lead 21 by reference signal generator 20 otherwise, a logic one "bad" calibration signal is so provided. Thus, in Figure 2, prediction error bit one, appearing in the fifth row as a logic zero, responsive to a "good" logic zero calibration signal bit one, is written in the left end, i.e., in cell one of the memory as shown in the sixth row. However inasmuch as the writing commences at the right end for a "bad" logic one calibration signal and continues toward the left end, error signal bit two, here a logic zero, is written in cell eight of the memory. The writing continues for each prediction error signal during the reordering interval. Progressively the memory is loaded from the respective ends toward the respective opposite end. The length of a run within the current line has been increased from a length three in the second row to a length four in the sixth row. Now we return to the description of our illustrative embodiment in Figure 1 which incorporates the aforedescribed process for reordering the error signal. Each pel signal detected at input terminal 10 is jointly provided to an input of reference signal generator 20, an input of exclusive OR gate 30, an input of control logic 200 and an input of predictor 15. An output of predictor 15 is extended to a second input of exclusive OR gate 30. The error signal output of exclusive OR gate 30 is provided over lead 556 to the IN inputs of memories 55 and 65. As previously mentioned, reference signal generator 20 and predictor 15 can include common simple tapped, delay line, random access memory apparatus to provide, responsive to a neighborhood state, a calibration signal and a predictor signal, respectively. Hence, the calibration signal output of generator 20 is extended over lead 21 to write address generator 300 and therewithin jointly to a first input of AND gate 330 amd an inverting first input of AND gate 310. If the bi-level calibration signal is a logic one, down-counter 340 is decremented. On the other hand, if the calibration signal is a logic zero, up-counter 320 is incremented. The left or right address is supplied from an output of counter 320 or 340, respectively, to a L or R input of selector 350. The left or right address is selected by selector 350 responsive respectively to the detection of a logic zero or logic one calibration signal at a SELECT input thereof. Thereby, the write address is permuted. The permuted address is thereafter supplied over lead 356 jointly to a write (W) input of each of selectors 50 and 60 for an extension to an ADDRESS input of one of memories 55 and 65. WHAT WE CLAIM IS:

1. Apparatus for processing digital coded picture element signals, comprising: means for obtaining from past coded picture element input signals, data related to the neighborhood of the picture element providing a current coded picture element input signal; and means for reordering coded picture element signals in a line by grouping together in the reordered line, signals for which the neighborhood data is the same.

2. Apparatus as claimed in claim 1, wherein the means for reordering is operative to reorder the coded picture element input signals themselves.

3. Apparatus as claimed in claim 1, including an arrangement for subtracting one from the other, a current coded picture element input signal and a coded picture element input signal from the next previous line and having the same line position, to produce a difference coded picture element signal, and wherein the means for reordering is operative to reorder the difference coded picture element signals.

4. Apparatus as claimed in any preceding claim, wherein said data comprises a picture element signal from the next previous line and having the same line position.

5. Apparatus as claimed in claim 1, wherein the data comprises a plurality of past picture element signals from the neighborhood of the current picture element.

6. Apparatus as claimed in claim 1 or 5, including a predictive encoding arrangement for subtracting one from the other a current picture element input signal and a predicted picture element signal, to produce a predictively coded picture element signal, and wherein the means for reordering is operative to reorder the predictively coded picture element signals.

7. Apparatus as claimed in claim 6,

wherein said data is a measure of confidence in said prediction.

8. Processing digital coded picture element signals by obtaining from past coded picture element input signals, data related to the neighborhood of the picture element providing a current coded picture element input signal; and reordering coded picture element signals in a line by gouping together in the reordered line, signals for which the neighborhood data is the same.

9. Apparatus for processing coded picture elements substantially as either example hereinbefore described with reference to Figure 1 as hereinbefore described with reference to Figure 3.