GB1567913A - Computing weighing scale - Google Patents

Description

(54) COMPUTING WEIGHING SCALE (71) We, HOBART CORPORATION, a corporation organised under the laws of the State of Ohio, United States of America, of World Headquarters Building, Troy, Ohio 45374, United States of America, do hereby declare the invention for which we pray that a patent may be granted to us and the method by which it is to be performed to be particularly described in and by the following statement: This invention relates to computing weighing scales, particularly scales for grocery stores, delicatessens, etc., for random weight items, and to calculate the total price or total value of such items. A typical prior art scale is disclosed in U.S. patent No. 3,741,324, June 1973, which has separate electronic digital indicators for price per unit weight and total price, and an optical weight display. A multistation version of a later scale, the Hobart Model 1500, is disclosed in U. S. patent No. 3,906,208, September 16, 1975.

Multi-purpose seven-segment (or equivalent) numerical displays, together with displayed data identification, is disclosed in U. S. patent No. 3,580,421 relating to liquids, a gasoline pump. In gasoline pump numerical displays there is infrequent change of the price per unit measure factor (cents/gal.), and thus no need for quick entry or change of this information.

There is also in the gasoline pump no requirement to recognize the end of gallons measurement; the tank is full, or desired quantity pumped. Also, unit price factor entry precedes dispensing, computation proceeds as liquid is dispersed, and none of the dispensed material is removed, quantity measurement is always unidirectional, and not subject to plus or minus changes as when a customer wants commodity removed from a scale platter.

In computing weighing scales, the price per unit weight will frequently change, and it may be necessary to adjust for tare weight of a package. In computing scales, moreover, govern mental "weights and measures" regulations must be met and costs limited. Thus, adaptation of a single multi-purpose multi-digit indicator to a computing scale presents unique and -unobvious requirements.

Accordingly the present invention consists of a weighing scale having total price computing capability comprising a platter, means for generating data in code corresponding to the weight of a commodity on said platter and including an output for such coded weight data, display means including a multi-digit numerical indicator, means for generating price per unit weight data in code and including an output for such coded price per unit weight data, calculating means having an input connected to accept said coded weight data and said coded price per unit weight data from said outputs and being operable to multiply the two to produce in code data defining the total price of a weighed commodity, said calculating means having an output for the total price code data, control means associated with said calculating means for causing said calculating means to interrogate said means for generating coded weight data and said means for generating coded price per unit weight data and to multiply the weight data entered in said calculating means by the entered price per unit weight, said control means also including means for selectively displaying numbers corresponding to at least two of said outputs on said numerical indicator in a predetermined sequence.

In order that the present invention may be more readily understood an embodiment thereof will now be described by way of example and with reference to the accompanying drawings in which: Fig. 1 is a perspective view of a computing scale according to the present invention, with a remote display and keyboard; Fig. 2 is one face of the display unit; Fig. 3 is a diagram of the keyboard; Fig. 4 (A, B & C) is an electrical schematic of the system; Fig. 5 (A and B) is a flow diagram of the communicate sequence of the program; Fig. 6 (A, B, C and D) is a flow diagram of the computation sequence of the program; Fig. 7 (A and B) is a flow diagram of program subroutines; Fig. 8 is an overall flow diagram of the system; Fig. 9 is a flow diagram of an alternate portion of the program; Fig. 10 is a timing chart; and Fig. 11 is a chart of the RAM register assignments.

Fig. 1 shows a weighing scale with housing 10, platform 12 and platform mechanism (not visible). Platform motion moves a weight encoder 14 (Fig. 4A) to generate a coded weight signal, see U. S. patent No. 3,741,324 and patents referenced therein. A keyboard 15 is connected to an electronics package within housing 10 by a cable. As an example, Fig. 3 shows a twelve-key keyboard, numbers 0-9 plus clear entry (CE) and total (TOT).

Figs. 4A, B and C comprise a schematic diagram of the scale using a microprocessor known as MCS-4 Microcomputer Set, from Intel Corporation, Santa Clara, California. A detailed description of such microprocessor is contained in a publication MCS-4 Micro Computer Set Users Manual, copyright Intel Corporation 1974. Further description appears in Intel U. S. patents Nos. 3,753,011 and 3,821,715.

The display comprises four seven-segment numerical displays 25-28 with decimal point 29 and background plate 30. The display also includes selectable indicators, (back lighted translucent signs possibly color distinguished, mounted on plate 30); U. S. currency, or other language or symbols, including metric can be used.

The signs in the display unit 20 are, (1) weight 32 and 33, (2) currency 35, (3) per pound 36, (4) total 37, and (5) price, 38, energized with sign 36 or sign 37. The driver circuits, lamps, etc., associated with the display elements are shown in Fig. 4C. The displays and signals may be duplicated on a reverse face for customer view.

In a typical weighing operation, if the weighed article is in a container or package of known weight, that weight, tare, is first entered on keyboard 15, and tare value displayed with indicators 31 and 32. Negative sign 31 blinks to indicate tare weight. Tare is inhibited for weight above 0.02, the weight dead zone limit (WDZ). The name price-reject zone might be more appropriate for WDZ weight values according to use of such values in the present scale.

WDZ differs from the weight forbidden zone wherein weighing is not permitted by certain countries for tolerance reasons.

The display continues indicating tare until an article is placed on platter 12, then blanks until scale motion stops, then shows the net difference between tare and gross weights. Net weight indication continues until a second keyboard entry, price per unit weight, starts. Price per unit weight together with the words "price", 38, and "per pound", 36, "$", 35, will then be indicated on the display. Display of net weight is maintained for a predetermined interval, before change to price per unit weight.

Price per unit weight will remain until the operator presses the total button TOT, to compute and display total value (net weight times price per unit weight). With total value the words "total", "price", and "$", are illuminated. The entire display, numbers and words, flashes while total value is indicated.

Total value indication continues indefinitely so long as the operator does not move the scale platter or depress the clear key, CE, on keyboard 15. If a small platter motion occurs (no WDZ entry) one of two options can be followed: (1) The display can return to and remain on weight until another keyboard entry is made to reinitiate computing, (previously entered price per unit weight is not remembered); or, (2) the display can continue indicating weight for a predetermined time, then indicate previously entered price per unit weight, then after a predetermined interval, a new total price.

If a large platter motion occurs (0.02 pound WDZ entered) price per unit weight is erased from display and memory and the scale remains in the weight mode until a new keyboard entry is made. Return to the 0.02 pound WDZ also erases tare if a computation is complete (total button was pressed).

If the operator adds or removes a very small amount of weight (insufficient to actuate motion detecting), the display indicates a new total value computed from the new net weight, and does not return to the weight mode.

If the article placed on the platter weighs less than an entered tare weight, a negative net weight results, this condition is indicated by displaying a negative weight amount. Attempts to compute with this negative net weight produce a first error display. If weight placed on the platter exceeds scale capacity, or if the scale indicates weight value below zero pounds, a second error display is presented. In addition, a total value which exceeds the display capacity results in a third error display. These error indicating special displays are described below and are especially useful for servicing.

The clear key CE on keyboard 15 can erase price per unit weight and the displayed total price. With weight on the platter this key returns the scale to weight mode from either unit price or total price modes. Within WDZ the clear key removes entered tare.

The total button TOT transfers the scale from price per unit weight to total value mode and also disables the keyboard from further use (except clear key). The total button is ignored until no more price per unit weight is tb be entered.

Electircal Layout Figs. 4A, B and C comprise an electrical schematic of the microcomputer circuits, keyboard, weight, photocells, and display circuit. The micro-processor includes a crystal clock providing 1 and 2 pulses, a central processing unit, CPU, a Random Access Memory, RAM, and Read Only Memory, ROM. As illustrated, the ROM consists of three electrically programmable and eraseable (PROM) chips (Intel 4702A) together with an interface (Intel 4289) and two latch circuits 4024A (CMOS from several manufacturers).

Together these are equivalent to a mask programmable ROM, such as Intel type 4001. In a mask programmable version, the interface circuits and the latch circuits are incorporated on the ROM chip.

Scale keyboard 15 is interrogated sequentially in three steps by input strobes KYBD. ST.

A, B and C, Fig. 4A. Keyswitch contacts are connected horizontally to four keyboard output lines B0, B 1, B2 and B3. Line B3 includes clear key CE and total key TOT, and numerical 0.

A keyboard strobe A, B and C lines are pulsed sequentially from a decimal decoder (CMOS 4428) by signals D6-D8. Decoder signals D1-D5 lead to a buffer circuit (CMOS 4049) which has six sequential outputs to decoding logic on the display control board.

Weight reading photocells A through N, correspond to photocells shown in U. S. patent No. 3,557,353 and cooperate with a movable chart (not shown) to read a weight code. The A and C photocell signals also indicate scale and chart motion, as described in the '353 patent; photocells M and N, cooperate to indicate the weight dead zone (WDZ).

When the chart is moving past the photocells, the monostable circuits 54 and 55 are continually being reset to the high state by preamplifier outputs from the A and C photocells coupled through the gates 50 and 51; the monostable outputs remain high until the time of - the monostable pulse generators expire. Thus, if the output of either monostable generator is low at the time the motion detect circuits are stopped, this is an indication of no motion.

In the PROM embodiment, the decoding address circuits 60 and 61 are associated with the interface circuit and address appropriate PROMS and latches. These circuits may be CMOS MC 14556 CP, and are internally incorporated in a mask programmable ROM as explained in the Intel Users manual.

Although the preferred embodiment of the invention is disclosed in terms of a microcomputer and its program, it is to be understood that this scale could be fabricated with conventional logic circuits by one skilled in the art.

Program In the microcomputer program of Table I the first column of numbers are program line numbers, and the second column the ROM address of each instruction in binary form. The third column of numbers identify the instructions in binary machine language, while the fourth column includes four alpha-numeric characters identifying program sections or subroutines. The fifth column in Table I identifies the instructions of column 3 in mnemonic symbols. Column 6 of Table I is programmer's comments.

The flow diagrams Figs. 5, 6 and 7 are related to the program listing of Table I by three and four digit numbers adjacent each decision and certain other blocks, i.e., the number 680 adjacent block 519 is the column 1 line number in Table I for the instruction(s) performing the indicated function.

It is notable in the present scale that input and output operations are performed in real time using only the microcomputer registers and not outboard or external storage elements.

According to this real time mode of operation, the microcomputer is connected frequently and briefly during a communicating cycle to each of the input and output transducers. These connections and their time duration are controlled by the micro-computer program, and are carefully selected to provide clear and pleasing communication. It has been found for example, that in operating a keyboard it is impossible for an operator to close and release a key in less than about 20 milliseconds; in a similar manner, an observer does not distinguish a light which flickers at a rate above approximately thirty cycles per second from a continuous ight.

In order that operator-related functions including sensing new weight, keyboard entry, and display updating be possible at human reaction speeds, the program is organized into two major portions. One portion, a first loop, shown in Fig. 5, communicates repeatedly, i.e., excites the displays, senses keyboard and weight inputs, performs a weight dead zone test and a motion test and then repeats. After performing these steps a predetermined number of times, or upon receiving a data-related command, the second or compute is performed, wherein computation, data conversion and other time consuming events occur.

A test for weight dead zone is included within the Fig. 5 communicate loop in order that scale departure from zero weight be recognized quickly. The identification of keyboard information as tare or price per unit weight, is also determined by weight dead zone presence.

A motion test is included in the communicate loop in order that significant change of platter weight be recognized quickly to blank and reset the display.

Fig. 6 shows the compute cycle, blocks 600-9653. (Numbers in the 9000 series are used after 6999 to reserve 700 numbers for Fig. 7.) Compute cycle subroutines are shown in Fig. 7, blocks 700-754.

The communicate cycle commences with block 508, Fig. 5, line 230 in Table I. This cycle may be repeated a predetermined number of times, 171 in the preferred embodiment, before entering the compute cycle. Each communicate cycle consumes approximately 5.9 milliseconds of time, see Fig. 10. This time is sufficiently short to insure capture of keyboard or weight information by the microprocessor (microcomputer).

Prior to entering the communicate cycle, the power on and resetting sequence of blocks 500 and 501 are performed (block 501 reset is developed in the microprocessor clock).

Following reset, the sequence counter and update counter (see Fig. 11) which respectively determine the identity of the information being displayed, and the number of times the communicate cycle is performed, are set to initial conditions, blocks 502 and 503. The update counter is set to a maximum so a compute cycle is executed following the first communicate cycle. The preliminary steps also include use of the blank subroutine at block 504 as a form of reset in preparation for reading zero weight as explained later.

After loading addressing and counting constants in RAM registers, block 508, Fig. 5, the communicate cycle begins at steps 509-518, driving the display 30, collecting weight information and keyboard status. In the present scale, signals developed by steps 509-518 at the RAM data port lines D1-D8, Fig. 4, enable information collection via the ROM 0 input port and also send information from the ROM 1 and ROM 2 output ports to the display.

Signals emanating from the RAM output port are given the name "D" times, (D relating to digits) since during certain of these D times numerical display 25-28 is illuminated. D times are shown in Fig. 10. The assignment of D times to RAM port output codes is shown in column 4 of Table ll. (Display digits 25, 26, 27 and 28 illuminate, respectively, during D2, D3, D4 and D5.) During D1 time the identity lamps for display signs 32, 33, 35, 36, 37 and 38 are illuminated. Dl is longer than D2-D5 in order that desirable brilliance result from incandescent lamps used in the signs. As also indicated in column 4 of Table II, the RAM 0 output codes other than D1-D4 are used to collect keyboard information.

RAM 0 BCD codes 1 through 5, Column 4, Table II, enable both input and output functions in the scale. BCD code 1 (D1 time), for example, provides both lighting of the sign lamps and accessing performance selecting switches or jumpers 65 in Fig. 4B. D3 time, furthermore enables the second most significant digit of the display 30 and weight indicating photocells. E, F, G and H (Fig. 4A).

During each trip through the block 509-518 steps and return through blocks 520-522, a different D time signal is generated. These signals appear upon performance of block 515, line 590 in Table I. Incrementing of the index register of the CPU, to produce different D times. occurs at line 650, Table I, block 518 in Fig. 5. Details of the index registers, etc., are explained at pages 10-14 of the MCS-4 User's Manual.

D time intervals D1-D5 are separated from adjacent D time intervals by approximately 125 microseconds, Fig. 10, this time is used to change the data sent to the display. D time signal termination occurs at block 511.

In order to stretch the duration of the D1-D5 times and thereby provide brighter displays, a time waste (steps 520-522) is included in the return path 513. In addition, loop 516 makes the D1 pulse longer than any subsequent D2-D5 pulse, so that indicator signs 37, etc., illuminated by incandescent filament lamps, appear as intense as the light emitting diodes in the numeric displays.

Upon D6 generation, steps 524-529 which develop pulses D7 and D8 are commenced. The shorter D7-D8 pulses allmw quick reading of the scale keyboard and thereby lenthen the display intensity controlling D 1-D5 times. D7 and D8 times are also not separated by the data change time provided between the outer D time pulses. The D8 pulse is longer than either D6 or D7 with D8 termination being determined by the time to complete the communicate cycle steps down to block 597 in Fig. 5.

On each trip through the D7-D8 steps 524-529, the possibility of a keyboard key closure is considered at block 524. Closure of a keyboard 15 key is first discovered during communicate cycle operation and remembered temporarily as a bit of information in RAM location 21-23 (Fig. 11). This rembered indication is decoded to a numeric value and tested for possible errors during compute cycle operation when the - time for a decoding procedure can be afforded.

The finding of a closed key at block 524, the JCN test of line 700 in Table I, provides access by path 533 to the keyboard status sequence at steps 532-549. In this sequence, status word A indicates a key closure may be safcly regarded as authentic information, i.e., a count of two for status A" indicates three consecutive scans of a closed key have occurred. Status word A is incremented at block 539 each consecutive communicate cycle the test of block 524 finds a key closed. If a key should bounce open after being once closed, status word A is reset at block 530.

Once a key status A of value two is sensed at block 534, the key contents at RAM locations 21-23 is known to be valid. (The keyboard information was placed in RAM locations 21-23 a block 5 17 during D6, D7 and D8 times, respectively.) Once verification of the keyboard information has occurred at block 534 the path through block 542, along path 543 is used for communicate cycles until the steps of blocks 548 and 549 are reached and initiate a compute cycle to decode and store keyboard information. Key down status C, block 549, is sensed during a compute cycle to initiate keyboard data decoding. Once a compute cycle has accepted the keyboard information, a key down status B flag is set. Testing this key-down status B at blocks 542 and 541 precludes keyboard decoding during subsequent communicate cycles until a no-key closed condition occurs. During the communiccate cycles which occur while an already sensed key remains closed, path 546 is used.

Once valid key closure is established, path 543 examines for the key being a clear key, CE, or total key, TOT; the finding of a closed clear key results in setting the update counter to maximum in order that an aborted compute cycle follow immediately. If the clear key is found open at block 544, the total key status is accessed and read, blocks 545 and 547, to determine if a total key entry was sensed previously. If the total key status word is set, an exit along path 526 occurs, such exit precluding the setting of the update counter to a comput cycle condition and also precluding the writing of key down "status C" in block 549. Absence of keyboard status C prevents entry of keyboard information on subsequent cycles. It should be noted, therefore, that whenever a total key status is sensed, block 547, exit along the path 526 occurs so no further information can be read from the keyboard by reason of status C not being set.

Once a determination is made that a key remained closed for three successive short cycles, status C is set and the update counter preconditioned to assure a compute cycle is immediately executed (assuming the key is a number key). This arrangement wherein the keyboard data has priority over the other steps assures key information capture before its disappearance and further implements the concept that processing is done in real time without the aid of external data storage.

At block 551, etc.. is implemented the criteria that price per unit weight entries are to be erased or inhibited so long as the scale is within the weight dead zone, (WDZ), i.e., below 0.02 pounds, and tare entries are to be erased when the scale returns to WDZ following total value compute. If the total key status is set therefore, then resetting tare in WDZ is desired.

In block 551, data representing the contents of the chart tracks "M" and "N" (most significant data, bits see U. S. patent No. 3,557,353) is accessed and examined, block 552, to determine if the scale is below 0.02 pounds. The results of the weight dead zone test is stored at block 555 and tested at block 557 with the clearing of price per unit weight entry occurring as indicated at block 558 and the reading, testing and clearing of the tare status and tare memory being indicated at blocks 559, 560, 561 and 564.

The communicate cycle motion test appears at blocks 567-578; these steps ultimately blank the display as indicated at blocks 572 and 574. Sequence counter resetting here assures a minimum information display time following motion cessation as explained later. At blocks 567 and 568 the motion testing sequence is excluded for a time following keyboard entry, in order that key movement scale vibrations not result in a false motion indication. The motion read inhibit status of block 567 is set at block 538.

If a motion test is to be performed, the motion signal is accessed from block 58, Fig. 4B and tested in blocks 569 and 570. Failure to detect motion causes motion flag reset at block 575.

Blinking/Flashing Display At blocks 578-595 in Fig. 5 is shown steps which achieve both blinking of the tare weight negative sign and flashing of the total price numbers. As indicated by the test at block 579, periodically the return, along path 596 to repeat the communicate cycle, occurs via blocks 580-595 rather than from block 579; during this 580-595 return blinking and flashing are performed.

Blinking and flashing commence with block 578 incrementing and reading register 15, (registers 14 and 15 are update counter B and A respectively with high order bits in B, see blocks 578 and 587). If counter "A" is zero at block 579, steps commencing with block 580 are performed including the sequence counter test of block 579 to determine whether a minus sign blinking or total value flashing are needed. If the sequence counter indicates 14 or more, the scale is in the total price or the display blanking mode (see column 1, Table II) and the flashing steps of blocks 591-594 are performed. Flashing is achieved by turning the total value display off during communicate cycles wherein the most significant portion of the update counter, register 14 has a value "14" at block 591. The total price display is thus turned off at blocks 592-594 for thirty-two communicate cycles whenever the most significant half of the update counter contains the value "14". The display blanking subroutine block 954 is shown in Fig. 7A.

Returning to block 581, the total price mode has not yet been reached, (the sequence counter has a value less than "14") so the block 582 test for sequence counter value cf 13, (price per unit weight mode) is performed. If the value is less than "14", at block 581 and not at "13" at block 582, then it must from column 1 of Table II, be "1", "10" or "12", i.e., tare or net weight display modes, wherein blinking of a negative sign may be desired. In the tare mode, a negative sign will always be present, and blinking is desired. In the net weight mode (sequence counter state "12"), the net weight can have a negative value (a blinking minus sign is needed) if the operator has entered a tare value greater than the article weight.

When tare is displayed the sequence counter can be in any of the states "1", "10" or "12".

State "1" forces the scale into weight display for 171 communicate cycles prior to advancing to the price per pound mode. States "10" or "12" allow entry into the price per pound mode, which is sequence counter state "13".

In the test of block 582, if the sequence counter is found in either the tare or the weight conditions, an exit to block 584 and a test for the most significant digit containing a negative sign results, blocks 584 and 585. Failure to find a negative sign, as well as finding the sequence counter in the price per pound mode, provides return by the path 593 to the mainstream of the communicate cycle. If a negative sign is found in the most significant digit position in the test of block 585, the steps which perform the blinking the least significant digit commence at block 587. Negative sign blinking is achieved by display turn off at block 589 if a "binary 2" is in update counter B. A count other than 2 at block 587 results in loading the minus sign at block 588. Displaying of blank or minus sign is indicated at block 590.

Following blinking and flashing, the update counter is incremented and tested for an upper half count of zero, block 597. Absence of a zero results in a return along path 596 to the communicate cycle start; while finding a count of zero, a compute cycle initiating count, causes presetting of the update counter at block 598 in preparation for a subsequent sequence of communicate cycles. The preset value of 85 in block 598 provides approximately one second of time elapse between successive compute cycles.

Communicate Cycle Summary 1. Generation of D time pulses for weight, keyboard and status input and for numeric and word display output, 2. Keyboard contact bounce exclusion and reading time election.

3. Price per unit weight and tare memory clearing in response to weight within WDZ.

4. Initiation of new scale and display sequence in response to platter motion.

5. - Blinking and flashing of selected display quantities.

Compute Cycle The compute cycle is in reality a plurality of program paths which are alternately followed depending upon conditions encountered.

When the update counter reaches a condition of all zeroes as a result of having performed 171 communicate cycles, or as a result of presetting, the decision of block 597 in Fig. 5B will enable path 586 to block 598 which commences a compute cycle. Update counter presetting is found at block 505, (update counter preset to insure a compute cycle following first communicate cycle after scale turn on) or block 548 (update counter preset to quickly parentheses, (i.e., 630 at block 820) relate the Fig. 8 blocks to blocks in Figs. 5, 6 and 7. In Fig. 8 decisions are indicated along the path leading from a decision block in lieu of the more formal indication within the block as shown in Figs. 5-7.

In Fig. 8, the paths 843, 845, 847, etc., indicate certain of the possible compute cycle operating sequences. The path 843, for example, indicates events occurring when the scale has been unused and a tare digit key is pressed. Path 845 causes an entered digit of tare to be illuminated on display 20.

Key Decoding The path 843 in Fig. 8 including a key entry is considered first. The block 532-549 sequence was employed earlier to determine whether a key closure should be accepted, ignored as bounce or ignored as previously read (status flags A, B and C). The key reading sequence provoked at block 549 commences with testing the key-down status C flag at blocks 601 and 604, the block 604 test providing a jump along path 603 for compute cycles initiated by something other than a key closure (i.e., by 171 communicate cycles, or by blocks 505, 651, etc.).

Since key actuation may give vibration and false motion signals, the status bit set in block 602 inhibits motion testing, blocks 567, 568, during next subsequent communicate cycles.

The motion read inhibit status is reset after a 700 millisecond group of communicate and compute cycles at the same block 602.

If the key down status C test of block 604 indicates the reading key information is appropriate, status C flag is reset, block 605, the addressing constant for key reading placed in memory, block 607, and key reading steps 608-611 commenced. (The key memory at locations 21-23 in RAM "0" is examined, one location each trip through 608-611 to find the single bit of information among the twelve bits stored indicating that a key has been closed.) The keyboard is wired (Fig. 4A) such that during D-6 times, an enable pulse is applied to the first column of keys (numbers 1,4,7 and CE), these being assigned key numbers of 1,2,3 and 4, respectively. The enabled circuit is KYBD. St. A. During D-6 time, keyboard output line BO-B3 is examined for the enable signal, indicating a key closure.

During D-6, D-7 or D-8 times, a signal will be found on one keyboard output line if a key is closed. The block 608-611 sequence repeats via path 606 until this closed key is found. The lower exit from block 611 prevents program hang up in the event noise or other unpredicted event allows entry into the 608-611 sequence without a keyclosure.

Conversion of key closure information to a Binary Coded Decimal (BCD) word is performed in a plurality of steps after block 609. These steps add to the memory bit number which contains a closed key indication, a conversion constant of zero value, four or eight according to key location in the first, second or third keyboard column (St. A, B or C) in Fig.

3. This summation of bit number and conversion constant is used as the look-up address in the table at line 5010, Table I. For example, if the operator has pressed the 8 key, a binary signal is stored in bit position 3 of RAM location 22. Since 8 is located in the second keyboard column, a conversion constant of four is added to the bit number of three to obtain a look-up address of seven. A look-up address of seven provides a line 5080 BCD output of eight which corresponds with the key ace numeral.

As a second example, the numeral six in the third column of the Fig. 3 keyboard is stored at bit two of RAM location 23; by adding this two to a conversion constant of eight, a table address of ten results. At line 5110 in Table I, address 10 provides a key output of BCD six as desired. In the flow diagram of Fig. 6, the constants zero, four and eight are generated at block 610, the addition of one constant is performed at block 618 and the table look-up is at block 619.

The KBP instruction at line 2900, Table I, block 615 provides a bit position number for a keyclosure indication. KBP also provides an error signal (BCD 15) if two keyclosures in the same vertical column are detected. The test of block 617 detects this KBP error signal and provides compute cycle abort.

Key Error If the operator simultaneously closes two keys in a horizontal row, the keyboard sequence just described will respond to the first encountered key, i.e., the leftmost, and ignore the other. The keyboard status sequence at block 532 in Fig. 5 will not permit a second closed key in a horizontal row to be read since key open must precede key closure for status B and C signals, blocks 542 and 549, to be set. Ignoring the rightmost of a horizontal two key closure and requiring key open preceding key closure provides roll over protection in the horizontal row while compute cycle abort (block 617) provides key roll over protection in the keyboard vertical columns. CE and TOT keys are regarded as numeric values 11 and 12 in theline 5010 conversion table; these numeric values are interpreted as "clear entry" and "total" later in the program.

Tare Inhibit Continuing now with events along tare entry path 843 in Fig. 8, for tare entry the scale chart is in the weight dead zone and the lower exit from block 813-621 used to the block 624, 625 tare inhibit jumper test. Presence of jumper 65 in Fig. 4B selects tare omit operation and results in a lefthand exit from block 625.

If jumper 65 is absent (storage of the decoded keyboard digit as tare is desired), tare memory is addressed for later use, block 627, the key number read in, block 628, and tested for being a total or clear key, blocks 630 and 631, the least significant digit of previous tare shifted to the next higher memory position and the new tare number entered, blocks 632 and 634. Blocks 632 and 634 are excluded for a total key while a clear key at block 631 initiates clearing and compute cycle aborting, blocks 637 and 638.

Compute cycle aborting, usually caused by operator action, includes within the abort sequence, setting the update counter, (registers 14 and 15) to a maximum condition to assure a new compute cycle commences immediately after the communicate cycle that automatically follows a compute cycle abort. Cycle aborting for an undesired or overriding condition minimizes computer time outside the display cycle, since the compute cycle steps following the abort are not performed. Just prior to leaving each communicate cycle initiated by an aborted compute cycle, the update counter is preset, block 598, to cause repeated communicate cycles once a compute cycle is successfully completed and the display information thereby updated. Most compute cycle abort events return to the starting terminal of the communicate cycle at block 500, however, the abort of blocks 637-639 returns instead to block 562 and tare-clearing in order that a "D" times and display not follow a clear entry command.

Weight Range As indicated at 826 in Fig. 8, once through blocks 630 and 631 the path 843 includes a weight range test. If either the E or G photocells have provided data for the weight reading under consideration, the weight chart is determined to be within its weighing capability, (between 0.00 and 25.00 pounds) as is explained in U. S. patent No.3,557,353. If improper weight is found at blocks 674, 675, the sequence counter (CPU RAM location 0) is set to a "one" condition to illuminate the word "weight" 32 in Fig. 2, and the display error subroutine executed to light the center bar segments 31, blocks 678, etc. Four bar segments and sign 32 indicates an error, an improper scale weight.

Gross Weight Less Tare If either but not both E and G photocells are lit, (a proper weight value) the compute net weight sequence, block 828-681 is accessed to subtract tare entry from gross weight. Compute net weight begins with subroutine conversion of gray code chart information into BCD, block 681. The properties of the preferred gray code and an example of this conversion are in U. S. patents Nos. 3,557,353 and 3,439,760. Conversion is performed in the present instance by the code conversion subroutine at block 740, Fig. 7, and the table at line 7950 in Table I.

Once gross weight and tare weight are accessed from memory, block 682, subtraction is performed by the looped instructions 684-687. The path 686 provides subtraction of higher order digits until block 687 indicates completed subtraction. Under certain conditions in subtracting BCD numbers a correction constant of 10 is needed; the test for this correction is indicated at block 688, line 4390 of Table I.

If the scale operator entered tare exceeding platter weight, the subtraction of block 684-687 will involve subtrahend larger than minuend. A carry bit indicating this condition is sensed at block 691, and initiates a reserve subtraction process, block 693, etc. If block 693 is used, the displayed data is accompanied by a negative sign, block 695, indicating tare greater than platter weight.

For normal tare display in this scale blocks 684-693 are used with tare value (subtrahend) greater than weight (minuend, zero). In path 843, therefore, tare data can be referred to as a net weight. At block 692 a flag is set indicating negative net weight; a block 9631 this flag prevents computation of negative weight total value.

Display Test & Load Prior to transferring net weight (tare) to display memory (block 9610), the sequence counter test of block 699 determines if the scale is in the total value mode. The possibility of total value mode exists from reuse of the weight range test, blocks 672-675, during total value mode, path 857, Fig. 8.

Addresses for the transfer to display memory, block 9610, are set at block 9602. A code determinitive of lamp 32, illumination etc. during the next communicate cycle is loaded in the sequence counter at blocks 9604-9609. At blocks 9607 and 9608 if the scale is within the weight dead zone only "LBS" 32, is to be illuminated, hence the sequence counter should equal ten. If outside the weight dead zone, both "weight" and "LBS" (sequence counter equal 12) are desired. An inverted status indication is employed in Table I relating to block 9605 to save ROM space.

At block 840, prior to displaying net weight (or tare, price per pound or total value), the most significant digits for display are tested for zero value, block 9612, for supressing superficial zeroes, at block 9615. A return to the communicate cycle start occurs at block 9617, by path 841, Fig. 8. In the next communicate cycle, the newly computed net weight will be displayed.

If the digit of tare information from path 843 in Fig. 8 is followed by a second tare digit subsequently events similar to path 843 occur. In the interval following a tare digit entry, the entered digit is displayed by repeated trips through the communicate cycle. A minimum tare display time of 171 communicate cycles (about one second) is assured by the sequence counter setting of "one" at line 1690 in Table I, block 572 in Fig. 5.

After each group of 171 communicate cycles displaying the tare digit(s), a trip through the compute cycle will occur along path 845 includes a decision of no keys to be read, block 804, and writing update counter status, block 816, this writing update counter status, block 816, this writing is used in the price per unit weight display mode and being without consequence in path 845. Path 845 also includes motion test (block 848) tests 850 and 852, and exit from block 854 to the weight range test, block 826. After the weight range test, path 845 is coincident with path 843 described above. During each of the path 845 compute cycles, displayed tare is recomputed using new platter weight from blocks 826 and 828. A new display sequence using the updated tare value is initiated by return along path 841.

Following display of tare, the operator will place a package on the platter 12; the resulting motion will cause the motion test, block 848-650, to provoke compute cycle abort decisions at block 650. Compute cycle aborting involves update counter setting, block 651, and return to the communicate cycle start, block 652. Tare display, path 845, will terminate a block 848-650 so long as the scale is in motion.

Signals generated at the scale motion detecting circuit are received as status bits through gate 58 and tristate buffer 59 on the microcomputer data bus. These signals are stored in status word zero of RAM register I (Fig. 11). The stored signals are accessed at block 649 in Fig. 6 and tested at block 650 to determine if the scale is in motion. Scale motion is also detected at block 570 in the communicate cycle, Fig. 5, in order that illumination of the display 20, Fig. 1, be inhibited while the scale is in motion.

Once platter motion terminates in path 845, the lefthand exit from block 854 in Fig. 8 is employed, (a sequence counter code less than nine is present from block 572) and the weight range tested and net weight determined, blocks 826 and 828. In path 845, the test of block 830 is not met, i.e., the system is not in the total mode but the test of block 832 finds the weight chart out of the dead zone so the sequence counter is set to 12 at block 836 to display the "LBS" and "weight" signs (Fig. 2) and modify the decision at block 854 during the next following compute cycle. Following block 836, the computed net weight is entered into memory, upper digit zero presence tested and blanked at block 840, and the weight displayed during the next communicate cycles which are initiated by return on path 841. On successive trips through a compute cycle with the platter loaded and motion terminated, path 845 is modified to the extent that the lefthand exit from block 856 is used to enter the weight range test, and setting the sequence counter at block 836 alters the route through blocks 854 and 856.

Price per Unit Weight Entry Once the operator presses a first key of price per unit weight, the decision at block 804 indic'ates a key entry. After the key status test blocks 532-549 is satisfied, key information is read and decoded, blocks 808 and 810, and exit from block 813 to block 842 is employed, in view of the weight chart being out of the dead zone. If the operator is properly entering a number rather than a total key, the lower exit from block 842 is employed and the price per pound entry sequence of block 846-644 performed.

In price per pound entry a binary number representing the key depressed-is entered at block 644, into RAM position 10 (Fig. 11), and then shifted to the left, in order that the first entered digit ultimately appear as the most significant digit of price per unit weight.

As digits from subsequent entries accumulate at memory locations 11-15, each successive execution of block 645 shifts a greater number of digits, the digits being transferred from location 11 - 15 to location 43-47 and then back to locations 11-15 in shifted position, one digit at a time. Following the first and each subsequent trip through blocks 644-648, a price entry status word is loaded into status word one of register 0 in the RAM (Fig. 11), this loading being accomplished at block 647.

Price per weight entry also includes setting the update counter status (RAM location 5 in Fig. 11) to a value of "15", block 648, as part of assuring a total key closure does not remove price per unit weight before 171 communicates cycles, about one second has elapsed. At block 862-9628, the sequence counter is tested to determine if 171 communicate cycles have intervened since price per unit weight entry. Resetting the update counter to "0" after 171 communicate cycles is accomplished at block 612.

Once price is entered and the status word set at block 846-647, the same compute cycle will enter the price per unit weight loading and display sequence of block 858-9658 including setting the sequence counter to 13, the price per pound mode. In this condition, the signs "price" 38 and "per lb." 36 (Fig. 2) are illuminated for displaying price per unit weight.

Information displayed from a block 858-9658 operation is transferred to display memory at block 9659 and the testing-blanking of block 840 performed.

Once the sequence counter is set to the price per unit weight "13" condition, the lefthand exit from block 852 and the path through block 860 to block 858 is employed in subsequent compute cycles. This will cause repeated use of block 858, with the latest information including a new key entry being transferred to the display memory for testing and blanking in block 840.

Total Key Command At some subsequent time, the operator will strike the total key TOT (Fig. 3) in order to compute and display total value information, path 849. If the operator strikes a TOT key before entering price per unit weight, the decision of block 855 provides compute cycle aborting. In block 844 a status flag is set indicating the total key has been depressed, block 657, and the tare reset status is set, block 658. The tare reset status indicates a completed transaction and is used at block 559 in the communicate cycle to enable tare erase upon next entering the weight dead zone.

At block 659 information from jumpers 65 (Fig. 4B) is read to determine duration of the price per unit weight display. A customer having a purchased item weighed is especially interested to see the price per unit weight entry made by the scale operator. The status word read at block 659 (Fig. 6B) is tested at block 9628 to determine if another jumper selected increment of communicate cycles is desired to meet the minimum display time requirement, the lower exit from block 9628 is used only if a minimum price per unit weight display has occurred. If the minimum price per pound display time has not occured, block 862 causes the loading and displaying of price per unit weight information, blocks 858 and 840, to repeat.

Diversion of path 849 for more display time is indicated at 863.

Compute Total Value (Article Price) Following display time testing at block 862, total value computation and rounding, block 864, is performed. This computation commences at block 9629 where RAM locations 32-39 (Fig. 11), are accessed and cleared and the tare status tested, blocks 9630 and 9631 to prevent total value computation in the event of a negative net weight. For a negative net weight at block 9631, a display error condition is indicated at block 9632.

Multiplication of net weight and price per unit weight is performed by the repetitive addition steps at blocks 9634-9642. The path 9636 in the multiplication sequence repeats adding the multiplicand digit, the number of times dictated by the multiplier digit. The path 9633 provides a jump around the addition steps in the case of a zero multiplier digit.

Once multiplication is complete, the total value rounding and transfer sequence of blocks 9647-9652 is performed; here the round subroutine increments total value digits in RAM locations 32-39. At block 9649 the sequence counter is set to the "14" state total mode) while at block 9650, the transfer from product memory (RAM 32-39) to display memory (RAM 1-4) is accomplished. In block 9651 and 9652, the total value product in RAM locations 32-39 is tested for having an overflow non-zero digit in the fifthmost significant digit position, i.e., RAM location 38. The sixth digit of product in RAM location 39 can also be tested for overflow. The steps of setting the sequence counter, transferring total value and testing the fifth digit overflow indicated in blocks 9649-9652, are represented by block 866 in Fig. 8. Following total value computation, rounding and testing, the test for zero blanking, block 840, and a return to communicate cycle are performed.

Total Value Display Mode After the sequence counter is set to "14" in the total value rounding sequence at block 9649 (Fig. 6D), compute cycles executed from completing 171 communicate cycles will follow a path including block 804, blocks 816 and 848, a lefthand exit from block 850 through the weight range and net weight computation events, out the righthand exit of block 830 through blocks 860 and 862 to a new computation, testing and displaying of total value quantity. Display occurs here during communicate cycle operation, block 802. It should be noted that this path involves recomputation of net weight and new computation of total value at blocks 828 and 864, respectively, so that the total value displayed is updated periodically.

If platter 12 is moved by a small amount, (less than required to activate the motion test of block 848). the lefthand exit from blocks 850 and updating of net weight and total value will continue, i.e. the scale is actively responsive to changes of weight while total value is displayed. If it is desired to display the net weight being used to compute the updated total value the operator may, of course, disturb the platter and activate the motion test of block 848 to cause compute cycle aborting. The operator can also return the scale to weight display mode by striking the clear entry key CE sensed at block 544 (Fig. 5A) to provoke an immediate compute cycle by way of blocks 548 and 549.

In the compute cycle which results from a clear key entry, the key test and decoding sequence of blocks 601-620 are performed and the right hand exit from block 621 employed, (the scale is in the total value mode and therefore out of the weight dead zone) and the read price sequence of block 633 is commenced to read and test the binary key number, block 636, for being a clear key. A clear key at block 636 provides access to the clear price subroutine (Fig. 7) at block 640. Clear price subroutine returns the sequence counter to a weight display code of "1", returns the price per unit weight memory to the "0" condition, blocks 725-728, and clears the price and total key statuses, blocks 729 and 730, so that the scale is placed in the weight display mode. The clear price subroutine does not erase entered tare. Tare is erased at block 814 only upon the chart being within the weight dead zone, block 813 and a clear key pressed, block 822.

The blocks 633-640 steps which access the clear price subroutine are omitted from Fig. 8 for simplicity; if shown, the steps would be located between blocks 813 and 842.

Compute Cycle - Overall The paths 843, 845, 847 and 849 in Fig. 8 indicate four possible compute cycle sequences.

If each possible path between blocks 802 and 840 is considered, e.g., including such modifications as path change after the first and second and third price per unit weight digit are entered, the number of possible different 802-840 paths could be quite large. Listed below are scale events which result in the major different paths from block 802 through 840 in Fig. 8. The numbers 843, 845, 847 and 849 in this list identify paths indicated in Fig. 8.

1. quiescent with 0.00 displayed 2. enter tare from keyboard (843) 3. tare display routine (845) 4. second tare entry from keyboard 5. article received on scale (chart moving) 6. chart stopped, chart out of range 7. chart stopped (in range), compute net weight 8. display net weight (847) 9. enter first digit of price per unit weight (minimum weight display time expired) 10. enter first digit of price per unit weight (weight display too short) 11. enter second digit of price per unit weight 12. enter total key (minimum price per pound display expired) (849) 13. enter total key (price per pound display too short) 14. compute total price 15. change platter weight (not motion signal) 16. display total price 17. change platter weight (motion signal but chart doesn't enter WDZ) 18. change platter weight (chart enters WDZ) Typical compute cycle operating times for this scale are listed below. Incorporation of events from even the shortest of these compute cycles into the 5.95 millisecond communicate cycle would significantly alter the communicate cycle operating time and diminish the proportion of display ON time. Such incorporation could also diminish the assurance of capturing a keyboard closure in real time operation. Hence, it is significant that the communicate and compute cycles are separated and apportioned as described above, to assure complete scale functioning with a minimum of electronic components, and be compatible with human response intervals, such as finger (digit) manipulation of keys or manual devices, and visual recognition, deciphering, etc., of the display. Some typical compute cycle operating times in milliseconds are as follows: Display weight, weight mode 4 ms Display weight, two tare subtractions 5 ms Key entry, price/pounds mode 3.7 ms Motion aborted compute cycle 0.8 ms Total Value Compute (3 digit x 3 digit multiply) 37 ms Computation of total value requires repeated use of blocks 9635-9642 (Fig. 6D) and therefore involves considerable non-illumination time for the display. This computation is made to occur during transition between price per unit weight display and a total price display to prevent display degradation.

Interlocking Even though an apparently unfavourable operating sequence such as compute cycle, communicate cycle, compute cycle may be precipitated by a compute cycle abort, real time display operation is protected in such instances by an interlocking arrangement. An example ot this interlocking is found where a key closure is valid at block 532-549 (Fig. 5A), and an immediate compute cycle precipitated by update counter setting, block 548. If this compute cycle should end with a compute cycle abort, if the operator pressed two keys in the same vertical column (block 617) it would appear that the steps of blocks 651 and 652 (update counter set to maximum in order that a compute cycle immediately follow the communicat cycle initiated at block 652) would lock the scale in a repeated series of compute cycles.

This undesired operation does not occur, however, since the keyboard status tests, block 532-549 preclude keyboard decoding until key open is sensed. Even though the operator maintains a key closure, only one compute cycle will attempt reading double keys as a result of keyboard status interlocking. In the compute cycle which results from block 651, keyboard reading and decoding will not occur and the multiple key abort, block 617 will be avoided since the key down test of block 604 precludes keyboard activity until "all key open" is detected. The keyboard status sequence of blocks 532-549 also prevents other keyboard acts from noticeably affecting operation of the real time display.

It is also to be noted that no scale platter acts can alter the desired motion signal response of display blanking. The motion signal is derived from the scale chart and immediately, in the communicate cycle, halts display illumination, blocks 570-574. The compute cycle is generally immune to operator intervention, (except for scale motion) since communication with external events occurs only during communicate cycle operation.

Sequence and Update Counter Operation Two counters, the display update counter and the sequence counter, control operating events in the scale. The display update counter (CPU registers 14 and 15) determine when sufficient trips through the communicate cycle have occurred, and a compute sequence is therefore needed. The update counter can reach a count of "0" either from incrementing one count per communicate cycle or from presetting (block 505, etc.). The update counter is separate from the update counter status word (RAM location 5, Fig. 11). The update counter status word indicates when 1 71 communicate cycles have occurred.

The sequence counter (RAM location "0", Fig. 11) is addressed as a program convenience by information permanently stored in CPU registers 12 and 13, register pair 6. Six sequence counter states are contemplated, 1, 10, 12, 13, 14 and 15, Table 11. Each state is forced on the sequence counter not incremented from a previous state.

The sequence counter selects paths through the compute cycle blocks 802-840, Fig. 8.

Examples of this function are at blocks 850, 852 and 854. A second function of the sequence counter is to select the word signs 32, 35, 36, 37 and 38 (Fig. 2), see column 1 of Table II. To control word sign illumination, the sequence counter contents in RAM location "0", terminated 85 microseconds after D-1, the currentflow time again being defined by D-1.

In the lowest line of the Fig. 10 timing chart, the location and duration of the information sampling strobe pulses within D time intervals is defined.

Alternate Embodiments In the preferred embodiment the display remains in the total value mode permanently once a total key entry is made (i.e., until operator intervention). Alternately, the scale, while in the total value mode, may repeat the sequence of weight/price per pound/total value displaying continuously. A modification to the communicate cycle which accomplishes this repeated cycling through weight/ price per pound/ total value displaying is shown in Fig. 9. The blocks 567 to 575 in Fig. 9 represent motion testing, (from block 567 to 575 in Fig. 5B) with the exception that the block 572 has been omitted, this block being inserted as the last step in the modified blank display subroutine at 700 to 710 in Fig. 9.

Moving block 572 from its normal position in Fig. 5 to a location in the blank display subroutine has the effect of returning the sequence counter to the count of "1" (the weight display mode) each time the display blank subroutine blocks 700-710 is utilized. Use of the blank display subroutine occurs at block 594 in Fig. 5, where the display blank subroutine is employed for flashing the total price display. With the modified form of the display blank subroutine, from 700-710 in Fig. 9, after the total price has been displayed for one update count, the sequence counter will be returned to "1" and the information stored in the net weight, price per unit weight, and total price RAM memory locations accessed in turn by different routes between blocks 802 and 840 in Fig. 8.

Permanent residing in the weight display mode following platter clearing can be achieved as illustrated by the blocks 567 to 973 in Fig. 9, these blocks being a modified version of the motion testing sequence of block 567-575 in Fig. 5. In Fig. 9, the block 973 is added in order that a jump to the clear price memory subroutine occur in response to detecting motion during a communicate cycle. The clear price subroutine includes setting the sequence counter to "1", block 724, Fig. 7A, accessing and zeroing each digit of the price per unit weight memory, blocks 725-728, clearing the price entry and total key status, blocks 729 and 730, and return to communicate cycle operation. In this sequence, returning the sequencing counter to "1" allows the scale to remain in price per unit weight mode until a new price per unit weight entry is made.

Subroutines In addition to the subroutines already described, Fig. 7 shows subroutines for (1) adding during total value computation, blocks 9637-9642, Fig. 6; (2) transferring between RAM locations for left shifting, RAM locations 11-15; (3) rounding total value; and (4) converting gray code to BCD.

The "add" subroutine, blocks 711-722 in Fig. 7 performes the addition of two digits in the CPU accumulator, block 712 and 714, decimal adjusts the accumulator, transfers the accumulated sum to memory, then increments addresses to access higher order digits, block 719 and transfers the generated carry bit to the accumulator and then to the sum blocks 720 and 721. The decimal adjust step, block 715, is performed by the DAA instructions at line 7340 in Table I. This instruction changes BCD accumulator numbers to decimal weighted numbers as explained in the Intel User's Manual.

The transfer data subroutine, blocks 732-739, reads the first digit of data from original location into the CPU accumulator, block 732, writes the accumulator data into the designated new memory address block 735, and increments both new and old addresses block 737 until the test of block 738 indicates the desired transfer to be complete.

The round subroutine of blocks 755-760 in Fig. 7B includes loading a rounding constant of value of 5 into the accumulator block 755; adding this constant to the number being rounded to determine if it has a value of 5 or more, block 757, decimal adjusting the accumulator contents, block 758 using the DAA instruction at line 7540 in Table I, loading the rounded digits in memory, block 759, testing for the presence of a carry bit indicating next higher number incrementing is to be performed, and adding the carry bit to the accumulator contents for the purpose of incrementing the next higher digit. This next higher digit is a block 762, for the next following trip through the blocks 757-760 sequence. Return to the compute cycle sequence is indicated at block 761.

The code conversion subroutine designates a memory location for receiving the most significant digit of weight information, block 740, collects the first gray code digit to the cleared accumulator, blocks 741 and 742, testing for the previous weight digit being odd or even, block 744, stores the gray code digit in memory, block 747, and converts the gray code digit to binary coded decimal form, block 748. The conversion indicated at block 748 is performed with the table at 7950 in Table I.

The converted gray code digit is written in binary coded decimal form in memory, and if found to be odd, a carry bit is loaded into the CPU accumulator at block 750 for use in making the test of block 744 during the next following trip through the code convert sequence. The memory addresses for both the gray code and BCD converted numbers are decremented at block 751 for the next trip through the block 740-752 sequence. Decrementing of the memory addresses is required since code conversion is performed first on the highest ordered digits. The test of block 752 accesses successively lower order digits in the weight indicating gray code word.

130 000000000000 00000000 NOP 140 000000000001 00101100 FIM P6 0 /ADR OF SEQ CTR 150 00000000 160 000000000011 11010001 LDM 1 170 000000000100 00101101 SRC P6 180 000000000101 11100000 WRM /SET SEQ CTR 190 000000000110 01010010 JMS BLNK /JMP TO BLNK DISP 200 10001000 210 000000001000 00101110 FIM P7 255 /SET UPDATE CTR 220 11111111 230 000000001010 00100010 STRT, FIM P1 0 /ADR OF DISP MEM 240 00000000 250 000000001100 00100100 FIM P2 16 /ADR OF RD-IN MEM 260 00010000 270 000000001110 00100110 FIM P3 33 /ADR.OF ROM OUT 280 00100001 290 000000010000 00101000 FIM P4 234 300 11101010 310 000000010010 00101010 FIM P5 0 /SET WASTE TIME 320 00000000 330 000000010100 00101100 FIM P6 0 /ADR OF SEQ CTR 340 00000000 350 000000010110 11110000 CLB 360 000000010111 01000000 JUN SCAN 370 00011111 380 000000011001 01101011 WAST, INC 11 /INCR WASTE TIME R 390 000000011010 10101011 LD 11 400 000000011011 00011100 JCN NZA WAST /TST REG = 0 410 00011001 420 000000011101 00101010 FIM P5 8 /SET WASTE TIME 430 00001000 440 000000011111 00100011 SCAN, SRC P1 450 000000100000 00100000 FIM PO 240 /ADR .FOR FIN INSTR 460 11110000 470 000000100010 11101001 RDM /RD DISP MEM DIG 480 000000100011 10110001 XCH 1 /EXCH FOR CODE CHANGE 490 000000100100 11111101 DCL 500 000000100101 00110000 FIN PO /CHANGE CODE 510 000000100110 00100011 SREC PI /ADR RAM"Q" OUTPUT 520 000000100111 11100001 WMP /RESET DIG ADR 530 000000101000 00100101 SRC P2 540 000000101001 10110000 XCH O /FETCH IS HALF OF CO@ 550 000000101010 11100010 WRR /WR ON ROM "1" OUTPUTS 560 000000101011 00100111 SRC P3 570 000000101100 10110001 XCH 1 /FETCH 2ND HALF OF COE 580 000000101101 11100010 WRR /WR ON ROM "2" OUTPUTS 590 000000101110 10100111 LD 7 600 000000101111 00100011 SRC P1 /ADR RAM OUTPUT 610 000000110000 11100001 WMP /WR DIG ADR 620 000000110001 11101010 RDR /RD INPUT TO ROM "0" 630 000000110010 00100101 SRC P2 /ADR MEM POS 640 000000110011 11100000 WRM /WR INPUT 650 000000110100 01100011 INC 3 /INCR MEM ADR 660 000000110101 01100101 INC 5 /INCR RD-IN MEM ADR 670 000000110110 01100111 INC 7 /INCR RAM OUT ADR 680 000000110111 01111001 ISZ 9 WAST /CT NO OF DIG SCAND 690 00011001 700 000000111001 00011100 SCA2, JCN NZA KDSA /IST FOR KY DN 710 01000111 720 000000111011 10100111 LD 7 730 000000111100 00100011 SRC P1 /ADR RAM OUTPUT 740 000000111101 11100001 WMP /WR DIG NO 750 000000111110 11101010 .RDR /RD INPUT 760 000000111111 00100101 SRC P2 /ADR MEM POS 770 000001000000 11100000 WRM /WR INPUT 780 000001000001 01100101 INC 5 790 000001000010 01100111 INC 7 800 000001000011 01111000 ISZ 8 SCA2 810 00111001 820 000001000101 00010100 JCN AO WKYD /IST FOR KY DN 830 01101010 840 000001000111 11101101 KOSA, RD1 /RD KY-DN STAT "A" 850 000001001000 11110110 RAR 860 000001001001 11110110 RAR 870 000001001010 0001.0010 JCN Cl KDSB iTST KY-ON STAT "A" 880 01010101 890 000001001100 11101100 RDO /RD MOT STAT 900 000001001101 00011100 JCN NZA KSAI IST FOR MOT 910 01010001 920 000001001111 11011111 LOM 15 930 000001010000 11100110 WR2 /WR MOT RD INHIB 940 000001010001 1.1101101 KSA1, RDI 950 000001010010 11110010 IAC 960 000001010011 01000000 JUN WKYD /JMP TO WR STAT "A" 970 0.1101010 980 000001010101 11110001 KDSB, CLC 990 000001010110 11101101 RD1 1000 000001010111 11110101 RAL 1010 000001011000 00010010 JCN Cl WDZT /TST KY-DN STAT "B" 1020 01101011 1030 000001011010 00100100 FIM P2 21 /ADR OF CLR KY 1040 Q0010101 1050 000001011100 00100101 SRC P2 1060 0000010l1101 11101001 RDM RD CLR KY 1070 000001011110 11.110101 RAL 1080 000001011111 00010010 JCN Cl KSB1 TST CLR KY 1090 01100110 1100 000001100001 00100011 SRC P1 1110 000001100010 11101111 RD3 /RD TOT KY STAT 1120 000001100011 00100101 SRC P2 1130 000001100100 00011100 JCN NZA WKYD /TST FOR TQT KY 1140 01101010 1150 000001100110 00101110 KSB1, FIN P7 255 /SET UPDATE CTR .1160 11111111 1170 000001101000 110111.11 LDM 15 1180 000001101001 11100111 WR3 /WR KY-DN STAT "C" 1190 000001101010 11100101 WKYD, WR1 /WR KY-DN STAT "A" & "B" 1200 / 1210 / WEIGHT DEAD ZONE TEST 1220 / 1230 000001101011 00100100 HDZT, FIM P2 20 /ADR MSD CELL RDG 1240 00010100 1250 000001101101 11110000 CLB 1260 000001101110 00100101 SRC P2 1270 000001101111 11101001 RDM /RD MSD CELLS 1280 000001110000 00010100 JCN AO WDZ1 /TST "M" & "N" = 0 1290 01110011 1300 000001110010 11011111 LDM 15 1310 000001110011 00100011 WDZI, SRC PI 1320 000001110100 11100100 WR0 /WR WDZ STAT 1330 000001110101 00011100 JCN NZA MOTS /TST FOR WDZ 1340 10000111 1350 000001110111 01010010 JMS CLER /JMP TO CLEAR PR MEM 1360 10011011 1370 000001111001 11101110 RD /RD TARE RESET STAT 1380 000001111010 00010100 JCN A0 MOTS /TST FOR TARE RESET 1390 10000111 1400 000001111100 11110000 CLB 1410 000001111101 11100110 WR2 /CLR TARE RESET STAT 1420 000001111110 00100100 FIM P2 28 1430 .00011100 1440 000010000000 00101010 FIM P5 12 /SET NO OF DIG 1450 00001100 1-460 000010000010 00100101 TARZ, SRC P2 /ADR TARE MEM 1470 000010000011 .11100000 WRM /ZERO TARE MEM 1480 000010000100 01100101 INC 5 1490 000010000101 01111011 ISZ .11 TARZ 1500 10000010 1510 / 1520 / MOTION TEST 1530 / 1540 000010000111 00100101 MOTS, SRC.P2 1550 000010001000 11101110 RD2 1560 000010001001 00011100 JCN NZA INDC /TST TO JMP MOT RD 1570 10011101 1580 000010001011 00100100 FIM P2 16 1590 00010000 1600 000010001101 00100101 SRC P2 /ADR INPUT STAT MEM 1610 000010001110 11101001 RDM /RD INPUT STAT 1620 000010001111 11110110 RAR 1630 000010010000 00011010 JCN.CO MOTI /TST FOR MOTION 1640 10011011 1650 000010010010 11011111 LDM 15 1660 000010010011 11100100 WR0 /SET MOT STAT 1670 000010010100 00101101 SRC P6 /ADR SEQ CTR 1680 000010010101 11010001 LoM I 1690 000010010110 11100000 WRM /SET SEQ CTR 1700 000010010111 01010010 JMS BLINK /JMP TO BLANK DISP 1710 10001000 1720 000010011001 01000000 JUN INDC /JMP TO CUNT 1730 10011101 1740 000010011011 11110000 MOT1, CLB 1750 000010011100 11100100 WR0 /RESET MOT STAT 1760 / 1770 / INCREMENT UPDATE COUNTER 1780 / 1790 000010011101 01101111 INDC, INC 15 /INCR UPDATE CTR AS 1800 000010011110 10101111 LD 15 1810 000010011111 00011100 JCN NZA STRT /TST CTR FOR ZERO 1820 00001010 1830 OC0010100001 00101101 SRC P6 /ADR SEQ CTR 1840 000010100010 11010010 LDM 1850 000010100011 11101011 ADM 1860 000010100100 00011010 JCN CO IND1 /TST SEQ CTR = 14 1870 10110001 1880 000010100110 11110001 CLC 1890 000010100111 11010010 LOM 2 1900 000010101000 10001110 ADD 1-4 1910 000010101001 00011010 JCN CO IND4 /TST CTR "B" = 14 1920 11001000 1930 000010101011 11011111 LDM 15 1940 000010101100 11100000 WRM /SET SEQ CTR = 15 1950 000010101101 01010010 JMS BLNK /JMP TO BLANK DISP 1960 10001000 1970 000010101 111 01000000 JUN IND4 1980 11001000 1990 000010110001 11110010 IND1, IAC 2000 000010110010 00010010 JCN Cl IND4 /TST SEQ CTR = 13 2010 11001000 2020 000010110100 00100010 FIM P1 9 2030 00001001 2040 000010110110 00100011 SRC P1 /ADR MSD OF STOR MEM 2050 000010110111 11010110 LOM 6 2060 000010111000 11101011 ADM 2070 000010111001 00011010 JCN CO IND4 /1ST FOR "-" SIGN 2080 11001000 2090 000010111011 10101110 LD 14 2100 000010111100 11.110.110 .RAR 2110 000010111101 11110110 .RAR 2120 000010111110 00011010 JCN CO IND2 /TST CTR flag FOR BIN 2 2130 11000011 2140 000011000000 11011111 LDM 15 /LD BLNK CODE IN ACCM 2150 000011000001 01000000 JUN IND3 2160 11000100 2170 000011000011 11011011 IND2, LDM 11 /LD "-" SIGN IN ACCM 2180 000011000100 00100010 IND3, FIM P1 4 2190 00000100 2200 000011000110 00100011 SRC P1 /ADR MSD OF DISP MEM 2210 000011000111 11100000 MRM /WR "- OR "BLNK" 2220 000011001000 11110001 IND4, CLC 2230 000011001001 01101110 INC 1-4 /INCR UPDATE CTR "B" 2240 000011001010 10101110 LD 14 2250 000011001011 00011100 JCN NZA STRT /TST CTR FOR ZERO 2260 00001010 2270 000011001101 00101110 FIM P7 85 /SET UPDATE CTR 2280 01010101 2290 / 2300 /KEY ENTRY TEST 2310 / 2320 000011001111 00100101 SRC P2 2330 000011010000 11101111 RD3 /RD KY-DN STAT "C 2340 000011010001 11100110 WR2 2350 000011010010 00011100 JCN NZA KET3 /TST KY-DN STAT "C" 2360 11011010 2370 000011010100 00100010 KET2( FIM P1 5 2380 00000101 2390 00001 10101 10 C0100011 SRC P1 /ADR UPDATE CTR STAT 2400 000011010111 11100000 WRM /WR UPDATE CTR STAT 2410 000011011000 01000001 JUN RDP2 2420 01101011 2430 000011011010 01000001 KET3, JUN KETS /JMP TO TST KY ENTRY 2440 00000000 2450 *240 2460 000011110000 10111111 191 2470 000011110001 10000110 134 2480 000011110010 .11011011 219 2490 000011110011 11001111 207 2500 000011110100 11100110 230 2510 000011110101 11101101 237 2520 000011110110 11111101 01 253 2530 000011110111 10000111 135 2540 000011111000 11111111 255 2550 000011111001 11101111 239 2560 00001111010 00000110 6 2570 000011111011 01000000 64 2500 000011111100 00000111 7 2590 000011111101 00011000 24 2600 000011111110 00101000 40 2610 000011111111 00000000 0 2620 *256 2630 000100000000 11110000 KETS, CL8 2640 000100000001 11100111 WR3 /RESET KY-DN STAT "C" 2650 000100000010 00100100 FIM P2 21 /ADR OF KY MEM 2660 00010101 2670 000100000100 00100110 FIM P3 0 /KY NO CORR CNST 2680 00000000 2690 000100000110 00101010 FIM P5 13 /SET NO OF DIG 2700 00001101 2710 000100001000 00101110 FIM P7 128 /SET UPDATE CTR 2720 10000000 2730 000100001010 00100101 KETI, SRC P2 2740 000100001011 11101001 RDM /RD KY NO 2750 000100001100 00011100 JCN NZA RDKY /TST KY 110 = 0 2760 00010110 2770 000100001110 01100101 INC 5 /INCR KY ADR 2780 000100001111 11010100 LDM 4 2790 000100010000 10000111 ADD 7 2800 000100010001 10110111 XCH 7 /SET NEW CORR 2810 000100010010 01111011 ISZ 11 KET1 /TST NO OF DIG 2820 00001010 2830 000100010100 01000000 KET4, JUN KET2 /J).1P - UPDATE CTR STAT 2840 11010100 2850 / 2860 /READ KEY ROUTINE 2870 / 2880 000100010110 00100000 RDKY, FIN PO 240 /ADR FOR FIN INSTR 2890 11110000 2900 000100011000 11111100 KBP 2910 000100011001 11110100 CMA 2920 000100011010 00010100 JCN AO RDPI /TST FOR MPL KYS 2930 10000000 2940 000100011100 11.110100 ClIA 2950 000100011101 10000111 ADD 7 /ADD CORRECTION 2960 000100011110 10110001 XCH 1 2970 000100011111 001.10000 FIN PO /XCH CODES 2900 000100100000 00100011 SRC P1 2990 000100100001 11101100 RDO /RD WDZ STAT 3000 000100100010 00011100 JCN NZA RDPR /TST WDZ 3010 010001 10 3020 000100100100 00100100 FIM P2 16 3030 00010000 3040 000100100110 00100101 SRC P2 /ADR STAT SW MEN 3050 000100100111 11101001 RDM /RD STAT SW MEM 3060 000100101000 11110110 RAR 3070 OC0100101001 11110110 RAR 3080 000100101010 00010010 JCN C1 RDP1 /TST FOR TARE INHIB 3090 10000000 3100 000100101100 00100100 FIM P2 28 3110 00011100 3120 000100101110 00100101 SRC P2 /ADR TARE MEM 3130 000100101111 11010100 LDM 4 3140 000100110000 10000001 ADD 1 3150 000100110001 00010010 JCN C1 RDK1 /TST FOR TOT KY 3160 00111110 3170 000100110011 11110010 IAC 3180 000100110100 00010010 JCN C1 ZTAR /TST FOR CLR KY 3190 01000000 3200 000100110110 00100010 FIM P1 29 /ADR OF 2ND DIG TARE 3210 OOOIJ101 3220 000100111000 11101001 RDM /RD IST DIG TARE 3230 000100111001 00100011 SRC P1 3240 000100111010 11100000 WRM /WR IN 2ND DIG POS 3250 000100111011 00100101 SRC P2 /ADR IST DIG MEM 3260 000100111100 10100001 LD I 3270 0001G0111101 11100000 WRM (WR NO IN TARE MEM 3280 000100111110 01000001 RDKI, JUN START 2 3290 10000100 3300 OD0101000C00 00101010 ZTAR, FIM P5 12 /SET NO OF DIG 3310 00001100 3320 000101000010 00101110 FIN P7 255 /SET UPDATE CTR 3330 1111111 3340 OC0101000100 01000000 JUN TARZ /JMP TO ZERO TARE 3350 10000010 3360 OC0101000110 11011011 RDPR, L9M 11 3370 000101000111 10010001 SUB 1 3380 000101001000 00010100 JCN AO ZKEY /TST FOR CLR KY 3390 01111110 3400 000101001010 11110001 CLC 3410 000101001011 11101111 RD3 /RD TOT KY STAT 3420 000101001100 00011100 JCN NZA RDPI /TST FOR PREV TOT 3430 10000000 3440 000101001110 11010100 LWA 4 3450 000101001111 10000001 ADD 1 3460 000101010003 00010010 JCN Cl DKEY /TST FOR TOT KY 3470 01110001 3460 000101010010 10100001 LD 1 3490 000101010011 C0100000 FIN PO 10 3500 00001010 3510 000101010101 00100001 SRC P0 /ADR PR ENTRY MEM 3520 000101010110 11100000 WRM /WR ND 3530 000101010111 00100010 FIM P1 43 /ADR OF LS REG 3540 00101011 3550 000101011001 00100100 FIM P2.11 /SET NO OF DIG 3560 00001011 3570 000101011011 01010010 JMS TRNS /XFR PR TO LS REG 3580 10101011 3590 000101011101 00100000 FIM P0 43 /ADR OF LS REG 3600 00101011 3610 000101011111 00100010 FIM P1 .11 /ADR OF PR MEM 3620 00001011 3630 000101100001 00100100 FIN P2 27 /SET NO OF DIG 3640 00011011 3650 000101100011 01010010 JMS TRNS /XFR PR TO MEM 3660 10101011 3670 000101I00101 11011111 LDM 15 3680 000101100110 11100101 till 3690 000101100111 00100010 FIM P1 5 3700 00000101 3710 000101101001 00100011 SRC P /ADR UPDATE CTR STAT 3720 000101101010 11100000 flRN /SET UPDATE CTR STAT 3730 000101101011 00100101 RDP2, S1?C P2 3740 000101101100 11101100 RDO 3750 000101101101 0001100 JCN NZA RDP1 /TST MOT STAT 3760 10000000 3770 000101101111 .01000010 JUN TSEQ 3780 00000000 3790 000101110001 11110001 DKEY, CLO 3800 000101110010 11101101 RD 1 /RD PR ENTRY STAT 3810 000101110011 00010100 JCN A0 RDPI /TST PR ENTRY STAT 3820 10000000 3830 000101.110101 11100111 WR3 /SET TOT KY STAT 3840 000101110110 11100110 WR2 SET TARE RESET STAT 3850 000101110111 00100100 FIM P2 16 3860 00010000 3870 000101111001 00100101 SRC P2 /ADR INPUT STAT MEM 3880 000101111010 11101001 RDM /RD INPUT STAT 3890 000101111011 101+1110 XCH 14 /SET UPDATE CTR 3900 000101111100 01000001 JUN RDP2 /JMP TO NOT STAT TST 3910 01101011 3920 000101111110 01010010 ZKEY, JMS.CLER /JMP TO CLR PR MEM 3930 10011011 3940 000110000000 03101110 RDP1, FIM P7 255 /SET UPDATE CTR 3950 11111111 3960 000110000010 01000000 JUN STRT /RETURN TO START 3970 0000l0l0 3980 / 3990 / WEIGHT RANGE TEST 4000 / 4010 000110000100 00100100 WTRT, FIN P2 18 /ADR OF 2ND DIG CELLS 4020 00010010 4030 000110000110 00100101 SRC P2 4040 000110000111 11101001 RDM 4050 000110001000 11110110 RAR 4060 000110001001 00011010 JCN CO WTRD /TST "E" IN DARK 4070 10010100 4080 000110001011 11110110 RAR 4090 000110001100 11110110 RAR 4100 000110001101 00011010 JCN CO WTRD /TST G IN DARK 4110 10010100 4120 000110001111 00101101 SRC P6 /ADR SEQ CTR 4130 000110010000 11010001 LDM 1 4140 000110010001 11100000 WRM /SET SEQ CTR = 1 4150 000110010010 01000010 JUN ERRD /JMP TO DISP ERROR 4160 01111100 4170 / 4180 / COMPUTE NET WEIGHT 4190 / 4200 000110010100 01010010 WTRD, JMS CDCH /JMP TO CNVT CODE 4210 11010100 4220 000110010110 00100000 CNWT, FIM P0 17 /ADR OF WT MEM 4230 00010001 4240 000110011000 00100010 FIM P1 28 /ADR OF TARE MEM 4250 00011100 4260 000110011010 00100100 FIM P2 5 /ADR OF STOR MEM 4270 00000101 4280 000110011100 00100110 FIM P3 10 /SET CORR CONSTANT 4290 00001010 4300 000110011110 00101000 FIM P4 32 /ADR OF TARE STAT 4310 00100000 4320 OC0110100000 00101010 FIM P5 12 /SET NO OF DIG 4330 00001100 4340 000110100010 11110000 SUB5, CLB 4350 000110100011 00100001 SUB1, SRC P0 /ADR WT MEM (MINUEND) 4360 000110100100 11101001 RDM 4370 000110100101 00100011 SRC P1 /ADR TARE (SUBTRAHEND 4380 000110100110 11101000 SBM 4390 000110100111 00010010 JCN C1 SUB1 /TST FOR CORR REQMT 4400 10101100 4410 000110101001 10000111 ADD 7 4420 000110101010 01000001 JUN SUB2 4430 10101101 4440 000110101100 11110001 SUB3, CLO 4450 000110101101 01100101 SUB2, INC 5 4460 000110101110 00100101 SRC P2 /ADR STOR MEM (DIFF) 4470 000110101111 11100000 WRM /WR VALUE 4480 000110110000 01100001 INC I 4490 000110110001 01100011 INC 3 4500 000110110010 01111011 ISZ 11 SUB1 /TST NO OF DIG 4510 10100011 4520 000110110100 00011010 JCN C0 SUB4 /TST VALID SUBT 4530 11000000 4540 000110110110 00100000 FIM P0 28 /ADR OF TARE MEM 4550 00011100 4560 000110111000 00100010 FIM.PI 17 /ADR OF WT .MEM 4570 00010001 4580 000110111010 00100100 FIM P2 5 /ADR OF STOR MEM 4590 00000101 4600 000110111100 00101010 FIM P5 44 /SET NO OG DIG 4610 00101100 4620 000110111110 01000001 JUN SUB5 /JMP - SUBT WT FRM TAR 4630 10100010 4640 000111000000 10101010 SUB4, LD 10 4650 000111000001 00101001 SRC P4 /ADR TARE STAT 4660 000111000010 11100100 WR0 /WR TARE STAT 4670 000111000011 00010100 JCN A0 WTDS /TST IST OR 2ND SUBTN 4680 110011000 4690 000111000101 00100101 SRC P2 4700 000111000110 11011011 LDM 11 4710 000111000111 11100000 WRM /WR "-" SIGN IN MSD 4720 / 4730 / TRANSFER WEIGHT TO DISPLAY 4740 / 4750 000111001000 00101101 WTDS, SRC P6 /ADR SEQ CTR 4760 000111001001 11010010 LDM 2 4770 000111001010 11101011 ADM 4780 000111001011 00010010 JCN C1 WTD3 /TST SEQ CTR = 14 4790 11011111 4800 000111001101 03100000 FIM PO 6 /ADR OF STOR MEM 4810 00000110 4820 000111001111 00100010 FIM P1 1 /ADR OF DISP MEM 4830 00000001 4840 000111010001 00100100 FIN P2 12 /SET NO OF DIG 4850 00001100 4860 000111010011 11101100 RD0 /RD WDZ STAT 4870 000111010100 00011100 JCN NZA "TD1 /TST WDZ 4880 11011001 4890 000111010110 11011010 LDM 10 /LD 10 CODE IN ACCM 4900 000111010111 01000001 JUN WTD2 4910 11011010 4920 000111011001 11011100 WTD1, LDM 12 /LD CODE "12" IN ACCM 4930 000111011010 11100000 WTD2, WRM /WR CODE IN SEQ CTR 4940 000111011011 01010010 JMS TRNS /XFR STOR MEM TO DISP 4950 10101011 4960 000111011101 01000010 JUN DIST /JMP TO DISP TEST 4970 01110010 4980 000111011111 01000010 WTD3, JUN COMT /JMP TO CMPT TST 4990 00100000 5000 *496 5010 000111110000 00000000 0 5020 000111110001 00000001 1 5030 000111110010 00000100 4 5010 000111110011 00000111 7 5050 000111110100 00001011 11 5060 000111110101 00000010 2 5070 000111110110 00000101 5 5080 000111110111 00001000 8 5090 000111111000 00000000 0 5100 000111111001 00000011 3 5110 000111111010 00000110 6 5120 000111111011 00001001 9 5130 000111111100 00001100 12 5140 000111111101 00000000 0 5150 000111111 110 00000000 0 5160 000111111111 00000000 0 5170 *512 5180 / 5190 / SEQUENCE COUNTER TEST 5200 / 5210 001000000000 00101101 TSEQ, SRC P6 /ADR SED CTR 5220 001000000001 11010010 LDM 2 5230 001000000010 11101011 ADM 5240 001000000011 00010010 JCN C1 TSEI /TST CTR = CODE 14 5250 00001100 5260 001000000101 11110010 IAC 5270 001000000110 00010010 JCN C1 COMT / TST CTR = CODE 13 5280 00100000 5290 001000001000 11010110 LDM 6 5300 001000001001 11101011 ADM 5310 0010000001010 00010010 JCN CI TPRE /TST CTR > CODE ) 5320 00001110 5330 10000100 TSEI, JUN WTRT /JUMP TO WT RG TST 5340 10000100 5s / 5360 / PRICE ENTRY TEST 5370 / 5380 001000001110 00100011 TPRE, SRC P1 /ADR PR ENTRY STAI 5390 001000001111 11110001 CLC 5400 001000010000 11101101 RDI /RD PR ENTRY STAT 5410 001000010001 00010100 JCN AO TSEI /TST FOR PR ENTRY 5420 0000100 5430 001000010011 00101101 PREI, SRC P6 /ADR SEQ CTR 5440 001000010100 11011101 LDM 13 5450 001000010101 11100000 WRM /SET SEQ CTR = 13 5460 001000010110 00100000 FIM PO 11 /ADR OF PR MEM 5470 00001011 5480 001000011000 00100010 FIM P1 1/ADR OF DISP MEM 5490 00000001 5500 001000011010 00100100 FIM P2 12 /SET NO OF DIG 5510 00001100 5520 001000011100 01010010JMS TRNS /XFR PR TO DISP 5530 10101011 5540 001000011110 01000010 JUN DIST /JMP TO DISP TEST 5550 01110010 5560 / 5570 / COMPUTE TOTAL PRICE 5580 / 5590 001000100000 00100010 COMT, FIM P1 5 5600 00000101 5610 001000100010 00100011 SRC pi /ADR FUNC SW STAT 5620 001000100011 11101111 RD3 /RD STAT 5630 001000100100 00010100 JCN AO PREI /TST FOR TOT KY 5640 00010011 5650 001000100110 11101001 RDM /RD UPDATE CTR STAT 5660 001000100111 00011100 JCN NZA PREI /TST FOR ZERO 5670 00010011 5680 001000101001 11110000 COMP, CLB 5690 001000101010 00100010 FIM P1 32 5700 00100000 5710 001000101100 00101010 FIM PS 8 5720 00001000 5730 001000101110 00100011 PROZ, SRC P1 /ADR PROD MEM 5740 001000101111 11100000 WRM /ZERO PROD MEM 5750 001000110000 01100011 INC 3 5760 001000110001 01111011 ISZ 11 PROZ /CT MO OF DIG 5770 00101110 5780 001000110011 11101100 RDO /RD TARE STAT 5790 001000110100 00011100 JCN NZA ERRD /JMP TO ERROR 5800 01111100 5810 001000110110 00101010 FIM P5 12 5820 00001100 5830 001000111000 00101000 FIM P4 11 /ADR OF MPLR 5840 00001011 5850 001000111010 00101001 MPY4, SRC P4 5860 001000111011 11101000 SBM /16 COMP - MPLR DIG 5870 001000111100 00010100 JCN AO MPY2 /TST FOR ZERO 5880 01001011 5890 001000111110 10111010 XCH 10 /STOR COMP - MPLR DIG 5900 001000111111 00100110 MPY, FIM P3 12 5910 00001100 5920 001001000001 00100100 FIM P2 35 /ADR OF PROD 5930 00100011 5940 001001000011 00100010 FIM P1 35 /ADR OF PART PROD 5950 00100011 5960 001001000101 00100000 FIM P0 6 /ADR OF MPLCN 5970 00000110 5980 001001000111 01010010 JMS ADD /ADD MPLCN TO PART PROD 5990 10110101 6000 001001001001 01111010 ISZ 10 MPY1 /INCR MPLR DIG COMP 6010 00111111 6020 C01001001011 01101001 MPY2, INC 9 6030 001001001100 01111011 ISZ 11 MPY3 6040 01010000 6050 001001001ll0 01000010 JUN VLRD /JMP TO ROD VAL 6060 01011101 6070 001001010000 00100000 MPY3, FIM PO 33 6080 00100001 6090 001001010010 00100010 FIM P1 32 6100 00100000 6110 001001010100 00100100 FIR P2 8 6120 00001000 6130 001001010110 01010010 JMS TRNS /SHIFT TART PROD 6140 10101011 6150 001001011000 11110000 CLB 6160 001001011001 00100011 SRC P1 6170 001001011010 11100000 WRM /ZERO MSD 6180 001001011011 01000010 JUN MPY4 /JMP TO CONT MULT 6190 00111010 6200 / 6210 / ROUND VALUE & TRANSFER TO DISPLAY 6220 / 6230 001001011101 00100000 VLRD, FIM PO 33 /ADR OF DIG TO RRD 6240 00100001 6250 001001011111 01010010 JMS RND /RND TOTAL PRICE 6260 11000111 6270 001001100001 00101101 VLTR; SRC P6 /ADR SEQ CTR 6280 001001100010 11011110 LDM 14 6290 001001100011 11100000 WRM /SET SEQ CTR = 14 6300 001001100100 00100000 FIM P0 34 /ADR OF LSD VAL 6310 00100010 6320 001001100110 00100010 FIM P1 1 /ADR OF DISP MEM 6330 00000001 6340 001001101000 00100100 FIM P2 12 /SET NO OF DIG 6350 00001100 6360 001001101010 01010010 JMS TRNS /XFR VAL TO DISP 6370 10101011 6380 001001101100 00100001 SRC P0 /ADR 5TH DIG VAL 6390 001001101101 11101001 RDM 6400 001001101110 00010100 JCN A0 DIST /TST FOR ZERO 6410 01110010 6420 001001110000 01000010 JUN ERRD /JMP TO DISP ERROR 6430 01111100 6440 / 6450 / DISPLAY TEST 6460 / 6470 001001110010 00100000 DIST, FIM P0 4 /ADR MSD OF DISP MEM 6480 00000100 6490 001001110100 00100001 SRC P0 6500 001001110101 11101001 RDM /RD MSD 6510 001001110110 00011100 JCN NZA DISI /TST MSD = 0 6520 01111010 6530 001001111000 11011111 LDM 15 6540 001001111001 11100000 WRM /BLINK MSD 6550 001001111010 01000000 DISI, JUN STRT /RETURN TO START 6560 00001010 6570 / 6580 / ERROR DISPLAY 6590 / 6600 001001111100 00100000 ERROR, FIM P0 1 /ADR OF DISP MEM 6610 00000001 6620 001001111110 00101010 FIM P5 12 /SET NO OF DIG 6630 00001100 6640 001010000000 11011011 LDM 11 6650 001010000001 00100001 ERR1, SRC P0 6660 001010000010 11100000 WRM /WR ERROR CODE 6670 001010000011 01100001 INC 1 /INCR DIG ADR 6680 001010000100 01111011 ISZ 11 ERR1 /TST NO OF DIG 6690 10000001 6700 001010100110 01000000 JUN STRT /RETURN TO START 6710 00001010 6720 / 673u / BLANK DISPLAY ROUTINE 6740 / 6750 001010001000 00100000 BLNK, FIM P0 1 /ADR OD DISP MEM 6760 00000001 6770 001010001010 00100010 FIM P1 6 /ADR OF STOR MEM 6780 00000110 6790 001010001100 00101010 FIM P5 204 /SET NO OF DIG 6800 11001100 6810 001010001110 1111000 CLB 6820 001010001111 00100011 BLN1, SRC P1 /ADR STOR MEM 6830 001010010000 11100000 WRM /CLEAR STOR MEM 6840 001010010001 01100011 INC 3 6850 0010100100010 01111010 ISZ 10 BLN1 /TST NO OF DIG 6860 10001111 6870 001010010100 11011111 LDM 15 /LD BLNK CODE 6880 001010010101 00100001 BLN2, SRC P0 /ADR DISP MEM 6890 001010010110 11100000 WRM /WR BLNK CODE 6900 001010010111 01100001 INC 1 6910 001010011000 01111011 ISZ 11 BLN2 /TST NO OF DIG 6920 10010101 6930 001010011010 11000000 BBL 0 /RETURN 6940 / 6950 / CLEAR PRICE ROUTINE 6960 / 6970 001010011011 11010001 CLER, LDM 1 6980 001010011100 00101101 SRC P6 /ADR SEQ CTR 6990 001010011101 11100000 WRM /SET SEQ CTR = 1 7000 001010011110 00100000 FIM P0 10 /ADR OF PR MEM 7010 00001010 7020 001010100000 00101010 FIM P5 10 /SET NO OF DIG 7030 00001010 7040 001010100010 11110000 CLB 7050 001010100011 00100001 CLR1, SRC P0 /ADR DIG 7060 001010100100 11100000 WRM /ZERO DIG 7070 001010100101 01100001 INC 1 /INCR MEM ADR 7080 001010100110 01111011 ISZ 11 CLR1 /TST NO OF DIG 7090 10100011 7100 001010101000 11100101 WR1 /ZERO PR STAT 7110 001010101001 11100111 WR3 /ZERO TOT KY STAT 7120 001010101010 11000000 BBL 0 /RETURN 7130 / 7140 / TRANSFER DATA ROUTINE 7150 / 7160 001010101011 11110000 TRNS, CLB 7170 001010101100 00100001 TRN1, SRC P0 /ADR DATA 7180 001010101101 11101001 RDM /RD DATA 7190 001010101110 00100011 SRC P1 /ADR NEW LOCATION 7200 001010101111 11100000 WRM /WR DATA 7210 001010110000 01100001 INC 1 /INCR OLD DATA ADR 7220 001010110001 01100011 INC 3 /INCR NEW DATA ADR 7230 001010110010 01110101 ISZ 5 TRN1 /INCR CHAR CTR 7240 10101100 7250 001010110100 11000000 BBL 0 7260 / 7270 / ADD ROUTINE 7280 / 7290 001010110101 11110000 ADD, CLB 7300 001010110110 00100001 ADD1, SRC P0 /ADR ADDEND 7310 001010110111 11101001 RDM /RD ADDEND 7320 001010111000 00100011 SRC P1 /ADR AUGEND 7330 001010111001 11101011 ADM /ADD AUGEND 7340 001010111010 11111011 DAA /ECD ADJUST 7350 001010111011 00100101 SRC P2 /ADR SUM 7360 001010111100 11100000 WRM /WR SUM 7370 001010111101 01100001 INC 1 7380 001010111110 01100011 INC 3 7390 001010111111 01100101 INC 5 7400 001011000000 01110111 ISZ 7 ADD1 /INCR CHAR CTR 7410 10110110 7420 001011000010 11110111 TCC 7430 001011000011 00100101 SRC P2 /ADR SUM 7440 001011000100 11101011 ADM /ADD LAST CARRY 7450 001011000101 11100000 WRM /WR SUM 7460 001011000110 11000000 BBL 0 7470 / 7480 / ROUND ROUTINE 7490 / 7500 001011000111 11110000 RND, CLB 7510 001011001000 11010101 LDM 5 7520 001011001001 00100001 RND2, SRC P0 /ADR RND DATA 7530 001011001010 11101011 ADM 7540 001011001011 11111011 DAA 7550 001011001100 11100000 WRM /WR ROUNDED DATA 7560 001011001101 00010010 JCN C1 RND4 /TST FOR CARRY 7570 11010000 7580 001011001111 11000000 BBL 0 7590 001011010000 11110111 RND4, TCC /XFR CARRY 7600 001011010001 01100001 INC 1 7610 001011010010 01000010 JUN RND2 /JMP TO RND MORE DIG 7620 11001001 7630 / 7640 / HOBART TO BCD CODE CONVERSION 7650 / 7660 001011010100 00100100 CDCM, FIM P2 20 /ADR OF CELL READING 7670 00010100 7680 001011010110 00101000 FIM P4 12 7690 00001100 7700 001011011000 00100000 FIM P0 240 /ADR OF CHAR TABLE 7710 11110000 7720 001011011010 11110000 CLB 7730 001011011011 00100101 CDC, SRC P2 /ADR CHAR 7740 001011011100 11101001 RDM /RD CHAR 7750 001011011101 00010010 JCN C1 BINV /TST FOR ODD-EVEN 7760 11101011 7770 001011011111 10110001 INVR, XCH 1 /STOR FOR FIN INSTR 7780 001011100000 00110010 FIN P1 7790 001011100001 10100011 LD 3 /LD NEW CHAR IN ACC 7800 001011100010 11100000 WRM /WR TO MEM 7810 001011100011 10100101 LD 5 7820 001011100100 11111000 DAC 7830 001011100101 10110101 XCH 5 /MODIFY CELL MEM ADR 7840 001011100110 10100011 LD 3 7850 001011100111 11110110 RAR /STOR UDD-EVEN BIT 7860 001011101000 01111001 ISZ 9 CDC /CONV 4 DIG 7870 11011011 7880 001011101010 11000000 BBL 0 7890 001011101011 11110101 BINV, RAL 7900 001011101100 11110011 CMC /COMP 4TH BIT 7910 001011101101 11110110 RAR 7920 001011101110 01000010 JUN INVR 7930 11011111 7940 *752 7950 001011110000 00000000 0 7960 001011110001 00000000 0 7970 001011110010 00000010 2 7980 001011110011 00000001 1 7990 001011110100 00000100 4 8000 001011110101 00000000 0 8010 001011110110 00000011 3 8020 001011110111 00000000 0 8030 001011111000 00000000 0 8040 001011111001 00001001 9 8050 001011111010 00000111 7 8060 001011111011 00001000 8 8070 001011111100 00000101 5 8080 001011111101 00000000 0 8090 001011111110 00000110 6 8100 001011111111 00000000 0 TABLE II CODE ASSIGNMENTS SEQ CTR ROM "1" ROM "2" RAM "0" STAT SW CODES OUTPUT OUTPUT OUTPUT CODES ASSIGNMENT 1 & 10 = Lb only 0 = e, per lb 0 = a 0000 = "0" reset 0 = motion sig 12 = price/lb 1 = f, total 1 = b, lb 0001 = D1 = ident lamps = stat sw 1 = tare inhibit 13 = total pr. 2 = g 2 = c, wt 0010 = D2 = 1st sig dig = ABCD cells 2 = 1.0 sec pr disp 15 = blank 3 = dec.pt. 3 = d, price 0011 = D3 = 2nd sig dig = EFGH cells 3 = 0.7 sec pr disp 0100 = D4 = 3rd sig dig = IJKL cells 0101 = D5 = 4th sig dig = MN cells 0110 = D6 = ) 0111 = D7 = ) Keyboard strobes 1000 = D8 = ) While the forms of apparatus herein described constitute preferred embodiments of this invention, it is to be understood that the invention is not limited to these precise forms of apparatus, and that changes may be made therein without departing from the scope of the invention as defined in the appendent claims.

Claims (28)

WHAT WE CLAIM IS:

1. A weighing scale having total price computing capability comprising a platter, means for generating data in code corresponding to the weight of a commodity on said platter and including an output for such coded weight data, display means including a multi-digit numerical indicator, means for generating price per unit weight data in code and including an output for such coded price per unit weight data, calculating means having an input connected to accept said coded weight data and said coded price per unit weight data from said outputs and being operable to multiply the two to produce in code data defining the total price of a weighed commodity, said calculating means having an output for the total price code data, control means associated with said calculating means for causing said calculating means to interrogate said means for generating coded weight data and said means for generating coded price per unit weight data and to multiply the weight data entered in said calculating means by the entered price per unit weight, said control means also including means for selectively displaying numbers corresponding to at least two of said outputs on said numerical indicator in a predetermined sequence.

2. A scale as claimed in claim 1 wherein said control means includes means for intensity modulating said display when a number corresponding to total price data is displayed.

3. A scale as claimed in claim 1 or claim 2 further including means for returning said display means to displaying one of said outputs in response to platter motion.

4. A scale as claimed in any one of the preceding claims wherein said display means comprises a plurality of horizontally aligned electrically illuminatable numeric display devices.

5. A weighing scale as claimed in claim 4 wherein each numeric display device has seven segments selectively illuminatable to display any one numeral from 0 to 9.

6. A weighing scale as claimed in any one of the preceding claims wherein said means for generating price per unit weight data comprises a keyboard having numerical keys and a clear key, said clear key being connected to said control means to cause said display means to return the beginning of its sequence and to enable entry of new price per unit weight information.

7. A scale as claimed in any one of the preceding claims wherein said calculating means is a microprocessor.

8. A scale as claimed in any one of the preceding claims further including means providing a tare weight signal output corresponding to the weight of platter commodity packaging and wherein said calculating means receives said tare weight signal and said commodity weight code data and generates therefrom a net weight signal.

9. A scale as claimed in claim 8 including means responsive to the weight signal being less than a predetermined value for enabling entry of said tare signal into said computing means, means transmitting said tare signal to said display means prior to display of weight of an article, and means indicating that the number displayed is a tare entry.

10. A scale as claimed in any one of the preceding claims further including indicator means associated with display means and operable to indicate to what a number displayed by said numerical indicator corresponds.

11. A scale as claimed in claim 10, wherein said control means are operative sequentially to drive said numerical indicator to display numbers corresponding to weight, price per unit weight, and total price and simultaneously illuminates the appropriate said indicator means to identify the number being displayed.

12. A scale as claimed in claim 10 or claim 11 comprising sensing means operable to detect changing of data from said output of said weight code generating means, means for selectively displaying numbers corresponding to each of said outputs on said numerical indicator in a predetermined sequence and to actuate said indicator means to denote the type of data displayed on said numerical indicator, said sensing means having a connection to said control means for causing said display to revert to display of the number corresponding to the -first displayed coded data if the display has advanced in sequence beyond the first display and there is a change in weight code output.

13. A scale as claimed in claim 12 wherein said means for providing a price per unit weight signal comprises a manually operable keyboard commonly supported with said scale, and means inhibiting operation of said sensing means for a predetermined time following keyboard actuation for inhibiting false sensing means operation with key movement.

14. A scale as claimed in claim 11, including sensing means sensing changing of data from said output of said weight code generating means, and blanking means responsive to said sensing means to blank said display means so long as the output of said weight code generating means is not at a steady state.

15. A scale as claimed in claim 12 further including means for causing the display sequence to repeat as far as it progressed prior to said weight code output change.

16. A scale as claimed in claim 12 wherein said display is operative to display numbers sequentially indicating a) weight of an article placed on the scale, b) the price per unit weight, c) the total price of the article, and said control means returns said one display to a weight indication upon change in weight signal without returning to zero weight and without removing the entire article, and then advances said one display to the condition it obtained prior to such change in weight signal.

17. A scale as claimed in claim 16, wherein said control means provides a minimum display time for number indicating weight and price per unit weight upon sequencing after detection of change in weight signal.

18. A scale as claimed in claim 12 wherein said calculating means is operative after said platter has again come to rest to recompute the total value by multiplying any new weight signal by the stored price per unit weight data, and means for reinitiating sequential display of said weight and price on said common display means.

19. A scale as claimed in claim 18 wherein said reinitiating means is automatically operable whenever a price per unit weight signal has been stored in said memory means, and said scale further includes time delay means for temporarily retaining display of the price per unit weight prior to display of a new total price.

20. A scale as claimed in claim 19 wherein said common display means displays both said weight and price per unit weight in sequence followed by display of the total price of the article on the platter.

21. A scale as claimed in claim 20 including means for clearing said memory means of price per unit weight data and reinstating display of weight in response to such clearing.

22. A scale as claimed in any one of the preceding claims further including means detecting a data error condition during operation of said calculating means, and means responsive to said data error detecting means for causing said display to display a unique error indicating pattern.

23. A scale as claimed in claim 22 wherein said error detecting means is responsive to a plurality of different error conditions, and said means responsive to said error detecting means causes different error display patterns for each of the error conditions.

24. A scale as claimed in any one of the preceding claims further including means responsive to change in the weight code data and operative to clear all information previously input to said calculating means.

25. A scale as claimed in claim 24 further including means for entering tare weight data representing article package weight into said calculating means, and wherein both tare weight data and price per unit weight data are cleared from said calculating means.

26. A scale as claimed in claim 25 wherein clearing of said tare weight data is conditional upon the total price of the article having been determined by said calculating means.

27. A scale as claimed in any one of claims 21 to 26 including memory means for storing the tare signal until a weighing and pricing transaction has been completed whether or not the article is removed from the platter, and means for erasing said tare signal from said memory means when said platter is emptied following a completed transaction.

28. A weighing scale substantially as hereinbefore described with reference to the accompanying drawings.