GB1564626A - Inverter system - Google Patents

Description

(54) INVERTER SYSTEM (71) I, DONALD FRASER PAR TRIDGE of 439 Aldo Avenue, Santa Clara, State of California 95050, United States of America, a citizen of the United States of America, do hereby declare the invention for which I pray that a patent may be granted to me, and the method by which it is to be performed, to be particularly described in and by the following statement: The present invention relates to an inverter system. A particular,-though not exclusive, application of the invention is to high frequency inverters such as are used in induction heating where it is required to control the supply of electrical power at frequencies in the range of 10 KHz to 200 KHz and higher. Other uses for high frequency inverters involve low frequency radio frequency generation and other areas in which high power at high frequencies is required including AM, FM and code generation.

Information on the subject of high frequency inverters have been disclosed in U.S. Patent 3,725,768, Brian R. Pelly, Issued April 3, 1973, and U.S. Patent No.

3,328,596, Fritz Germann, Issued June 27, 1967. Similar disclosures have also been made in the following publications: 1. General Electric SCR Manual, Fourth Edition, Page 254.

2. High Frequency, Silicon Controlled Rectifier Sinusoidal Inverter, by R. Thompson, in the Proceedings I.E.E. Vol. 110, No.

4, April 1963.

3. Adding SCR's to Get High Power Means Smaller Transmitters, by G.

Brainerd, et al, ELECTRONICS. June 13, 1966.

4. Developing True Solid State Static Alternators, by R. Murphy, ELECTRO NICS, May 24, 1963.

5. Latest Developments in Static High Frequency Power Sources for Induction Heating, by B. R. Pelly in IEEE Transactions on Industrial Electronics and Control Instrumentation, Vol. IECI 17, Pages 297312, June 1970.

There will be described hereinafter embodiments of inverter systems of the present invention which are intended to provide high frequency power to an induction heating form of load, or more generally to a load exhibiting a series-resonant characteristic.

More broadly stated, in one aspect the invention provides an inverter system comprising a d.c. source, inductance means, a capacitor that is connected in an inverter circuit operable to provide an alternating polarity of charte on the capacitor, and a load that is external to the inverter circuit, the inverter circuit including switching means serving to connect the capacitor to the source to receive charging current via the inductance means and to couple the load to the capacitor via a circuit point intermediate the capacitor and the inductance means connected thereto such that the load is influenced by the voltage across the capacitor as it charges and so as to develop across the load an alternating voltage in response to the operation of the inverter circuit.

The inverter circuit preferably comprises switching means in the form of controlled rectifiers. These may be thyratrons or other valves but are preferably semiconductor controlled rectifiers (SCRs). To provide a longer recovery time for the controlled rectifiers following a period of conduction of any given device and/or a higher output frequency for a given recovery time, the inverter circuit may be one of a plurality of such circuits that are sequentially operated in a cyclic fashion.

In a second aspect of the invention there is provided an inverter system comprising a d.c. source, inductance means, a plurality of capacitors that are connected in respective inverter circuits that are connected in parallel and each of which is operable to provide an alternating polarity of charge on the associated capacitor, and a load that is external to the inverter circuits, each inverter circuit including switching means serving to connected the associated capacitor to the source to receive current via the inductance means and to couple the load to the associated capacitor via a circuit point intermediate the capacitor and the inductance means connected thereto such that the load is influenced by the voltage across the capacitor as it charges and so as to develop across the load alternating voltage in response to operation of the inverter circuit; and means connected to control the operation of the inverter circuits such that they operate according to a cyclic sequence that provides successive contributions to a continued alternating voltage developed across the load.

The invention and its practice will now be further described with reference to the accompanying drawings, in which: Figure 1 is a circuit diagram of one embodiment of the invention in which a load exhibiting a series resonant characteristic is energised from a d.c. source with the aid of a capacitor connected in a bridge inverter circuit.

Figure IA is another load configuration suitable for use with the circuit of Figure 1; Figures 2A, 2B, 2C, 2D and 2E are selected waveforms pertaining to the operation of the circuit of Figure 1; Figure 3 is a circuit diagram of a second embodiment of the invention illustrating the use of two, parallel connected, bridge inverter circuits with associated capacitors; Figures 4A, 4B and 4C are selected waveforms indicative of the operation of the circuit of Figure 3; Figures 5, 6 and 7 are circuit diagrams of other embodiments of the invention; Figure 8 is a waveform diagram pertaining to the operation of the circuit of Figure 7; andFigure 9 is a circuit diagram of a further embodiment of the present invention.

Before considering the circuit of Figure 1 in detail, attention will be given initially to the waveforms involved and the way they interact with the load. Referring to Figure 2B, this figure shows a typical waveform that is rich in fundamental even and odd harmonics of a frequency fO. For instance the approximate rms component of the fundamental frequency is .45E where E is the peak voltage applied to the load. The approximate rms component of the second harmonic (2fro) is one-half (.225E) of the value of the fundamental frequency. The third harmonic (3fro) is approximately onethird (.15E) of the fundamental frequency and thus the greater harmonics are included in proportionate value.

If the waveform of Figure 2B is applied across a high Q series tuned LC load circuit tuned to a frequency equal to the frequency fO, then the voltage across the series tuned load and the current through the load appear as shown in Figure 2B. However if the voltage waveform of Figure 2B is applied across a high Q series tuned LC circuit which is tuned to twice the fundamental frequency (2fro) of the voltage, then the current and voltage waveforms of the tuned circuit load will appear as shown in Figure 2C. With this understanding of the waveforms a description of the first embodiment of the invention follows.

Shown in Figure 1 is a circuit 10 capable of generating the waveforms shown in Figures 2B and 2C. In this circuit a variable dc course 12 supplies the power and is connected to one terminal of an inductor 11.

Connected to the other end of the inductor for receiving power therethrough, is an induction heating load exhibiting a series resonant characteristic and represented by its equivalent series tuned circuit comprising a capacitor 13, an inductor 14 and a resistance 15. The other end of the load is connected to the negative terminal of the dc source through ground. While a series tuned load is shown in this example other types of loads will function equally well with the subject circuit. For instance in Figure 1A is shown a series-parallel type tuned load which might be representative of another type of induction heating load.

For regulating the frequency of the voltage supplied to the load there is connected in parallel with the load a low impedance switching circuit including a capacitor 20 in combination with two sets of seriesconnected SCRs or switching devices 16, 17, 19 and 19 that form a bridge inverter circuit having its supply terminals connected across the load and operable to provide an alternating polarity of charge on the capacitor.

The SCRs are shown by way of example, however such switching devices could also be other types such as thyratron tubes, mercury-arc tubes and the like. The first set of series-connected SCRs are labeled SCR 16 and SCR 17 while the second set is labeled SCR 18 and SCR 19. Connected between the mid-points of the two sets of series-connected SCRs is the capacitor 20.

As the circuit of Figure 1 is switched, there will be generated the waveforms shown in Figure 2B if the load is tuned to the basic frequency fO. As will become more apparent below. because the SCRs are switched in pairs performing two switching operations on the capacitor for each complete cycle of inverted operation the bridge inverter generates two cycles of the waveform of Figure 2B at the frequencys fO, for each cycle operation of the inverter bridge.

The output voltage is at low impedance and rich in harmonics. Further the frequency of the voltage is independent of the resonent frequency of the load as illustrated by one cycle of operation of this circuit, which cycle is as follows. For purposes of the description of the operation, the following assumptions are made which are not necessarily required but which simplify the explanation. Firstly the current in the inductor 11 is maintained at a constant value by controlling the variable dc source 12. In addition the capacitance of the capacitor 20 is sufficiently large so that the voltage excursion across it during any one cycle of operation of the circuit is small. As a result, the current in the load will be small in comparison to the current in the inductor 11.

With the preceding assumptions the waveforms shown in Figures 2A, 2B and 2D represent the actual waveforms of the circuit of Figure 1. In other words the current in the capacitor during any one period (at fO) will be a square wave of a magnitude I (Figure 2D) with a small sinusoidal current superimposed or summed with it. On the next cycle the current waveform in the capacitor 20 will be in the same form except opposite in polarity.

Thus a full cycle of operation of the circuit 10 generates two full cycles of output voltage. The first cycle of the output voltage is generated when the SCRs 16 and 19 are caused to conduct simultaneously. As a result the terminal p (Figure 1), the output voltage across the load, will be negative since the capacitor 20 will be charged with the polarities as shown in Figure 1. The capacitor 20 will charge in a positive direction for generating a voltage waveform similar to that shown during the time T1 to T2 in Figure 2B. At the occurrence of the time T2, the SCRs 17 and 19 are caused to conduct.

Illustrated in Figure 2A is the voltage waveform across the SCR 16 occurring during the various cycles of operation of the circuit. Thus during the time T1 to T2, the voltage is shown as being near zero volts while the SCR 16 is actually conducting. At the time T2 when the SCRs 17 and 18 are caused to conduct the voltage on the capacitor 20 will be applied across the SCR 16 as shown between the times T2 and T3. It should be noted that the time the reverse voltage is impressed across the SCR 16 is equal to one-half the period of the generated frequency. Thus for operation of the circuit at a 10 KHz rate the reverse voltage for the SCR 16 is in the order of 50 microseconds. This time period is quite long for the operation of a standard high frequency inverter and if the load is tuned to the frequencys generated, i.e. fO, then the load power factor is 1 with a turnoff time of 50 microseconds at a 10 KHz rate. Of course the waveforms across the other SCRs are similar to the waveform across the SCR 16 but at different time intervals.

During the period of time (half cycle of the bridge inverter) that the SCRs 17 and 18 are in the conducting mode another complete cycle of output voltage is generated.

Stated otherwise, with the firing of each pair of SCRs, i.e. SCRs 16 and 19 or SCRs 17 and 18, connects the capacitor for charging by the source via the inductor and connects the capacitor to the load at the circuit point P intermediate the capacitor and the inductor 11 so that the load is influenced by the voltage across the capacitors as it changes and so that, in this embodiment, there is generated a complete cycle of output voltage. Thus the SCRs are fired in sets of two with the SCRs 17 and 18 and the SCRs 16 and 19 being placed in the conducting mode at alternate times.

To explain the current flow, during the time period T1 to T2 when the SCRs 16 and 19 are caused to conduct, there are actually two sources which supply current which flows through the SCRs 16 and 19 and the capacitor 20. During the first half of the period T1 to T2, i.e. until T1A [Figure 2D (assuming that the load is tuned to the fundamental frequency f0 generated by the inverter)] the current in the SCRs 16 and 19 and the capacitor 20 is greater than the current in the inductor 11. Thus the first current path starts at ground and passes through the dc source 12, the inductor 11, the SCR 16, the capacitor 20, the SCR 19 and back to ground. The second current is also initiated at ground to thereafter pass through the load resistor 15, the inductor 14, the capacitor 13, the SCR 16, the capacitor 20 and the SCR 19 back to the ground connection. If the inductor 11 is large, then the currents through the first path including the inductor 11 will be at substantially a constant magnitude (I). The second current path will be sinusoidal in nature assuming a series resonant load of some reasonable Q value. Thus during the first period T1 to T1A the current will be additive with the current in the inductor 11 and during the second time period TIA to T2 the sinusoidal current will subtract from the current passing through the inductor 11.

With the conditions set forth for the preceding description of the circuit of Figure 1 the current in the capacutor 20 will appear as shown in Figure 2D (1). As illustrated the current I is the magnitude of current in the inductor 11 and the magnitude X represents the peak-to-peak current in the series tuned load. Thus for any one complete cycle of operation of the circuit, i.e. of the bridge inverter. two complete cycles of the output voltage are generated. The output impe dance is relatively low in value and the output frequency can be varied essentially independently of the load value by altering the firing rate of the switching SCRs.

Under the conditions set forth, there will be little power delivered to the load. This results because the current in the inductor 11 was held constant by regulation of the dc source 12 and the capacitance of the capacitor 20 was sufficiently large to limit to a small value the voltage excursion across the capacitor during any one-half cycle of operation for the circuit. One method of increasing the power delivered to the load in circuit involves decreasing the size of the capacitor 20 while maintaining the current level substantially constant in the inductor 11. Thus with the smaller capacitance in the switching circuit, the voltage excursion across the capacitor 20 will be larger, i.e. the voltage E in Figure 2B will be at a greater magnitude.

As a result a larger current will flow in the load assuming the inductor current is maintained at a constant value. As a result the current flowing in the capacitor 20 will appear similar to that shown in Figure 2D (2) wherein the magnitude X will increase and the magnitude Y will decrease. Thus as the capacitive value of the capacitor 20 is decreased the peak-to-peak value of X of the load current will increase and the power to the load will increase as a result. As the peak value of the load increases, the minimum value Y of the current in the capacitor 20 will likewise decrease. For the area of operation during which the minimum value of current approaches but does not pass through zero, this mode of operation is referred to as "continuous current". As the current through the capacitor 20 increases, the output waveform and the SCR waveform will begin to distort. This distortion is due to the fact that as the capacitor 20 is decreased in size thereby resulting in more power being delivered to the load. the dc source 12 must be increased in value to maintain the current in the inductor 11 at a constant value. However since the terminal P is on the opposite side of the inductor 11 from the dc source there must be present a dc offset voltage effectively equal to the dc source 12. This offset voltage is shown in Figure 2E (1) for a value near the full continuous current, i.e. the maximum value for the peak-to-peak current X. The waveform shown is typical of both the output waveform for any one cycle of operation.

i.e. the time period from T1 to T2 and the voltage waveform across the SCR 16 during the period that this switching device is in the nonconducting mode. The offset voltage is shown to have a value 0' volts in Figure 2E (1) however the shape of the waveform will vary depending upon how close the system is operating to full continuous current and also the resonant frequency of the load if an induction heating load is utilized. However the same general form for the voltage will be that shown in Figure 2E.

Another mode of operating the circuit is called the discontinuous full-current mode shown in Figure 2D (3). For this condition the capacitor 20 is reduced in capacitive value sufficiently that a portion of each cycle of the load current is equal to the current in the inductor 11. The typical load volrage waveform for discontinuous full current for both the output voltage and the SCR voltage during the nonconductive period is shown in Figure 2E (2). Note further that as shown in Figure 2D (3) the value for Y is negative. There will result similar waveform changes in Figures 2C as the value of the capacitor 20 is decreased when the load is tuned to the second harmonic of the generated voltages.

In actual operation the capacitor 20 is usually maintained at a fixed capacitive value and the voltage of the dc source 12 is varied to control the level of power supplied to the load. Under some conditions the output frequency can also be varied to regulate the power delivered to the load.

Also while the means for turning on or firing the switching devices or silicon controlled rectifiers is not shown, such circuits are well-known and commonly used in the industry.

Shown in Figure 3 is a second embodiment of the invention illustrated as circuit 10A. This circuit is a modification of that shown in Figure 1 and includes a similar inductor 11A. a dc power source 12A with a load having a series resonant characteristic represented by a capacitor 13A, an inductor 14A and a resistor 15A. As before, the assumption is made that the current in the inductor 11A is maintained constant by regulation of the dc source 12A.

In this circuit there is included a pair of switched low impedance circuits S1 and S2 connected in parallel across the load. The switching circuit S1 includes the bridge inverter circuit comprising the SCRs 16A, 17A, 18A and 19A with the capacitor 20A connected to the common junction between the SCRs 16A and 17a and the SCRs 18a and 19A. Similarly the switching circuit S2 comprises the SCRs 21, 22, 23 and 24 connected in bridge inverter configuration with the capacitor 25 connected between the respective common junction terminals of the two pairs of series-connected SCRs.

Each inverter circuit and its associated capacitor is connected in the same manner with respect to the load and the induction 1 1A as the inverter circuit of Figure 1.

The operation of this circuit is similar to that of Figure 1 except the firing order for the pairs of SCRs of the bridges is consecu tive. With each firing of the seriesconnected SCRs a full output voltage cycle is generated. A typical firing order for the S Rs is for the SCRs 16A and 19A to be fired concurrently, followed by SCRs 21 and 24, SCRs 17A and 18A, SCRs 22 and 23, and once again a repeat of the firing of SCRs 16A and 19A and so on in a cyclic sequence, each successive pair of SCRs fired successively contributing to the continued alternating voltage developed across the load. Thus in the described cycle the frequency of the combined waveform generated by the inverters is the individual inverter operating frequency multiplied by two (for bridge inverters) multiplied by the number of inverters. The two halves of each inverter cycle are spaced in time in the recited sequence.

With the use of two bridge circuits as low impedance switches the pairs of SCRs are caused to conduct at one-half the frequency of the SCRs of the Figure 1 circuit for the satne generated frequency. In addition the turnoff time for the SCRs in this embodiment is three times that of Figure 1s for the same generated frequency.

The addition of the second bridge does not change substantially the output waveform. That is with each firing of a pair of SCRs of each bridge a full cycle of output voltages is generated with the circuit being capable of generating a frequency three times that of the first embodiment with the same turnoff time for the SCRs under similar loading conditions. Under practical conditions the two-bridge approach can generate as much as four to five times the frequency of the figure 1 circuit.

To explain one cycle of operation of the circuit 10A the capacitors are initially charged as shown. When the SCRs 16A and 19A are caused to conduct, the current paths are through these SCRs and the capacitor 20A from the dc source 12A and the inductor 11A. Similarly there is a current path through the load, the SCR 16A, the capacitor 20A and the SCR 19A back to ground. As in the previous embodiment the second current is substantially sinusoidal in nature assuming a series resonant load of some reasonable Q value and the load is turned to the waveform frequencys generated by the two inverters. When the voltage across the capacitor 20A has reversed and charged to a voltage equal in magnitude but opposite in polarity to the initial voltage, the SCRs 21 and 24 are caused to conduct. Thus another full cycle of output voltage is generated. The current paths are the same as for the previous firing except the current goes through these SCRs and the associated capacitor. Following this time period, the SCRs 17A and 18A are caused to conduct, followed in the next period by SCRs 22 and 23 and finally by a repeat of the firing of the SCRs 16A and 19A.

The output voltage waveform during two plus cycles of operation of the circuit 10A is shown in Figure 4C. The SCRs that are conducting for each of the four output cycles are indicated beside the waveform. The voltage across a representative SCR 16A for a two-bridge circuit is shown in Figure 4A.

Note that the recovery time for any SCR in this circuit comprising two bridges is one and one-half time periods in comparison to the circuit of Figure 1.

With the addition of a third bridge and maintaining of the output frequency constant the voltage waveform across a representative SCR 16 would be similar to the solid line waveform shown in Figure 4B.

The output voltage waveform is the same as for two bridges in the circuit, i.e. the waveform shown in Figure 4C. The circuit itself would appear as the circuit shown in Figure 3 except with the addition of a third low impedance switching circuit S3 similar to the switching circuits S1 and S2. The firing times would be alternated as for the two-bridge circuit with the additional seriesconnected SCRs being fired at the appropriate times.

A representative voltage across the SCR 16A for a three bridge approach corresponding to the voltage curves previously described for the SCR 16 of the previous embodiments appears in Figure 4B. As can be seen the turnoff time for the SCR or any of the other SCRs is approximately two and one-half time periods. If more turnoff time is required as for lower valued SCRs or if a higher output frequency is required, then additional bridges can be added to extend the frequency of the basic systems. In addition the load (if an induction heating circuit is the load) can be tuned to a harmonic of the fundamental generated frequency to further extend the range of the basic system. As can be seen an increase in the number of low impedance switching circuits can result in the generation of a very high frequency output. Keep in mind that the basic description of the two and threebridge switching system was based on the assumption that the peak-to-peak current in the load is small compared to the constant current in the inductor 11. As explained before. such a condition can be accomplished by maintaining the capacitance of the capacitors 20A and 25 at a very large value.

The current waveforms in multi-bridge systems just described appear similar to that of Figure 2B (1). However the waveforms will distort as the load increases to full current as indicated by the dotted lines superimposed on the waveforms of Figure 4B. In fact these waveforms may also be distorted somewhat based on whether or not the induction heating load is resonant at the generated frequency. Shown in Figure 4B in dotted lines is a typical distorted waveform during the first three periods after the firing of the SCR 16A. This waveform indicates a three-bridge circuit and it should be noted that the turnoff time for all the SCRs is still maintained for a time in excess of two periods. The distorted waveforms for the output voltage would again appear similar to that shown in Figure 2E (1) and Figure 2E (2), However the advantage of the subsequent embodiments described is the higher frequencies generated in the same basic circuit.

From the foregoing it should be noted that there are two aspects of the described inverter system which are. The first involves the connection of the load dynamically in parallel with the bridge switching circuit which may be contrasted with the possibilities of connecting the load in series with a bridge switching circuit or in parallel with the bridge capacitor within the bridge itself.

A in the described systems energising a series tuned load, there is required only one firing of the bridge to complete at least one output voltage cycle on the load, i.e. an output cycle is completed for each ocassion that the capacitor, or one of the capacitors if more than one inverter circuit is employed, is switched to be charged from the d.c.

source through the inductor.

The second aspect concerns the capability of connecting several bridge switching circuits in parallel with one another and each dynamically in parallel with the load. In this manner the frequency of operation and/or the turnoff time for the switching devices can be extended greatly with little added expense.

Referring now to Figure 5, there is shown another modification of a circuit identified as circuit 10B. Similarly to Figure 1. there is provided a similar dc source 12B. an inductor 11B and a switching circuit similar to those previously utilized which in this case is identified as S1B. The low impedance switching circuit incorporates the SCRs 16B, 17B, 18B and 19B connected in bridge inverter configuration with the capacitor 20B connected at the common terminals between the pairs of SCRs. Thus to this point the circuit 10B is identical to the figure 1 circuit previously described.

The difference between this circuit and embodiments previously described is the connecting point for the resistor 15B. The load is identified by a capacitor 13B, an inductor 14B and a resistor 15B as in the previous embodiments. however the load is connected in parallel with the inductor 11B.

Thus the load is still connected to the circuit point intermediate the inductor and the inverter and dynamically in parallel with the switching circuit because the dc source 12B is considered an ac short circuit from the standpoint of operation. The currents in the SCRs, the capacitor 20 and the inductor 11 for a tuned load are the same as described for the circuit of Figure 1.

The basic operating difference between this circuit and that previously described is that there is no dc offset voltage across the series tuned induction heating load. This assumption is based upon the premise that the IR drop across the inductor 11B is substantially zero.

A further modification of the present invention is illustrated in Figure 6 in the circuit 10C. Herein the similar components are illustrated as the dc source 12C, the inductor 11C and the switching device S1C comprising the SCRs 16C, 17C, 18C and 19C in bridge configuration with a capacitor 20C connected thereacross. In addition the load is identified as a capacitor 13C, an inductor 14C and a resistor 15C.

The operation of this circuit is similar to that of Figure 5 with the exception that a transformer 26 is interposed between the load and the connections across the inductor 11C. The transformer 26 comprises a primary winding 27 and a secondary winding 28 with the by the capacitor 13D, the inductor 14D and the resistor 15D. In this embodiment the output voltage waveform is the same as that for previous circuits and the waveforms across the SCRs are, while still in the same general form as that of Figure 1, somewhat altered. Shown in Figure 8 is a waveform for this circuit showing the voltage across one of the switching devices in each of two, parallel connected, inverter circuits containing respective capacitors 33 and 34.

The switching circuit SI D comprises a first SCR 29 connected in series with two circuits to form a parallel connection across the load. The first circuit includes an SCR 30 and an inductor 36 while the second circuit incorporates the capacitor 33.

In parallel with this first switching circuit is a second switching circuit of similar character utilizing an SCR 31 in series connection with a parallel combination of an SCR 32 in series with an inductor 35. and a capacitor 34. The waveform of Figure 8 shows the voltage across either the SCR 29 or the SCR 31 under lightly loaded conditions.

Assuming the voltage shown in Figure 8 is that of SCR 9 the following operating conditions are present. From the time T1 to "1,2the SCR '9 is turned on. At the time T2 the SCR 31 is fired. Following the firing of the SCR 31. at time T3 the SCR 30 is fired to cause the resonant reversal of the charge polarity on the capacitor 33. At the time TIA the SCR 29 is caused to conduct again to repeat the cycle.

The current through the capacitor 33 when the SCR 29 is conducting, is the same form as the current through the capacitor 20 of Figure 1. In this embodiment the turning on of SCR 29 or 31 enables charging of the capacitor 33 or 34 respectively through inductor 11D while coupling the capacitor to the load. There is only one cycle of the generated frequency for each cycle of operation of an inverter. One advantage of this circuit is the fact that the two SCRs are not commutated in series as in the circuit 10 with the attendant disadvantages. It must be recognized however, that under the same load conditions the voltages of the circuits 1OD on the SCRs is approximately twice that of the SCRs of Figure 1.

Shown in Figure 9 is still another embodiment of the present invention which can be referred to as a balanced one-half bridge inverter circuit. Once again the circuit utilizes a dc voltage source 12E and the load identified as a capacitor 13E, an inductor 14E and a resistor 15E. In parallel connection across the load is the switching device S1E comprising an SCR 40 and an SCR 41 in series connection. However instead of an additional pair of SCRs there is utilized a pair of capacitors 42 and 43 in series connection directly across source 12E. Once again connected in the bridge is a third capacitor 44 connected between the common terminal between the canllcitors and that between the SCRs of thc switching circuit.

The inductor while still being couple is split into two parts with one-hall being connected between the negative terminal of the de source 12E and one end of the series connection of the SCRs, and the other half being connected between the positive terminal of the de course and the other end of this series SCR connection. The polarities of the coupled inductor parts are in indicated by the dots.

The primary advantage of this circuit is that only two SCRs are needed for the basic switching function, however each SCR must carry twice the current of the SCRs utilized in Figure 1. This condition is assuming that the same load is impressed on the circuit.

However by sequentially firing the SCRs substantially the same waveforms are obtained with the exception that the current passes through the capacitors instead of another pair of SCRs in the switching circuit SIE. The generated frequency f0 is twice the frequency of operation of the half-bridge inverter.

It can be seen that in each of the embodiments the circuits are shown by way of example and the frequency or the turnoff times for the switching devices can be extended by adding additional switching circuits or low impedance bridge circuits to the basic circuit illustrated. However in each instance the load is connected dynamically in parallel with the switching device serving as a low impedance switching circuit. In addition, the frequency of the generated voltage can be controlled independently of the load and consequently, the Q of the load can be any value. In addition, when energising a load exhibiting a series resonant characteristic, each firing of the SCRs to charge the associated capacitor from the source enables a full cycle of output voltage to be generated on the load, that is a full negative and positive voltage - not just a negative or positive voltage for each such firing. furthermore, the load may be tuned not only to the generated frequency to produce a full output cycle per cycle of the generated frequency but because the generated waveform is rich in harmonics, the load can be tuned to a harmonic, particularly the second.

WHAT I CLAIM IS: 1. An inverter system comprising a d.c.

source, inductance means, a capacitor that is connected in an inverter circuit operable to provide an alternating polarity of charge on the capacitor, and a load that is external to the inverter circuit, the inverter circuit

**WARNING** end of DESC field may overlap start of CLMS **.

Claims (35)

**WARNING** start of CLMS field may overlap end of DESC **. by the capacitor 13D, the inductor 14D and the resistor 15D. In this embodiment the output voltage waveform is the same as that for previous circuits and the waveforms across the SCRs are, while still in the same general form as that of Figure 1, somewhat altered. Shown in Figure 8 is a waveform for this circuit showing the voltage across one of the switching devices in each of two, parallel connected, inverter circuits containing respective capacitors 33 and 34. The switching circuit SI D comprises a first SCR 29 connected in series with two circuits to form a parallel connection across the load. The first circuit includes an SCR 30 and an inductor 36 while the second circuit incorporates the capacitor 33. In parallel with this first switching circuit is a second switching circuit of similar character utilizing an SCR 31 in series connection with a parallel combination of an SCR 32 in series with an inductor 35. and a capacitor 34. The waveform of Figure 8 shows the voltage across either the SCR 29 or the SCR 31 under lightly loaded conditions. Assuming the voltage shown in Figure 8 is that of SCR 9 the following operating conditions are present. From the time T1 to "1,2the SCR '9 is turned on. At the time T2 the SCR 31 is fired. Following the firing of the SCR 31. at time T3 the SCR 30 is fired to cause the resonant reversal of the charge polarity on the capacitor 33. At the time TIA the SCR 29 is caused to conduct again to repeat the cycle. The current through the capacitor 33 when the SCR 29 is conducting, is the same form as the current through the capacitor 20 of Figure 1. In this embodiment the turning on of SCR 29 or 31 enables charging of the capacitor 33 or 34 respectively through inductor 11D while coupling the capacitor to the load. There is only one cycle of the generated frequency for each cycle of operation of an inverter. One advantage of this circuit is the fact that the two SCRs are not commutated in series as in the circuit 10 with the attendant disadvantages. It must be recognized however, that under the same load conditions the voltages of the circuits 1OD on the SCRs is approximately twice that of the SCRs of Figure 1. Shown in Figure 9 is still another embodiment of the present invention which can be referred to as a balanced one-half bridge inverter circuit. Once again the circuit utilizes a dc voltage source 12E and the load identified as a capacitor 13E, an inductor 14E and a resistor 15E. In parallel connection across the load is the switching device S1E comprising an SCR 40 and an SCR 41 in series connection. However instead of an additional pair of SCRs there is utilized a pair of capacitors 42 and 43 in series connection directly across source 12E. Once again connected in the bridge is a third capacitor 44 connected between the common terminal between the canllcitors and that between the SCRs of thc switching circuit. The inductor while still being couple is split into two parts with one-hall being connected between the negative terminal of the de source 12E and one end of the series connection of the SCRs, and the other half being connected between the positive terminal of the de course and the other end of this series SCR connection. The polarities of the coupled inductor parts are in indicated by the dots. The primary advantage of this circuit is that only two SCRs are needed for the basic switching function, however each SCR must carry twice the current of the SCRs utilized in Figure 1. This condition is assuming that the same load is impressed on the circuit. However by sequentially firing the SCRs substantially the same waveforms are obtained with the exception that the current passes through the capacitors instead of another pair of SCRs in the switching circuit SIE. The generated frequency f0 is twice the frequency of operation of the half-bridge inverter. It can be seen that in each of the embodiments the circuits are shown by way of example and the frequency or the turnoff times for the switching devices can be extended by adding additional switching circuits or low impedance bridge circuits to the basic circuit illustrated. However in each instance the load is connected dynamically in parallel with the switching device serving as a low impedance switching circuit. In addition, the frequency of the generated voltage can be controlled independently of the load and consequently, the Q of the load can be any value. In addition, when energising a load exhibiting a series resonant characteristic, each firing of the SCRs to charge the associated capacitor from the source enables a full cycle of output voltage to be generated on the load, that is a full negative and positive voltage - not just a negative or positive voltage for each such firing. furthermore, the load may be tuned not only to the generated frequency to produce a full output cycle per cycle of the generated frequency but because the generated waveform is rich in harmonics, the load can be tuned to a harmonic, particularly the second. WHAT I CLAIM IS:

1. An inverter system comprising a d.c.

source, inductance means, a capacitor that is connected in an inverter circuit operable to provide an alternating polarity of charge on the capacitor, and a load that is external to the inverter circuit, the inverter circuit

including switching means serving to connect the capacitor to the source to receive charging current via the inductance means and to couple the load to the capacitor via a circuit point intermediate the capacitor and the inductance means connected thereto such that the load is influenced by the voltage across the capacitor as it charges and so as to develop across the load an alternating voltage in response to the operation of the inverter circuit.

2. An inverter system as claimed in Claim 1 in which said inverter circuit is a bridge circuit operable to periodically reverse the connection of the capacitor with respect to the source and the load.

3. An inverter system as claimed in Claim 1 in which said inverter circuit is a half-bridge circuit in which said capacitor is connected between thejunction of a pair of serially-connected capacitors and the junction of a pair of serially-connected switching devices, the series connection of the capacitors being connected directly across the pole of said source and said switching devices being connected, with like polarity, in series with the source and the inductance means

4. An inverter system as claimed in Claim 1 in which said inverter circuit comprises a first switching device connected in series with said source, said inductance means and said capacitor to charge same with one polarity, and a second switching device connected in series with an inductor which series connection is in paralel with the capacitor to reverse said one polarity of charge on the capacitor by resonant discharge through said second switching device.

5. An inverter system as claimed in Claim 2 in which the load is connected across the supply terminals of said bridge inverter circuit.

6. An inverter system as claimed in claim 3 in which the load is connected across the series connection of said pair of switching devices.

7. An inverter system as claimed in Claim 4 in which the load is connected across the series connection of said first switching device and said capacitor.

8. An inverter system as claimed in Claim 1, 2 or 4 in which said inductance means comprises an inductor across which said load is connected.

9. An inverter system as claimed in Claim 1, 2 or 4 in which said inductance means comprises an inductor across which said load is connected through a coupling transformer.

10. An inverter system as claimed in Claim 1, 2 or 4 in which said inductance means comprises a first winding of a trans former to a second winding of which the load is connected.

11. An inverter system as claimed in Claim 3 in which said inductance means comprises two inductors, one connected between one pole of the source and one of said pair of switching devices and the other connected between the other pole of the source and the other of said pair of switching devices.

12. An inverter system as claimed in Claim 11 in which said switching devices are controlled rectifiers, and said two inductors are magnetically coupled such that the flow of current arising from the turning on of one switching device acts to impress a reverse bias voltage across the other.

13. An inverter system as claimed in any preceding claim in which said load comprises an induction heating arrangement.

14. An inverter system as claimed in any preceding claim in which the load exhibits a series resonant characteristic having a resonant frequency substantially at the frequency generated by the inverter circuit.

15. An inverter system as claimed in any one of Claims 1 to 14 in which the load exhibits a series resonant characteristic having a resonant frequency substantially at a harmonic of the frequency generated by the inverter circuit.

16. An inverter system as claimed in Claim 15 in which said harmonic is the second harmonic.

17. An inverter system comprising a d.c.

source, inductance means, a plurality of capacitors that are connected in respective inverter circuits that are connected in parallel and each of which is operable to provide an alternating polarity of charge on the associated capacitor, and a load that is external to the inverter circuits, each inverter circuit including switching means serving to connect the associated capacitor to the source to receive current via the inductance means and to couple the load to the associated capacitor via a circuit point intermediate the capacitor and the inductance means connected thereto such that the load is influenced by the voltage across the capacitor as it charges and so as to develop across the load alternating voltage in response to operation of the inverter circuit; and means connected to control the operation of the inverter circuits such that they operate according to a cyclic sequence that provides successive contributions to a continued alternating voltage developed across the load.

18. An inverter system as claimed in Claim 17 in which each inverter circuit is a bridge circuit operable to periodically reverse the connection of the associated capacitor with respect to the source and the load.

19. An inverter system as claimed in Claim 17 in which each inverter circuit is a half-bridge circuit comprising a pair of serially-connected switching devices to the junction between which one side of the associated capacitor is connected, the other side of the capacitor being connected to the junction between a pair of seriallyconnected capacitors, the series connection of the capacitors being connected directly across the poles of said source and said switching devices being connected, with like polarity, in series with the source and the mductance means.

20. An inverter system as claimed in Claim 17 in which each inverter circuit comprises a first switching device connected in series with said source, said inductance means and the associated capacitor to charge same with one polarity and a second switching device connected in series with an inductor which series connection is in parallel with the associated capacitor to reverse said one polarity of charge on the capacitor by resonant discharge through said second switching device.

21. An inverter system as claimed in Claim 18 in which the load is connected across the supply terminals of each bridge inverter circuit.

22. An inverter system as claimed in Claim 19 in which the load is connected across the series connection of each pair of switching devices of each inverter circuit.

23. An inverter system as claimed in Claim 20 in which the load is connected across the series connection of said first switching device and the associated capacitor of each inverter circuit.

24. An inverter system as claimed in Claim 17, 18 or 20 in which said inductance means comprises an inductor across which said load is connected.

25. An inverter system as claimed in Claim 17, 18 or 20 in which said inductance means comprises an inductor across which said load is connected through a coupling transformer.

26. An inverter system as claimed in Claim 17, 18 or 20 in which said inductance means comprises a first winding of a transformer to a second winding of which the load is connected.

27. An inverter system as claimed in Claim 19 in which said inductance means comprises two inductors, one connected between one pole of the source and one of said pair of switching devices of each inverter and the other connected between the other pole of the source and the other of said ppair of switching devices of each inverter.

28. An inverter system as claimed in Claim 27 in which said switching devices of the inverters are controlled rectifiers and said two inductors are magnetically coupled such that the flow of current arising from the turning on of one switching device of an inverter acts to impress a reverse bias voltage across the other.

29. An inverter system as claimed in any one of Claims 17 to 28 in which said load comprises an induction heating arrangement.

30. An inverter system as claimed in any one of Claims 17 to 29 in which the load exhibits a series resonant characteristic having a resonant frequency substantially at the frequency generated by the inverter circuits.

31. An inverter system as claimed in any one of Claims 17 to 30 in which the load exhibits a series resonant characteristic having a resonant frequency substantially at a harmonic of the frequency generated by the inverter circuits.

32. An inverter system as claimed in Claim 31 in which said harmonic is the second harmonic.

33. An inverter system as claimed in any preceding claim in which said source is operable to supply a substantially constant current.

34. An inverter system as claimed in any preceding claim, in which the or each inverter as the case may be, comprises switching means constituted by controlled rectifiers.

35. An inverter system substantially as hereinbefore described with reference to Figures 1 and 2 Figures 3 and 4; Figures 5 and 2; Figures 6 and 2: Figures 7 and 8; or Figure 9 of the accompanying drawings.