GB1563820A - Apparatus and method for providing toner images - Google Patents

Description

(54) APPARATUS AND METHOD FOR PROVIDING TONER IMAGES (71) WNe, XEROX CORPORATION of Rochester, New York State, United Skates of America, a Body Corporate organized under the laws of the State of New York, United States of America, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement :- This invention generally relates to apparatus and a method for providing toner images. More particularly, the present invention relates to such apparatus when adapted for regulating the time during which a fuser assembly is on in said apparatus.

Electrophotographic reproducing techniques of the type described in detail in U. S. Pat. No. 2, 297, 691, issued to Chester F. Carlson, form electrostatic latent images of original documents by selectively dissipating a uniform layer of electrostatic charges deposited on the surface of a photoreceptor in accordance with modulated radiation images focused thereon. An electrostatic latent image thus formed is developed and transferred to a support surface to form a final copy of an original document. The development process is effected by applying electroscopic particles, conventionally known as toner or toner particles, to the electrostatic latent image whereat such particles are electrostatically attracted to the latent image in proportion to the amount of charges constituting such image. Hence, the areas of small charge concentration are developed to form areas of low particle density, while areas of greater charge concentration are developed to form areas wherein the particle density is greater. Once transferred to the support surface, the developed image may be per manently fixed thereto by heat fusing g techniques wherein the individual transferred toner particles soften and coalesce when heated so as to adhere to the support surface.

Various modifications in fusing techniques have heretofore been developed which achieve diverse results, such techniques including e. g. selective fusing.

Selective fusing contemplates the irregular, non-continuous, non-periodic operation of a fuser assembly in response to particular predetermined conditions. In this regard, selective fusing techniques are readily adapted to cooperate with selective xero- graphic printing techniques. Thus, if copies of only selected ones of successively scanned original documents are to be printed, a fuser assembly must be energized for each time the developed image of a selected original is transferred to the support surface. It is appreciated that if the support surface comprises a web of suitable material, e. g. paper, the web will be transported to the fuser assembly in an irregular manner corresponding to the scanning of the unique originals to be reproduced. Con sequentlv, scorching or burning of the web that is stationarily disposed within the fuser assembly must be avoided, while, at the same time, sufficient heat must be accumu latecl in the assembly to assure adequate fusing of the toner areas to web.

In the implementation of the aforementioned fusing technique, i. e., the fusing of successive toner areas disposed in image configuration upon an irregularly moving support surface, it has been found, that in addition to the problem of scorching the support surface, it is necessary to provide for a delay in raising the temperature of the fuser assembly to a proper value in response to the energization thereof, for the accumulation of heat within the assembly during the duration of energization thereof, and for the temperature to which the assembly has cooled in the time that has expired since the immediately preceding energization thereof.

Prior attempts at regulating a fuser assembly of the type herein contemplated in order to account for the foregoing has resulted in regulation without due consideration to the actual temperature in the fuser assembly or, as is the case in the apparatus discloscd in U. S. Patent 3,851,144, have required variable power supplies constantly supplying either low or high levels of energy to a heating element.

According to a first aspect of the present invention, there is provided apparatus comprising: a source for generating light images and print signals associated with at least some of the images, any one of the print signals being associated with only one of the images ; a support base; means for providing toner images corresponding to said light images associated with print signals, on successive sections of the support base; a fuser assembly comprising at least one heater means to which said toner images will be presented; wherein in said apparatus there are: (a) means, responsive to said print signals, for turning on the fuser assembly heater means for a predetermined time period between successive said print signals, said predetermined time period occurring immediately prior to the presentation of a said toner image to the fuser assembly; (b) means for turning on the fuser assembly heater means upon said presentation of a toner image to the fuser assembly ; and (c) means responsive to the temperature in the fuser assembly so as to be able to inhibit means (a) and (b) and thereby turn off the fuser assembly heater means during said predetermined time period.

According to a second aspect of the present invention, there is provided a method for providing toner images, comprising using apparatus according to said first aspect of the present invention so as to provide said toner images.

In said apparatus of the present inven- tion, said source can be adapted to generate the light images at a predetermined frequency. Said apparatus can comprise means for periodically turning on the fuser assembiy heater means for a length of time to keep warm the fuser assembly heater means, said ength of time being dependent on the temperature in the fuser assembly. Said means for periodically turning on the fuser assembly heater means can comprise means for varying said length of time independentlv of the temperature in the fuser assembiy. Preferably, said heater means is electrical heater means.

Said heater means can be a radiant heer.

Preferably said heater means comprises at ! east one ribbon heating element.

Said means for providing toner images can comprise means responsive to the print signals so as to be able to advance the support base a predetermined amount after a said print signal occurs, and means for advancing sections of the support base at said predetermined frequency without regard to the presence or absence of said print signals.

Said means (a) can comprise an up-down counter adapted to count up the intervals of time occurring between successive saicl print signal and count down at a rate which is higher than the rate of said interval of time. Said counter can be adapted such that the count down rate of said counter will be independently variable.

Said means (c) can comprise means for sensing the temperature in the fuser assembly and for providing binary signals related to said sensed temperature, and means responsive to said binary signals so as to be able to inhibit said means (a) and (b).

The present invention will now be described by way of example with reference to the accompanying drawings wherein: Fig. 1 is a schematic diagram of one embodiment of apparatus in accordance with the present ; Fig. 2 is a partial schematic diagram of part of an electrical circuit, including means for driving a support base through a fuser assembly in the apparatus of Fi.

1, and means for keeping warm the fuser assembly ; Fig. 3 is a partial schematic diagram of another part of said electrical circuit including means for limiting the maximum fusing on time as a function of ambient temperature in said fuser assemblv ; and Fig. 4 is a partial schematic diagram of another part of said electrical circuit, including means for energizing the fuser assembly for the period of time related to intervals of time occurring between print signals associated with images to be printed.

Fig. 1 comprises apparatus wherein a light image of an original (i. e. a data card i ! to be reproduced is projected onto the sensitized photosensitive surface of a photosensitive drum 20 to form an e ! ectro- static latent image thereon. Thereafter, the ; latent image is developed with an oppositelv charged developing material compris ing elect ;-oscopic particles knot-n as toner particles, to form a powder image (i. e. de .-eloped electrostatic latent image) corresponding to the latent image on the photosensitive surface. The poder image is then electrostaticalls transferred to a support base 9 te which it may be fixed bn a fuse'' assembly 40 whereby the powder image is ca ! sed to adhere pe,-mallentlv to the su ?- port base 9.

In the illustrated apparatus, visible document information is provided on each of the data cards I that are succesively transported from a feeder try 2 to a restack tray 49. The data cards are irans- ported in timed sequence with respect to the operation of the remaining apparatus and are caused to traverse scanning station B and slit exposure device 34 in successive order. Each data card is addi tionally provided with pre-coded information thereon, which pre-coded information is determinative of the selective printing of the visible document information carriect by the carcl. More particularly, if the pre-coded information scanned from the card by scanning station B admits of a particular pre-condition, logic circuitry of print signal generator 5 responds to such scanned information to derive a print signel. The thus derived print signal is operated upon in timed sequence to provide a direct correspondence between the sequential manipulation of such print signal and the particular operation performed by the apparatus illustrated in Fig. 1.

The sequential passage of data cards from the scanning station B through the projection system 33 to the restack tray 49 will cause optical images of the visible document information on each of the data cards passing through the slit exposure device 34 to be sequentialy projected upon the surface of photosensitive drum 20. The photosensitive drum 20 is continuously driven at a constant angular velocity such that the surface thereof is moving at a velocity equal to that of data cards moving past the exposure device 34. In moving in the direction indicated by the arrow prior to reaching the exposure station C, that portion of the photosensitive drum being exposed is uniformly charged by a corona discharge station G. The exposure of the photosensitive drum surface to the light image selectively dissipates the electrostatic charge on the surface thereof in the area struck by light, thereby forming an electrostatic latent image in image configuration corresponding to the light image projected from the visible document information on the data card transported through the slit exposure device 34. As the photosensitive drum's surface continues its movement the electrostatic latent image passes through a developing station D in which there is positioned a developing apparatus generally indicated by the refer- ence numeral 35.

If the electrostatic latent image passing through development station D is drive from a data card having a print signal associated therewith, such print signal is utilized to activate the developer motor 24 such that the developing apparatus may be operated to develop this electrostatic latent image. In contradistinction thereto, should the electrostatic latent image passing through the developing station D be derived from a data card not having a print signal associated therewith, the developer motor 24 is not activated and this electro- static latent image is not developed. Therefore, it should be appreciated that the developing apparatus 35 is operated in an intermittent manner wherein only those electrostatic images derived from data cards having print signals associated therewith are developed at station D. As the photosensitive drum 20 continues to rotate in the direction indicated by the arrow successive areas thereof will be provided with image information distributed thereon in the form of a distributed electrostatic charge pattern. However, only selected ones of successive areas will be developed.

As illustrated in Fig. 1, the developing apparatus 35 is provided with electroscopic particles (i. e. toner particles) that are cascaded across the surface of photosensitive drum 20, which particles are attracted electrostatically to the distributed charge pattern to form powder images (i. e. developed electrostatic latent images).

The developed electrostatic latent image is transported by the photosensitive drum 20 to a transfer station E located at a point of tangency to the photosensitive drum whereat a support base 9 is intermittently moved at a speed in synchronism with the moving drum in order to accomplish transfer of the developed image. The support base 9 is depicted in Fig. 1 as a web comprised of suitable material, e. g. paper, driven from a supply bin 13 to selective transfer mechanism 25, through fuser assembly 40, about driving means 16 and into a receiving tray 14. It will be appreciated that the support base 9 may also comprise a continuous strip of paper having gummed labels supported thereon which can be readily removed from the web subsequent to the reproducing operation. At the time a developed image having a print signal associated therewith arrives at the transfer station E, the associated print signal is operated upon to cause the driving means 16 to be activated, thereby transporting the support base 9 at a velocity equal to the surface velocity of the photosensitive drum 20. Moreover, the print signal is used to operate the selective transfer mechanism 25 whereby the support base 9 engages the photosensitive drum 20 in an arc contact. In addition. charging means 30 may be energized to provide a charge on the support base 9 prior to its engagement with the photosensitive drum so that the developed image may be electrostatically transferred from the surface of drum 20 to the adjacent sicle of the support base as such support base is brought into contact therewith.

Thus, it is seen, that each developed ele trostatic latent image is transferred to the support base 9 ; and the support base is, therefore, advanced in an intermittent manner in accordance with each print signal that is derived from the scanning information carried bv the transported data cards.

After said transfer of the developed electrostatic latent image, the support base 9 is transported to the fuser assembly 40, wherein the transferred image on the support base is permanently fixed thereto.

Fuser assembly 40 contains one or more ribbon heating elements adapted to emit a suitable amount of heat when energized.

The dimensions of the fuser assembly may be such as to admit of a plurality of said transferred images to be disposed therein simultaneously. The print signal derived from a data card is operated upon in a preselected sequential manner in correspondance with the transporting of a transferred image to the fuser assembly 40. Because, however, immediately succeeding areas of the support base 9 are provided with transferred images, but succeeding ones of the data cards are not necessarily provided with the unique pre-coded scanning information, it is recognized that the support base is moved intermittently through the fuser assembly in an irregular manner. In general, the fuser assembly must not be continuously energized, thereby avoiding scorching of the support base that is maintained in a temporary stationary relationship with respect thereto. Nevertheless, as an immediately succeeding portion of the support base is advanced to the fuser assembly, the latter must be energized to an operating level capable of fixing the transferred image that is upon the support base. The manner in which the fuser assembly 40 is regulated to provide the just-mentioned selective fusing is described in detail hereinbelow.

The excess electroscopic particles remaining as residue on the electrostatic latent images, as well as those particles not otherwise transferred from the drum 20, are carried by the photosensitive drum 20 to a clean station F on the periphery of the drum adjacent the charging station G.

The cleaning station may comprise a rotating brush and a corona discharge device for neutralizing charges remaining on the non-transferred electroscopic particles.

Various other configurations and components may constitute a cleaning station F as is well known to those skilled in the art. A more complete description of the selective printing apparatus illustrated in Fig. 1, and the manner in which such apparatus operates, is set forth in detail in U. S. Patent 3,743,779, issued to Mark A Hutner on July 3, 1973 and assigned to Xerox Corporation, the assignee of the present invention.

Referring to Fig. 1, intermittent movement of the support base 9 in accordance with print signals, and continuous motion of the support base so as to remove printed sections ot the support base located within the apparatus at the end of a run, are accomplished with a single revolution clutch 15 coupled to the driving means 16.

In turn, clutch 15 is controlled with a logic circuit responsive to a system clock 50 (see Fig. 2) and generated command signals. More specifically, clock 50 provides on line 51 a positive pulse signal having a duration of 190 ms. and a period of 330 ms. As will become apparent the 330 ms. period is the interval of time required to translate successive sections of the support base to the fuser assembly and is the reciprocal of the data card feed rate. With respect to command signals, a start responsive signal generator 52 provides a command signal on line 53 such that whenever the apparatus is started a binary"1" is provided for approximately 100 ms; a feed responsive signal generator 54 provides a command signal on line 55 such that a binary"I"exists thereon except when a feed button for support base 9 (the button is part of the apparatus) is depressed; and a print data signal generator 56 provides a command signal which is synchronized with print signals to provide on line 57 binary"0"s three clock cycles after print selections and binary"I"s during other periods. In the logic circuit, line 53 is connected to an input of NAND gate 58; line 57 is connected to an input of a NAN gate 59; and line 55 is connected to a Schmitt trigger 60 which squares and inverts, the output of the trigger 60 being connected via line 61 to the input of an inverter 62. The output of inverter 62 is connected via line 63 to inputs of NAND gates 58 and 59. The output of NAND gate 58 is connected via line 64 to the preset and clear inputs, respectively, of a flip-flop 65 and shift register 66, the Q output of flip-flop 65 being connected by line 57 to serial inputs of the shift register, and the output of NAND gate 59 is connected by line 68 to the D input of flip-flop 65. Line 51 is connected to a Schmitt trigger 69, which squares and inverts, and the output of trigger 69 is connected via line 70 to inverters 71 and 102. The output signal of inverter 71 is connected by line 72 to the clock inputs of flip-flop 65 and shift register 66. Thus, it may be seen that when the apparatus is turned on the binary "0"generated on line 64 by the temporary binary"I"on line 53 and the binary"1" on line 55 presets the Q output of flip-flop 65 and causes all the outputs of shift register 66 to go low. In addition, when the apparatus is started, the system clock 50 is activated and as a result the Q output of flip-flop 65, i. e., a binary"1", is propagated through the shirt register 66. With binary"I"s present on lines 63 and 57 binary"0"s are propagated through the shift register 66. However, whenever a binary"0"appears on line 57, corresponding to a print signal, or when the feed button for support base 9 is depressed, a binary"I"is propagated in the shift regi, ster 66. If the feed button is held in a depressed condition a series of binary"1"s is propagated down the shift register 66.

The last stage QH of shift register 66 is connected by a line 73 to an input of a NAND gate 74 and an input of a NAND gate 75. Furthermore, the next to the last stage Qn of the shift register 66 is connected by line 153 to NAND gate 75. The output of NAND gate 74 is coupled by a low-pass RC network to an input of AND gate 76 and the output of NAND gate 75 is coupled by another RC network to another input of AND gate 76. The output of AND gate 76 controls the single revolution clutch 15. Operatively, when a binary "I"is at Q} and a binary"0"is at Q, a binary"I"which appears periodically for 190 ms. on line 72 causes the output of AND gate 76 to go low for 190 ms. to activate the clutch 15. More specifically, the low 190 ms. signal on line 72 activates within the clutch a solenoid which releases a powered shaft for a complete revolution.

The shaft is coupled to the support base driving means and, accordingly, the driving means advances a section of the support base 9. If a binary"I"is also present on Q, ;, the output of the AND gate 76 remains low during the remaining period of the clock signal. When a shift occurs in the shift register 66, the binary"1"in Q,, shifts to On and the binary low on AND gate 76 remains for at least another 190 ms., depending on the new state of Q, ; It will be appreciated by those skilled in the art that when a steady stream of binary "I"s are being supplied by the shift register 66 the output of NAND gate 75 provides a binary"0"level which causes the output of AND gate 76 to provide a binary"0" level, and the clutch 15 remains energized.

Thus, chatter which would occur if the clutch 15 were activated on every system cycle is eliminated. When the apparatus is started the binary"I"propagated through the shift register will shift an unprinted section of the support base 9 through the apparatus. This segm nt may bc used to identify machine runs. In view of the foregoing it should now be appreciated by persons skilled in the subject art that each print signal will cause a shift in the support base 9 and that activation of the feed button for the support base will advance a section of the support base or multiples of the section through the apparatus at the clock rate. The latter is particularly useful at the end of a run when it is desired to move the last printed section out of the apparatus.

Fuser assembly 40 is supplied with electrical power on a cycle by cycle basis, the amount of time during each cycle (=330 ms.) that the fuser assembly is on being controlled by logic circuitry responsive to the temperature in the fusing chamber and the evolving print signal pattern. More specifically, the logic circuitry controls the maximum possible on time of the fuser assembly for any cycle of the apparatus; one time of the fuser assembly during nonfusing cycles; on time of the fuser assembly during fusing cycles; and the on time for a fuser assembly for a cycle prior to a fusing cycle.

In the apparatus shown, the maximum possible on time for the fuser assembly is limited to fixed times, i. e., 330 ms., 280 ms., 230 ms., or 190 ms., corresponding to, respectively, temperatures in the fuser assembly below 75 C, below 95 C, below 115 C, or above 115 C. In general, this is accomplished by providing an electrical voltage related to the temperature in the fuser assembly, by comparing the electrical voltage with reference voltages to provide binary command signals and by using the command signals to drive logic components which control the time during which electrical power is supplied to the fuser assembly. Fig. 3 shows a D. C. power supply 80 connected to one end of a thermistor 81, the other end of the thermistor being connected to one end of a resistor 82. The other end of resistor 82 is coupled to ground by a potentiometer 83 and, via line 93, to comparators 84-87. Potentiometer 83 may be used initially to adjust the voltage applied to the comparators for a particular fuser temperature. Physically, thermistor 81 is located within the fuser assembly and as a result the voltage applied to comparators 84-87 is a function of temperature in the fuser assembly. Power supply 80 is connected to one end of a resistor 88 and the other end of resistor 88 is connected to comparator 87 and one end of resistor 89. The other end of resistor 89 is connected to comparator 86 and to one end of a resistor 90. The other end of resistor 90 is connected to comparator 85 and to one end of a resistor 91. The other end of resistor 91 is con nected to comparator 84 and is coupled to ground by resistor 92. Thus, it may be seen that the power supply 80 and resistors 88-92 provide the reference voltages to comparators 84-87. If, for example, power supply 80 provides-12 volts, thermistor 81 and resistors 82,83 may have values such that the voltage one line 93 may have values of-2. 3v,-4. 6v,-6. 95v, and -8. 5v corresponding, respectively, to temperatures of 553C, 75^C, 95 C, and 115'C at thermistor 81. Under these circumstances, the values of resistors 88-92 may be chosen to provide reference voltages of-2. 3v,-4. 6v,-6. 95v, and-8. 5v, respectively, to comparators 84-87. Comparators 84-87 are similar and provide a binary type output. In particular, output line 97 of comparator 87 provides a binary"0"or a binary"I"when, respectively, the voltage on line 93 is more positive or less positive than the applied-8. 5v reference; output line 96 of comparator 86 provides a binary"0"or a binary"1"when, respectively, the voltage on line 93 is more positive or less positive than the applied -6. 95v reference; output line 95 of comparator 85 provides a binary"0"or a binary"I"when, respectively, the voltage on line 93 is more positive or less positive than the applied-2. 3v reference. Lines 94-97 are connected to logic components and the temperature related binary signals thereon control the maximum time per system cycle that the fuser may be on.

More specifically, line 97 is connected to a 40 ms. monostable multivibrator 98; line 96 is connected to a line 90 ms. monostable multivibrator 99, line 95 is connected to an input of a NAND gate 100 ; and line 94 is connected to an inverter 127 (see Fig.

2). Line 72 is also connected to an input of a NOR gate 101 and line 70 is coupled by a series arrangement including inverter 102, a I ms. RC delay circuit 103 and an inverting and squaring Schmitt trigger 104 to an input of NOR gate 101 and NAND g 123 is coupled to both inputs of a Schmitt trigger 124 by a 3 ms. delay RC network 125 and the output of trigger 124 is connected to an input of NOR gate 122.

Therefore, the output of gate 122, which is connected to the preset-enable input of register 121 by line 126, provides a 3 ms. binary"I"pulse 1 ms. after the beginning of each system cycle and loads the register stages A-E. Stages A and B are left floating in a binary" !" state ; stage C is loaded with a binary"I"state when the temperature in the fuser assembly is less than 55 C and with a binary"0"state when the temperature in the fuser assembly is greater than 55 C ; and, as will be described hereinafter, after start up stages D and E receive binary "0'signals from AND gate 129. The serial input of register 121 is grounded and, therefore, binary"0"s are loaded into stage A with each pulse provided on line 120.

As a result, the output of the register 121, on line 130, provides a 60 ms. positive pulse when the temperature in the fuser assembly is less than 55 C and a 40 ms. positive pulse when the temperature in the fuser assembly is greater than 55 C, one or the other of these pulses occurring during the first 190 ms. of each cycle. Line 130 is connected to a NOR gate 131 whose output is connected by line 132 to a NAND gate 133, the output of gate 133 being connected by line 134 to NAND gate 112.

The other inputs to gate 112, on lines 64 and 111, are at a binary"1"level for at least the first 190 ms. of each cycle and, therefore, the fuser assembly is turned on or 40 to 60 ms. depending on the temperature in the fuser assembly. It should be noted that the on time of the fuser assembly is a multiple of the period of the timing pulses on line 121 and, to accommodate for different support bases or ambient conditions, may be varied. Typical period variations may range from 14 ms. to 35 ms.

In the absence of print signals the fuser assembly is only turned on for 40 ms. or 60 ms. during each cycle and this is enough to keep the fuser assembly in a ready for fusing state if only a few cycles have elapsed since the previous fusing cycle.

However, the interval of time between fusing cycles is not controllable and the amount of time it takes to bring the fuser assembly to a fusing temperature is directly related to the time elapsed since the previous fusing cycle. Therefore, to provide proper fusing temperature, the apparatus of the present embodiment includes means for controlling the time during which power is applied to the fuser assembly in a pre-fusing cycle. The minimum time is 40 or 60 ms, and the maximum time is limited by the maximum fusing cycle times previously described, i. e., 330 ms., 280 ms., 230 ms., and 190 ms. corresponding to temperatures in the fuser assembly of up to 75'C, 95 C 115 C and above 115'C, respectively. The Q outputs of sh : ft register 66 (see Figs. 2 and 4) are related, as a function of time, to received print signals and the output of each of stages QD-QO may be used to predict how the support base 9 will be moved through the fuser assembly. Therefore, shift register 66 is used to drive circuitry which applies power to the fuser assembly in a pre-fusing cycle.

The pre-fusing cycle circuitry (see Fig.

4) includes a reversible up-down counter 150, a flip-flop 151 which increases the count range, and a number of gates. Since the amount of time needed to preheat a fuser assembly is proportional to the number of non-fusing cycles since the last fusing cycle, the number of non-fusing cycles are counted. As a practical limit the highest non-fusing cycle count needed is 24. Operatively, each time a non-fusing group of cycles begins the counter is reset.

It then counts each non-fusing cycle up to a selected limit and stops. When the register 66 indicates that fusing is to occur in the next cycle the pre-fusing cycle begins and the fuser is turned on until the countdown reaches zero. Nominally, the time between counts is 20 ms., the same as is used in keeping the fuser assembly warm.

However, the actual time can be adjusted from 14 ms. to 35 ms. to compensate for e. g. apparatus differences, atmospheric conditions, or paper types.

The pre-fusing circuitry functions as follows. Referring to Fig. 4, with a binary "1"provided by Qc of register 66 on line 153 and in view of the fact that line 154 provides a binary"I"except during startup, which will be described hereinafter, the output of NAND gate 155 provides a binary"0". The output of gate 155 is connected by line 156 to the clear input of flip-flop 151, resetting Q to a binary"0" level. Line 155 is also connected to the input of a NAND gate 157 and the output of gate 157, via line 158, provides a binary "I"which appears on the clear input of counter 150 and resets its outputs to binary "0"levels. As will be appreciated, this signal overrides count inputs.

If a binary"0"group begins after the binary"I"on Q, ; the resets will be removed on the leading edge of the next cycle of the apparatus. The clear on counter 150 will go to a binary"0"level and the clear on flip-flop 151 will go to a binary"I"level. As previously stated, about one 1 ms. after each new system cycle has begun a 3 ms. wide pulse is generated at the output of NOR gate 122.

This signal appears, via line 126, at the lower input of Schmitt trigger 159. The upper input of trigger 159, line 160, is at a binary"I"level until a count of 24 is reached; therefore, a binary"0"pulse, 3 ms. wide, is generated at the output of counter 150. This count up pulse will continue until a count of 24 is reached, one pulse for each system cycle occurring just after the leading edge of each system clock cycle occurs. After reset the outputs Q \, Qn, Qc, and QD of counter 150 are at binary"0"levels as is the Q output of flip-flop 151. The outputs Q 4D provide a binary count up to 16 and a count up pulse which appears on a cycle when all the outputs are at binary"I"levels on counter 150 causes a binary"0"pulse, as wide as the count up pulse, to appear on the carry output line 162. This signal appears on the preset input of flip-flop 151 and causes its Q output to go to a binary 1"level. The count up pulse also causes the counter 150 to reset to the 0 count, i. e., all outputs at a binary"0"level. The count will continue up until at the count of 24 the Qn output of counter 150 goes to a binary"I"level. This level appears, via line 163, on the lower input of Schmitt trigger 164. Since the upper input of Schmitt trigger 164, line 166, goes to a binary"I"level at the count of 16, the output of Schmitt trigger 164 goes to a binary"0"level and this appears, via line 160, at the upper input of Schmitt trigger 159. This provides a binary"I"level on line 161 regardless of the level on line 126, inhibiting further counts to the count up input. The counter 150 will remain in this state until as described hereinafter a binary"I"occurs on line 167. In many cases, the print signal pattern will not permit the counter to reach the full count of 24, but the operation of the system is similar. The countdown cycle, which begins when the next binary"I"occurs on line 167, operates with any count on the up/ down counter 150.

In the following description a count of 16 is assumed and a countdown cycle time of 20 ms. controlled by pulse generator 117 (see Fig. 2) is used. This time will allow about 16 countdown cycles. If the coundown cycle were 14 ms. long, approximately 22 cycles could be completed in one cycle (330 ms.) of the apparatus. On the other extreme, only about 9 cycles could be completed if the cycle time were 35 ms. If the counter 150 has a count higher than can be reached in one cycle of the apparatus, the additional counts are lost. This occurs because when countdown is initiated the count may not reach zero before the end of a countdown cycle and the following cycle of the apparatus will reset the counter 150 to zero in preparation for an other count up.

In a countdown cycle a binary"1" enters the QF stage of shift register 66.

This level appears, via line 167, on another input of AND gate 168. Since line 154 is at a binary"I"level except during start up, the output of gate 168 will provide on line 170 a binary'I"level. This level appears on the upper input of NAND 171. If the count on the up/down counter 150 is not zero, the output of NAND gate 172 will be a binary"I"level and if this level is provided, via line 173, to NAND gate 171. With both inputs at binary"1"levels the output of gate 171 provides a binary "0"which appears, via line 174, as an input to gate 133 and causes its output to go to a binary"I"level. Recalling that line 64 provides a binary"1", except during standby, and a binary"1"is provided on line III until a maximum time, related to temperature in the fuser assembly, is reached, it should now be apparent that the fuser assembly will remain on until counter 150 counts down to zero or the maximum fusing time per cycle of the apparatus has been reached.

About 1 ms. into the countdown cycle a count up pulse will be generated at the count up input of counter 150 and will in crease the count from 16 to 17. The up count will occur in every cycle of the apparatus, although it will be overridden by the clear input when binary"l"s are in the Q, stage of shift register 66. As mentioned above, the output of gate 168 is at a binary"1"level during preheat cycle and, via line 170, appears at the input of NAND gate 175. The output of gate 172 is also at a binary"I"level when the count is not zero and its output appears, via line 173, on the lower input of gate 175.

At the start of a cycle of the apparatus the output of variable pulse generator 117 is at a binary"1"level and this appears as a binary"0"on the output of Schmitt trigger 119. This binary"0"level appears, via line 120, on the input of NAND gate 175 and drives its output to a binary"1" level. However, when the period of the generator 117 is 20 ms. the first pulse out is 1.6 times later or 32 ms. and at this time a negative or binary"0"pulse appears on the output of the generator 117. This is inverted by Schmitt trigger 119 and for the duration of this pulse the output of gate 175 will generate a binary"0"pulse of about 0.3 ms. duration. This purpose appears on the countdown input of counter 150 and it counts down one count.

A countdown cycle proceeds with each binary"0"pulse from the generator 117.

As previously stated, the first pulse occurs 1.6 times the nominal cycle time, and sub sequent pulses are at the cycle time rate.

The NOR gates 180 and 181 decode the outputs of the counter 150 and the outputs of these gates are at binary"I"levels when both inputs to each are at binary"0" levels. The only time the output of both gates 180 and 181 are at binary"1"levels simultaneously is when all the outputs of counter 150 are at binary"0"levels. For counts below 16 the Q output of flip-flop 151 is at a binary"1"level. Therefore, for a zero count on the counter, all the inputs to gate 172 will be at binary"1"levels and will cause its outputs, on line 173, to go to a binary"0"level. In consequence line 174 provides a binary"1"to gate 133 and because its other inputs will be at binary"I"levels and its output will provide a binary"0"level which turns off the fuser. The binary"0"on the output of gate 172 will cause the output of gate 175 to remain at a binary"I"level and prevents any additional countdown signal from reaching the countdown input of counter 150. The system will remain in this state until the end of the cycle of the apparatus. Had the initial count been lower, the countdown cycle would have been completed sooner. If it were longer it would have been completed later or possibly not at all. In any case, the binary '1"on line 167 of shift register 66 will move to line 153 on the next cycle of the apparatus, and this will reset the counter 150 and flip-flop 151 to zero.

Primary fusing occurs when a binary "I"reaches the Q, stage of shift register 66 and fusing time in this cycle is limited only by the maximum on time per cycle.

More specifically, the output of the Q, stage of shift register 66 appears, via line 153, on the upper input of NOR gate 131.

With a binary"I"on line 153 the output of gate 131 will provide a binary"0"on an input of NAND gate 133 and its output will provide a binary"I"level. This level will appear, via line 134, on the input of gate 112. Therefore, the output of gate 112 will go to a binary"0"level and turn on the fuser assembly until its maximum on time per cycle of apparatus has been reached.

The preceding description described electrical power control occurring in the primary fusing cycle and in the pre-fusing cycle. During normal operation there is one exception to the described mode of operation. In the event that at least 16 cycles have occurred since the last print signal and at last two time adjacent print signals follow this non-print group, additional fusing will be required, and it will occur in the cycle before preheat. The need for additional fusing arises because in this em bodiment the fusing chamber selected is about 3"wide. If print signals occur one at a time, there are for the support base 9 three distinct start stop motion cycles in which 1"sections of the support base 9 can be subjected to the fusing. If these signals occur in groups, the time spent in the fusing chamber is reduced. In other words, the time spent absorbing energy from the preheat cycle and also as the fuser assembly is cooling, is substantially reduced for three consecutive print signals and reduced for two consecutive signals.

NAND gate 187 controls the fuser assembly for this extra heat cycle. If at least 16 cycles go by without a print signal, the Q output of flip-flop 151 will be at a binary"I"level and appears, via line 188, on an input of gate 187. In addition, when the two successive print signals provide binary"I"levels at the Qn and Q, ; stages these binary signals will appear on the inputs of gate 187 and cause its output to provide a binary"0"level, thereby turning on the fuser. The amount of time the fuser assembly will remain on will be controlled by the maximum on time per cycle of the apparatus.

If the apparatus has been off for at least a few seconds when operation occurs, the fuser assembly is considered cold because no electrical power has been applied to it for the first print signal, the fuser assembly is provided a longer ontime keep-warm cycle for a few cycles of the apparatus. Also, the prefusing cycle on the second print signal is the maximum possible, even if the second print signal closely follows the first print signal. These steps are necessary to provide adequate fusing under adverse conditions.

The specifics of how this is accomplished is set forth below.

As previously stated, when the cyclical operation begins one blank section is provided at the beginning of the support base 9. This happens as a consequence of presetting the flip-flop 65 when it is cleared.

This flip-flop stores the fact that the apparatus is in the startup mode. During standby, the output of the NAND gate 58 (see Fig. 2) is at a binary"0"level, thereby: resetting the shift register 66, presetting flip-flop 65 setting the flip-flop provided by NAND gates 190 and 191, inhibiting gate 112, resetting the shift register 121, and loading counter 150. Counter 150 will store the count of 15 when loaded because parallel inputs, not shown, are left fRoating in binary"I"states. A binary"0"on the load input causes the binary"I"s on the parallel inputs to be transferred to respective register states. When the flip-flop provided by gates 190 and 191 is set the output of gate 190 goes to a binary"1"levet and is connected to input of gate 191 by line 193. The other input of gate 191 is at a binary"I"level because the output of the shift register state Qr} is at a binary "0"level which is inverted by inverter 194.

The binary"I"s on the inputs of gate 191 causes its output to go to a binary"0" level which appears, via line 154, on the lower input of NAND gates 155, thereby providing a binary"I"level on line 156 from the output of gate 155. As a result, the clear of counter 150 is released. There- fore, when the apparatus is started, the load input of counter 150 is released and the counter will count to 24. The clear input to the counter is inhibited during startup by the binary"0"applied via line 154 to gate 155.

If the temperature is above 55 C, the apparatus'es cycles which immediately follow the startup have a keep warm cycle of 40 ms. This is the same as the normal keep warm which occurs during non-fusing cycles. The shift register 121 and the generator 117 control this time as they do in normal non-fusing cycles. As will be appreciated, if the temperature is below 55 C the keep warm cycle is 5.6 times the nominal 20 ms. of generator 117 or 112 ms. With the temperature in the fuser below 55 C a binary "I"level is applied by line 128 to the C input of register 121 and to the lower input of AND gate 129 (see Fig. 2). The binary "I"present on line 193 causes gate 129 to provide binary"1"levels to the D and E inputs of register 121. The A and B inputs of register 121 are at binary"1"levels because they are floating. Therefore, when a preset enable pulse occurs near the be ginning of a cycle of the apparatus, all five stages of shift register 121 go to binary "I'levels and the fuser assembly goes on.

About 32 ms. later the first clock pulse from the generator 117 causes the register 121 to shift. After this first clock pulse, the clock pulses from the generator 117 will occur at 20 ms. intervals. Because the serial input of the shift register is at a binary"0"level the Q, stage will go to a binary"0"level after said first clock pulse. Q,, will go to a binary"0"level on the second clock pulse, etc. On the fifth clock pulse, QR will go to a binary "0"levez and turn of the fuser assembly.

It takes five clock pulses from the genera- tor 117 to turn off the fuser assembly however, the first clock pulse occurs at a time which is 1.6 times the period of the other cycles, thus the effective on time of the fuser assembly is 5.6 times the period of the clock pulses from the generator 117.

The longer keep warm cycles continue until the first binary"I"reaches the 0,., stage of shift register 66. At this tim. e the binary"I"appears on line 196 and causes the output of NOR gate 197 to go to a binary"0"level. The upper input of NOR gate 198 is at a binary"0"level during startup, therefore, its output provides a binary"I"level and causes the fuser to go on. The fuser assembly will remain on for the portion of thee apparatus'es cycle allowed by the maximum on-time circuitry. Because the temperature in the fusing chamber is below 55 C this would be the full cycle of 330 ms. On the next cycle of the apparatus, the shift register will shift the binary"I"on stage On to Qr. However, line 167 connects this level to gate 197 and this cycle will also turn on the fuser assembly for the maximum on time per cycle limit. On the next cycle of the apparatus the binary"1"on QF will shift to Q. : This level is applied by line 153 to an input of NOR gate 131, and again this will turn on the fuser assembly for the maximum allowable time set by the thermistor's temperature. As each of machine cycles of the apparatus have been occurring, the counter 150 has been counting from the initial load of 15 toward 24. On the next cycle of the apparatus the binary"I"on the Q stage of shift register 66 will transfer to QH. This level will appear on the input of inverter 194 and resets the flip-flop formed by gates 190 and 191. The binary"0"on the input of gate 190 causes its output to go to a binary"I"level. With both inputs of gate 191 at binary"1"levels its output provides a binary"0"which appears on the input of gate 191. Thus, the output of gate 191 is held regardless of the state of inverter 194 or the shift register stage Q, t- At this time the clear input of counter 150 and flip-flop 151 are enabled, the extra fusing cycles which were transmitted by gates 197 and 198 are inhibited in the future by the binery"I"which now appears, via line 154, on the input of gate 198. The binary"0"level on the output of gate 190 also inhibits extra fusing cycles on shift register 121. Gate 129 now has a binary"0"level on its upper input, and inputs D and E of shirt register 121 are at binary"0"levels. The binary"I"on line 73 causes the support base 9 to advance and during this cycle only a keep warm fusing pulse will be generated. The counter 150 has reached the count of 23, and the next binary"1"is a minimum of three cycles behind. Therefore, the maximum count of 24 will be reached.

When the next binary"I"occurs, the fusing sequence will be the same as described above except that the counter 150 has a higher than normal count if it occurs within the next few cycles of the apparatus.

In summary, when the apparatus is operated there will be four warmup cycles.

These cyles will be 5.6 times the period of generator 117 for temperatures in the fuser assembly below 55 C or two times the period of generator 117 for such temperatures above 55 C. These four cycles will be followed by three fusing cycles which are limited only by the maximum on time limit set by the thermistor 81, 330 ms., 280 ms., 230 ms., or 190 ms. In the following cycle the support base 9 advances. These measures provide the maximum possible fusing heat without scorching the support base.

When the feed button for support base 9 is pressed, the startup sequence proceeds in a manner very similar to that of a normal start run. The startup flip-flop l90 and 191 is set, so that the NOR gates 197 and 198 and gate 129 are enabled, thereby allowing longer keep warm cycles for temperatures below 55 C. During feed of the support base 9, line 55 provides a binary "0"level which also appears on line 63.

As a result, a binary"I"level appears on the D input of flip flop 65, and it will remain at this level as long as the feed button for support base 9 is pressed. As the apparatus cycles the Q output of flip-flop 65 will remain at a binary"I"level. This causes the shift register 66 to fill up with binary"I"on all its outputs. The first three cycles will have keep warm fusing cycles controlled by shift registers 121. On the fourth cycle, stage QD of shift register 66 will go to a binary"1"level. This level will appear on an input of AND gate 201. Line 61 provides a binary"I"on gate 201 and causes the output of gate 201 to go to a binary"1"level. As described earlier, this turns on the fuser assembly during startup. For the next three cycles of the apparatus, the fuser assembly will be kept on by the binary"I"s in stages QD, QE, QF, and Q, ;.

Each of these cycles is still limited by the maximum on cycle time controlled by the temperature of thermistor 81. In the following cycle the support base 9 starts moving because of the action of the gates 74 and 76. The fuser assembly will remain on until the feed button for support base 9 is released. The shift register 66 will have binary"I"s in all its outputs after the first 8 cycles. The flip-flop 190 and 191 will reset, but this will have no effect on the output because the high on the Q, ; stage of shift register 66 will keep the fuser assembly on in each cycle of the apparatus.

In summary, for feed of support base 9 the first three cycles will be keep warm and all others will be full fusing cycles until the feed button for support base 9 is released. These cycles will be limited only by the maximum on time per cycle.

It is to be understood that the description

Claims (14)

1. gisten above with respect to the accompanying drawings is of a preferred embodiment according to the present invention, and has been set forth as an example thereof and is not to be construed or interpreted as a limitation on the claims appended hereto.

   WHAT WE CLAIM IS : 1. Apparatus comprising: a source for generating light images and print signals associated with at least some of the images, any one of the print signals being associated with only one of the images ; a support base; means for providing toner images corresponding to said light images associated with print signals, on successive sections of the support base; a fuser assembly comprising at least one heater means to which said toner images will be presented; wherein in said apparatus there are: (a) means, responsive to said print signals, for turning on the fuser assembly heater means for a predetermined time period between successive said print signals, said predetermined time period occurring immediately prior to the presentation of a said toner image to the fuser assembly ; (b) means for turning on the fuser assembly heater means upon said presentation of a toner image to the fuser assembly; and (c) means responsive to the temperature in the fuser assembly so as to be able to inhibit means (a) and (b) and thereby turn off the fuser assembly heater means during said predetermined time period.
2. 2. Apparatus as claimed in claim 1, wherein said source is adapted to generate the light images at a predetermined frequency.
3. 3. Apparatus as claimed in claim 1 or 2, wherein said apparatus comprises means for periodically turning on the fuser assembly heater means for a length of time to keep warm the fuser assembly heater means, said length of time being dependent on the temperature in the fuser assembly.
4. 4. Apparatus as claimed in claim 3, wherein said means for periodically turning on the fuser assembly heater means comprises means for varying said length of time independently of the temperature in the fuser assembly.
5. 5. Apparatus as claimed in any one of claims I to 4, wherein said heater means is electrical heater means.
6. 6. Apparatus as claimed in any one of claims I to 5, wherein said heater means is a radiant heater.
7. 7. Apparatus as claimed in any one of claims I to 6, wherein said heater means comprises at least one ribbon heating element.
8. 8. Apparatus as claimed in any one of claims 2 to 7, wherein said means for providing toner images compirses means re sponsive to the print signals so as to be able to advance the support base a predetermined amount after a said print signal occurs, and means for advancing sections of the support base at said predetermined frequency without regard to the presence or absence of said print signals.
9. 9. Apparatus as claimed in any one of claims I to 8, wherein said means (a) comprises an up-down counter adapted to count up the intervals of time occurring between successive said print signals and count down at a rate which is higher than the rate of said interval of time.
10. 10. Apparatus as claimed in claim 9, wherein said counter is adapted such that the count down rate of said counter will be independently variable.
11. . I. Apparatus as claimed in any one of claims 1 to 10, wherein said means (c) comprises means for sensing the temperature in the fuser assembly and for provid- ing binary signals related to said sensed temperature, and means responsive to said binary signals so as to be able to inhibit said means (a) and (b).
12. 12. Apparatus as claimed in claim 1, substantially as hereinbefore described with reference to and as shown in the accompanying drawings.
13. 13. A method of providing toner images, comprising using apparatus as claimed in any one of claims 1 to 12 so as to provide said toner images.
14. 14. A method as claimed in claim 13, substantially as hereinbefore described with reference to and as shown in the accompanying drawings.