GB1561394A - Electric windscreen wiper systems - Google Patents

Description

(54) ELECTRIC WINDSCREEN WIPER SYSTEMS (71) We, GENERAL MOTORS LIMITED, a British Company of High Street North, Dunstable, Bedfordshire, do hereby declare the invention for which we pray that a patent may be granted to us, and the method by which it is to be performed to be particularly described in and by the following statement: This invention relates to electric windscreen wiper systems for motor vehicles.

Windscreen wiper systems for motor vehicles customarily employ a pair of windscreen wipers comprising a wiper arm and wiper blades attached thereto, jointly operated by an electric motor driving an output member which is linked to means for effecting oscillatory movement of both the wiper arms and blade assemblies. With increasing use of relatively large windscreens on motor vehicles, and particularly on commerical vehicles, it has become necessary to use correspondingly larger and heavier wiper arm and blade assemblies which in turn have required use of a larger electric motor to operate them.

The present invention proposes the use of a separate electric motor for each wiper arm and blade assembly, the motors being connected in a circuit which ensures synchronism of the motors at the speed of the slowest motor, so that the wiper arm and blade assemblies are kept substantially in synchronism when in operation despite minor differences in the speed of rotation of the motors.

In an electric windscreen wiper system according to the present invention, there is provided a circuit for effecting synchronisation of at least two closely similar electric windscreen wiper motors, each of which drives a respective wiper arm and blade assembly, in which each motor operates a switch which is arranged to close at least once during each revolution of an output shaft connected to said motor, each switch being connected to an input of a respective bistable multi-vibrator, the output from which is fed both to a logic circuit which controls switch circuits for all of said motors and to a delay circuit for resetting all of said bistable multivibrators simultaneously upon simultaneous operation of all of said switches, the operation of the circuit being such that, as long as all of the motors run substantially in synchronism with one another, all the multi-vibrators are simultaneously reset to cause all the motors to remain switched on, but, if any one motor runs slower than any other motor in the system, the respective bistable multi-vibrator for that other motor ensures that the logic circuit switches off said other motor until said one motor comes into synchronism therewith.

Preferably each switch, when closed, connects the set input of its respective bistable multi-vibrator to the earth side of the main circuit of the windscreen wiper motors.

The logic circuit preferably is composed of a system of NAND gates, which produce outputs which control switch circuits for the motors.

The appended claims define the scope of the invention claimed. The invention and how it may be performed are hereinafter particularly described with reference to the accompanying drawing which discloses a preferred embodiment of a synchronisation circuit according to the invention, for the synchronisation of three separate D C electric windscreen wiper motors.

Referring now to the accompanying drawing, three direct current windscreen wiper motors, 1, 2, and 3, are used, each of which is provided with a wiper arm and blade assembly (not shown), and each one of which has a switch associated with an output shaft of the motor.

Thus, in the drawing, the motors 1, 2 and 3 have respective switches 4, 6 and 8 and the mechanical connections therebetween are indicated by respective broken lines 5, 7 and 9.

Switch 4 is connected to a bistable multi-vibrator 10 by means of a line 11, switch 6 is connected to a similar bistable multi-vibrator 12 by means of a line 13, and switch 8 is connected to a similar bistable multi-vibrator 14 by means of a line 15. Each one of the three switches is connected to the "set" input of the respective bistable multi-vibrator. Each one of the three switches is arranged to be opened and closed twice during each revolution of the motor output shaft associated therewith.

The output from bistable multi-vibrator loins fed through lines 16, 17 and 18 to one input of a three-input AND gate 19. Similarly, the output from the bistable multi-vibrator 12 is fed via lines 20, 21 and 22 to another input of the AND gate 19, and the output from bistable multi-vibrator 14 is fed via lines 23 and 24 to the third input of AND gate 19. The output from AND gate 19 is fed directly to the input of a mono-stable multi-vibrator 25, the output of which is fed firstly via line 26 and diode 27 to the "reset" input of the bistable multi-vibrator 10, secondly via line 26 and diode 28 to the "reset" input of the bistable multi-vibrator 12, and thirdly via line 29 and diode 30 to the "reset" input of bistable multi-vibrator 14. AND gate 19, mono-stable multi-vibrator 25 and diodes 27, 28 and 30 constitute the components of adelay circuit for resetting all of the bistable multi-vibrators 10, 12 and 14 simultaneously.

The output from the bistable multi-vibrator 10 is connected firstly via lines 16, 17 and 31 to one input of a two-input NAND gate 37, secondly via lines 16, 17 and 32 to one input of a two-input NAND gate 47, and thirdly via lines 16 and 33 to one input of a two-input NAND gate 39. Similarly, the output from the bistable multi-vibrator 12 is connected firstly via lines 20,21 and 34 to the other input of the two-input NAND gate 37, secondly via lines 20 and 35 to one input of a two-input NAND gate 38, and thirdly via lines 20 and 36 to one input of a two-input NAND gate 50. Finally, the output from the bistable multi-vibrator 14 is connected firstly via lines 23 and 40 to one input of a two-input NAND gate 54, secondly via lines 23 and 41 to the other input of the two-input NAND gate 38, and thirdly via lines 23 and 42 to the other input of the two-input NAND gate 39. The output of NAND gate 37 is connected via line 56 to the other input of the NAND gate 54; the output of the NAND gate 38 is connected via line 52 to the other input of the NAND gate 47; and the output of the NAND gate 39 is connected via line 53 to the other input of the NAND gate 50.

The output of NAND gate 47 is connected via line 57, resistor 58 and line 59 to the base of an NPN transistor 60, the collector of which is connected to one side of an armature winding of motor 1 via line 61 and line 62. The emitter of transistor 60 is connected to the base of an NPN transistor 63, the collector of which is connected to line 62 via line 64. The emitter of transistor 63 is connected to the base of an NPN power transistor 65, the collector of which is connected to line 62 via line 66. The emitter of power transistor 65 is connected to the negative, earth, side of the windscreen wiper synchronisation circuit by line 67. The three interconnected NPN transistors 60, 63 and 65 constitute an amplifying switching circuit controlling the operation of motor 1.

Similarly, the output from NAND gate 50 is fed via line 68, resistor 69, and line 70 to the base of an NPN transistor 71, the collector of which is connected to one end of an armature winding of the motor 2 via line 72 and line 73. The emitter of transistor 71 is connected to the base of an NPN transistor 74, the collector of which is connected to line 73 via a line 75, and the emitter of which is connected to the base of an NPN power transistor 76. The power transistor 76 has its collector connected to line 73 via a line 77, and its emitter connected to the negative, earth, side of the windscreen wiper synchronisation circuit via line 78. The interconnected NPN transistors 71, 74 and 76 constitute an amplifying switching circuit for controlling the current supplied to the armature winding of motor 2.

Similarly, the output from NAND gate 54 is fed via line 79, resistor 80, and line 81 to the base of an NPN transistor 82, the collector of which is connected to one end of an armature winding of the motor 3 via line 83 and line 84. The emitter of transistor 82 is connected to the base of an NPN transistor 85, the collector of which is connected to line 84 via a line 86, and the emitter of which is connected to the base of an NPN power transistor 87. The power transistor 87 has its collector connected to line 84 via a line 88, and its emitter connected to the negative, earth, side of the windscreen wiper synchronisation circuit via line 89. The interconnected NPN transistors 82, 85 and 87 constitute an amplifying switching circuit for controlling the current supplied to the armature winding of motor 3. The opposite sides of the armature windings of motors 1, 2 and 3 are connected respectively via lines 90, 91 and 92 to a 12 volt positive line 93, in which is an on-off switch 94 for the circuit as a whole.

OPERATION Closure of the switch 94 energizes the windscreen wiper system. Since each of the windscreen wipers would start moving from a parked position, the respective output shafts of the motors will occupy the same angular position relative to one another. Assuming that the output shafts are initially rotating in synchronism with one another, then, once these output shafts start to rotate, the switches 4, 6 and 8 will all close at the same time to connect the respective set inputs of the bistable multi-vibrators 10, 12 and 14 directly to earth. All of the set inputs will then be at a logic level of 0, which will result in the outputs from the bistable multi-vibrators 10, 12 and 14 all being at a logic level of 1. This, in turn, means that all three inputs to the AND gate 19 will be at a logic level 1, which produces a logic level 1 input signal at the mono-stable multi-vibrator 25. This, in turn, results in the production of a logic level 0 signal, for a predetermined time (200 ms approx.), which is applied to the reset inputs of the bistable multi-vibrators 10, 12 and 14 via the diodes 27, 28 and 30. The application of a logic level 0 signal to the reset inputs of bistable multi-vibrators 10, 12 and 14 results in the logic level of the output signal of these multi-vibrators changing from a logic level 1 to a logic level 0. Application of a reset pulse to the three multi-vibrators 10, 12 and 14 can only occur when the three motors are in synchronism with one another and the switches 4, 6 and 8 are closed.

The presence of the AND gate 19 in the delay circuit effectively inhibits the delay circuit from responding to signals other than those already specified.

If the three motors 1, 2 and 3 are substantially in synchronism with one another, then the respective outputs from the three bistable multi-vibrators 10, 12 and 14 will change from a logic level 0 to a logic level 1 and then back to a logic level 0 twice during each revolution of the respective output shafts of the three motors. As will be seen in the description hereinafter, the logic circuit will maintain a current supply to all three motors while this sequential change in logic level occurs, that is, while the three motors are in synchronism with one another.

Table I Output Logic Output Logic of Operating of NAND gates in State of Bistable Logic Circuit Motors Multivibrators (1 = on, 0 = off) 10 12 14 37 38 39 47 50 54 1 2 3 0 0 0 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 0 1 1 0 0 1 0 1 1 1 1 0 1 1 0 1 0 1 1 1 0 1 1 0 0 1 0 0 1 0 0 1 1 1 0 1 1 0 1 1 1 0 1 1 1 0 0 1 0 0 1 0 1 1 0 0 1 1 0 0 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 A truth table for the output logic of the bistable multi-vibrators 10, 12 and 14, and the corresponding output logic of the NAND gates 37, 38, 39,47, 50 and 54 of the logic circuit is shown in Table 1. From this table, it can be seen that, when the output logic of the bistable multi-vibrators 10, 12 and 14 are at a logic level of 0, then the inputs to the gates 37,38 and 39 are all at a logic level of 0, which in turn results in the output of these gates all going to a logic level of 1. This, in turn, results in the inputs to gates 47,50 and 54 going to logic levels of 0 and 1 respectively, and this produces an output from these gates at a logic level of 1. Consequently the respective amplifying switching circuits for motors 1, 2 and 3 all remain switched on.

Similarly, the last line of Table 1 indicates that exactly the same situation occurs when the output logic of the bistable multi-vibrators 10, 12 and 14 are all at a logic level of 1. Thus, provided the respective outputs of the bistable multi-vibrators 10, 12 and 14 remain at the same logic level for the same periods of time during each revolution of the respective output shafts, that is, the motors remain in synchronism one with another, then the respective amplifying switching circuits for the motors will remain switched on.

If, for example, motor 3 is faster than motors 1 and 2, then the switch 8 will close before the switches 4 and 6. Under these circumstances the output logic of the bistable multi-vibrators 10 and 12 will be at a logic level of 0, but the output logic of the bistable multi-vibrator 14 will be at a logic level 1, as shown in the second line of Table 1. This will not affect the logic levels of the outputs of the NAND gates 37, 38,39, 47 and 50, but it will result in the logic level of the output of NAND gate 54 changing from a logic level 1 to a logic level 0. This, in turn, means that the amplifying switching circuit for motor 3 will switch off, and motor 3 will slow down or stop. The amplifying switching circuit for motor 3 will remain switched off until both switches 4 and 6 are next closed during the rotation of the respective output shafts of motors 1 and 2. Once this occurs, the output logic of the bistable multi-vibrators 10, 12 and 14 are all at a logic level 1, corresponding to the last line in Table 1, which, in turn means that all three amplifying switching circuits are now switched on. Consequently motor 3 starts again, since its output shaft is now substantially in synchronism with the output shafts of motors 1 and 2.

If motor 2 is faster than motors 1 and 3, then a similar chain of events will occur, as shown in the third line of Table 1, except that the output from gate 50 will go to a logic level 0 once switch 6 is closed, and this, in turn will result in the amplifying switching circuit of motor 2 being switched off, and motor 2 slowing down or stopping until the respective switches 4 and 8 of motors 1 and 3 are closed. Once this point is reached, then the output logic of the bistable multi-vibrators 10, 12 and 14 reverts to the last line of Table 1, and all three amplifying switching circuits become switched on again.

If motor 2 is faster than motors 1 and 3, and motor 3 is faster than motor 1, then the output logic of the bistable multi-vibrators 10, 12 and 14 will first go to the situation shown in line 3 of Table 1, and motor 2 will slow down or stop. At this stage, both motors 1 and 3 are still running, albeit at different speeds to one another. Consequently switch 8 will close before switch 4, which will result in the output logic of bistable multi-vibrator 14 going to a logic level 1, which will produce the logic situation indicated in line 4 of Table 1. Under these circumstances it can be seen that the output of NAND gate 38 changes to a logic level of 0, and that the output logic of the NAND gates 50 and 54 becomes a logic level of 0. Thus, in this situation, motor 3 will also slow down and stop, until rotation of the output shaft of motor 1 results in the closure of switch 4. Once this occurs, then the output logic of the bistable multi-vibrators 10, 12 and 14 reverts to the last line of Table 1, which, in turn, results in the amplifying switching circuits for all three motors being switched on and motors 2 and 3 commencing to run.

The synchronisation system disclosed in this specification effectively monitors the speeds of the three motors at least once every revolution of the respective output shafts of those motors, and, if synchronisation is not present, the circuit effectively ensures that synchronisation is regained as soon as possible after the detection of non-synchronisation. Thus, in the situation where all three motors are attempting to run at different speeds to one another, the synchronisation circuit effectively slows down or stops the faster motors, if necessary sequentially, in order to regain synchronisation with the slowest motor. The circuit has the advantage that it is not necessary to delegate any one motor as a reference motor, since the circuit is capable of restoring synchronisation in circumstances where the speed of each of the motors fluctuates, such as will be the situation during operating conditions under load. In practice, it is found that the synchronisation circuit ensures that the switching-on and switching-off of the amplifying switching circuits for each of the motors occurs continually so that the motors are effectively kept substantially in synchronism with one another throughout their operation.

The synchronisation circuit disclosed in the Figure can be readily modified to operate for a windscreen wiper system employing only two motors. This modification can be carried out by eliminating from the circuit the electronic components associated with, for example, motor 3, replacing AND gate 19 with a similar two-input AND gate, and modifying the connections to NAND gates 38 and 39 by connecting line 42 to line 36, and by connecting line 41 te " \e 32.

This modified circuit for two motors functions in exactly a similar fashion to that already described for the three motor system.

The synchronising circuit according to the invention is capable of rapidly and effectively synchronising the operation of at least two separate windscreen wiper motors within a production speed tolerance of + or - 5 rpm. The physical size of the bistable multi-vibrators, the mono-stable multi-vibrator, and the electronic components of the logic circuit and their respective amplifying and switching circuits are such that the electronic section of the synchronising circuit could be readily housed beneath the dashboard of a motor vehicle.

Moreover it would be a relatively simple matter to design the electronic section of the synchronising arrangement as a modular unit which could be readily inserted into or removed from the electricity supply to the windscreen wiper motors of a windscreen wiper system of a motor vehicle.

Our British patent specification No. 1522521 discloses and claims a windscreen wiper system containing two closely similar electric windscreen wiper motors maintained in synchronism with one another by means of a logic circuit controlling switch circuits for said two motors, the input signals to said logic circuit being obtained from a voltage divider circuit connected to switch means actuated by said two motors.

Claims (6)

WHAT WE CLAIM IS:

1. An electric windscreen wiper system comprising a circuit for effecting synchronization of at least two closely similar electric windscreen wiper motors, each of which drives a respective wiper arm and blade assembly, in which each motor operates a switch which is arranged to close at least once during each revolution of an output shaft connected to said motor, each switch being connected to an input of a respective bistable multi-vibrator, the output from which is fed both to a logic circuit which controls switch circuits for all of said motors and to a delay circuit for re-setting all of said bistable multi-vibrators simultaneously upon simultaneous operation of all of said switches, the operation of the circuit being such that, as long as all of the motors run substantially in synchronism with one another, all the multi-vibrators are simultaneously reset to cause all the motors to remain switched on, but, if any one motor runs slower than any other motor in the system, the respective bistable multi-vibrator for that other motor ensures that the logic circuit switches off said other motor until said one motor comes into synchronism therewith.

2. An electric windscreen wiper system according to claim 1, in which each switch is arranged to close twice during each revolution of the motor output shaft associated therewith.

3. An electric windscreen wiper system according to claim 1 or 2, in which each switch, when closed, connects the set input of its respective bistable multi-vibrator to the earth side of the main circuit of the windscreen wiper motors.

4. An electric windscreen wiper system according to any one of the preceding claims, in which the logic circuit is composed of a system of NAND gates, which produce outputs which control switch circuits for the motors.

5. An electric windscreen wiper system comprising a circuit for effecting synchronisation of three electric windscreen wiper motors substantially as hereinbefore particularly described and as shown in the accompanying drawing.

6. A motor vehicle containing an electric windscreen wiper system according to any one of the preceding claims.