GB1560041A

GB1560041A - Device in a pulse code modulation transmission system for recognizing as correct a code word received at least a number of times

Info

Publication number: GB1560041A
Application number: GB3039877A
Authority: GB
Original assignee: Nederlanden Staat
Current assignee: Nederlanden Staat
Priority date: 1976-08-06
Filing date: 1977-07-20
Publication date: 1980-01-30
Also published as: SE7708773L; NL176035B; NL7608761A; NL176035C; SE426280B; DE2731402B2; FR2361031B1; DE2731402A1; DE2731402C3; FR2361031A1

Description

(54) DEVICE, IN A PULSE CODE MODULATION TRANSMISSION SYSTEM, FOR RECOGNIZING AS CORRECT A CODE WORD RECEIVED AT LEAST A NUMBER OF TIMES (71) We, DE STAAT DER NEDER LANDEN, te dezen vertegenwoordigd door de Directeur-Generaal der Posterijen, Telegrafie en Telefonie of 12, Kortenaerkade, The Hague, The Netherlands, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement:- The invention relates to a device, in a pulse code modulation transmission system, for recognizing as correct a code word received at least a number of times.

More patricularly the device serves for recognizing signalling information in a fixed time slot in a frame in a pulse code modulation transmission system for telephony. In this system a code word has to be recognized a number of times in a predetermined number of successively received code words within the signalling information of a channel. It is obvious to apply a majority decision for this purpose. When now for example eight successive code words belonging to a certain channel have been received, at least six of them have to be equal before a decision can be taken as to the code word that has. to be passed on as correct to the equipment next in line in order to be processed.

A majority decision 6 out of 8 according to the known methods has two drawbacks: 1. Every time the series of incoming code words has to be divided into blocks of eight code words from which the 6 out of 8 majority decision is taken.

2. The storage of eight code words per channel requires a relatively large amount of store room.

Another possibility is to designate per channel some code word out of a series of incoming code words as correct and to have counters determine, out of the incoming code words, the number of code words that correspond with the said code word or the number of code words that do not correspond with the same. The total maximum of code words thus determined may not exceed eight. This method too has two drawbacks: 1. Out of the series of code words per channel one code word has to be chosen, which is especially difficult when immediately after or almost immediately after this choice a series of code words that are equal as compared to one another, but that are different from the code word chosen, is received. In this case the 6 out of 8 criterion can no longer be satisfied.

2. A number of counter combinations are not likely: if three code words of the eight code words that are received differ from the code word stored, it would serve no useful purpose to go on counting in this series of eight code words, because the code word stored can no longer occur six times.

The device according to the invention does not encounter the aforesaid difficulties and offers a simple and excellent solution for the problem posed.

In accordance with the invention there is provided a device in a pulse code modulation transmission system for recognizing as correct a code word out of at least (m - 1) and no more than (n - 1) consecutively received code words after a first occurrence of said code word, the device comprising: - an input store for storing the last of the received code words for one channel; - a working store for storing the first code word to be recognized as a reference code word for each of the channels; and - a comparator circuit for comparing the code word in the input store with the code word for the appropriate channel in the working store, characterized by - means for replacing the reference code word recorded in the working store by a next received code word which differs from the reference code word and maintaining such stored code word during the reception of at least (n - m + 1) code words in the same channel; - means for replacing the reference code word recorded in the working stored by a next received code word which differs from the reference code word after the comparator circuit has found m code words corresponding with the reference code word out of no more than n successively received code words in the same channel; and - means to supply an output circuit with the code word that has been found m times within no more than n successively received code words in the same channel.

In this way one achieves a majority decision that is flexible: another reference code word is only fixed after a change in the series of code words received has occurred, and the whole series of n code words need not always be examined. Of course the series for the majority decision can be started by the reception of a mutilated code word5 after which the preceding code word is received another few times, so that the series for the majority decision would be wrongly started. However, the device according to the invention provides means for then starting a fresh series for a majority decision in such a quick way that in almost all cases the m out of n criterion can be satisfied.For this preferred purpose the device includes a state register for recording, for each of the channels of the PCM transmission system, one of the (m - 1) (n - m + 1) + 1 numerical values which indicate a combination of a) a number of received code words corres ponding with the code word recorded in the working store, and b) a number of received code words not corresponding with the code word recorded in the working store; a controlling device capable of changing the numerical value in the state register on receipt of a fresh code word; and an output circuit.

The combinations of corresponding and not corresponding code words that are not relevant are left out of consideration, in consequence of which a relatively simple and cheap solution has been found for the extraction of the signalling in a PCM-signal, a signal in which, if no special provisions are made, bit errors can occur which can have a very undesirable influ ence on the signalling because of the nature of the connection.

The invention will now be further described with the help of the drawings, in which: Fig. 1 shows an example of a PCM frame structure; Fig. 2 is a diagram of a preferred embodiment of the device according to the invention.

Fig. 3 is a function diagram of the control circuit 18 of Fig. 2; Fig. 4 is a function-time diagram represented ing the working of the device according to Fig. 2; Fig. 5 shows an embodiment of a device according to the invention with a more elaborate output circuit, and Fig. 6 is a function-time diagram representing the working of the device according to Fig. 5.

In a telecommunication network in which sections with analog transmission and sections with pulse code modulation transmission are both utilized, the disturbances caused in the analog part will be passed on to the PCM transmission part if no special measures are taken. In the speech information of a telephone system disturbances of the said kind will only affect for example the intelligibility to a limited extent. Disturbances in the signalling information on the other hand can lead to wrong decisions at the receiving end.

It is an object of the device according to the invention to eliminate disturbances in the signalling information at the receiving end of a PCM transmission line.

To explain the working of the device according to the invention a PCM frame in which the signalling information is passed on in a fixed time slot has been chosen as an example. A PCM frame of the said type is further described in CCITT recommendation G732.

The structure of the frame is represented in Fig. 1. Line a represents the multiframe consisting of 16 frames numbered =15. The structure of one frame, in this case 7, is represented on line b. A frame of this type consists of 32 time slots numbered 0--31. The first time slot 0 of each frame contains data on the frame synchronization and the channelindependent signalling. Time slot 16 of each frame contains the channel-dependent signalling of invariably two channels. The structure of the latter time slot, in this case containing the channel signalling for the channels 7 and 23, is represented on line c.

Each signalling time slot 16 comprises eight bits, of which the first two bits and the fifth and the sixth bit are used for signalling. The equipment as well as the way of processing the information contents of time slot 16 will be further described in what follows.

Fig. 2 shows an embodiment of a circuit according to the invention for recognizing a signalling code word. Each signalling code word of eight bits contains the signalling information for two channels. So the circuit consists of two identical parts, each of which is suited for processing two of the four information carrying bits a and b; the bits c and d have a fixed value and are left out of consideration.

The working of only one of the two identical circuits will be described. In the circuit 1 designates an input store, and 2 as comparator circuit, known in itself and having two-wire inputs 3 and 4 and an output 5. As long as the same code enters at the inputs 3 and 4, the output 5 will be on level 1; when the codes at the inputs 3 and 4 are different, the output 5 will be on level 0. A working store 6, formed by a shift register of 16 X 2 bits, has two two-wire inputs 7 and 8, an input 9 and a twowire output 10. As long as the input 9 is on the Olevel, the signal at the input 7 is allowed to pass; when the input 9 is on the level, the signal at the input 8 is allowed to pass.The signal of the output 10 is not only supplied to the input 7 of the working store 6 and to the input 4 of the comparator 2, but also to a two-wire input 11 of a logic circuit 12, which blocks the signal at the input 11 as long as a line 13 is on the 0-level, and which allows the signal to pass to a two-wire output 14 when the line 13 is on the 1-level. Moreover, the line 13 can serve for announcing a signal present at the outputs a and b of the logic circuit 12. This may be of importance for example when the outputs a and b of the logic circuit 12 are connected to a so-called bus bar. In addition, the circuit comprises a state register 15, formed by a shift register of 16 X 4 bits, in which one of the states that will be described in what follows can be recorded on each line in the sense that each line contains information for one channel.The state register 15 has a fourwire input 16 and a four-wire output 17.

The control of the circuit is ensured by a control circuit 18, of which a four-wire input 19 is connected to the four-wire output 17 of the state register 15 and a four-wire output 20 to the four-wire input 16 of the register 15. Moreover, the control circuit 18 has another input 21, connected to the output 5 of the comparator 2, and an output 22, connected to the input 9 of the working store 6. Furthermore the control circuit 18 is provided with an output 23 connected to the line 13 of the logic circuit 12. The incoming signal is recorded in the input store 1 and the shift registers 6 and 15 make a step on receipt of a signal C, from a timing circuit, which is not shown.

Before further describing the working of the circuit the control circuit 18 will first be further described. In a preferred embodiment the latter circuit may be a ROM, the functional diagram of which is represented by Fig. 3.

The control device 18 receives, at its input 19, a four bit binary code word representing one of the numbers 0 to 15 attributed to 16 discrete states from the state register 15, and determines, with the aid of the signal at its input 21, which will be the next state code word. When for example the state code word o is at the input 19, the state code word at the output 20 will be 0 or 1. When the state code word 8 is at the input, the state code word at the output 20 will be 9 or 13 (Fig. 3). In the aforesaid examples the choice of the output signal depends on the signal at the input 21.

Table 1 shows the truth table for the control circuit 18. It is self-evident that the truth table in Table 1 is given by way of example.

Instead of to state 1 the jump from states 11, 12, 13, 14 and 15 can also take place to another state, e.g. state 3. The consequence of this is that after a number of different code words have been recorded in the working store 6 a fresh code word will sooner be gated out from the output 10 via the logic circuit 12.

The working of the circuit (Fig. 2) will now be further described with the help of a function-time diagram of one channel as represented in Fig. 4; for the sake of clarity the intermediate signalling code words of the remaining channels have not been drawn. The incoming signalling code words consist of two bits per signal, so that four different code words, indicated by p, q, r and s in Fig. 4, are possible. When a signalling code of a channel to be examined enters via the input shift register at the input 3 of the comparator 2 and when the code word corresponds with the code word in the working store 6, a signal appears at the output 5 of the comparator 2 (Fig. 2); column 1 of Fig. 4 shows such a state.In addition it appears that the input 19 of the control circuit 18 (Fig. 2) is in state 0 (see Fig. 2), so that according to Table 1 the code word 0 appears at the output 20, which code, word is again recorded in the state register 15. In column 3 (Fig. 4) the first change occurs: the code word p received up to now has been replaced by q. Now the input 3 has a value which is different from the value at the input 4, so that a 0 appears at the output 5 and at the input 21. At the input 19 too there was still a state 0, so that according to Table 1 the output 20 now delivers a state code word 1. On receipt of the next synchronization pulse Cs (Fig. 2) the state 1 of the output 20 is recorded in the state register 15.At the same time, however, the output 22 had become cm 1" (see Table 1), so that the incoming code word q is supplied to the input of the shift register 6. On receipt of the aforesaid synchronization pulse the signalling code word p present on the relevant line is replaced by the signalling code word q. Every time the signalling code word q is now received in the time slot belonging to the channel described, a next step is made in the function diagram (Fig. 3).

In column 8 the input 19 receives the state 5 and the input 21 a " 1 " signal, so that, according to Table 1, the output 20 has the state 0. Furthermore, the output 23 reaches level " 1 " (see Table 1), so that the signalling code b is passed on to the equipment next in line via the logic circuit 12 now opened.

In column 9 (Fig. 4) a deviating code word is received once; according to the rules of the system, however, a code word must be transmitted at least eight times and the code word received may only be approved of after having been received at least six times. Con- sequently the code word s received in column 9 has to be considered an error. At the input 21 a "0" signal appears as a result of a comparison of the code words at the inputs 3 and 4. In the way as described above for the transition in column 8 the contents of the relevant line in the state register 15 are changed from state 0 to state 1 and the signalling code word s is recorded on the relevant line in the working store 6. In the way as described already the function diagram (Fig. 3) is gone through until state 11 is recorded in the state register 15, thus causing the situation as shown in column 12 (Fig. 4). According to Table 1 the output 22 now reaches level 1, so that on receipt of the next synchronization pulse the signalling code word q received is recorded in the working store 6 again. Now the situation as represented in column 13 (Fig.

4) has come into existence. The effect of the signalling code word s received in error (column 9, Fig. 4) becomes evident in column 17 (Fig. 4), where the code q is again passed on to the equipment next in line.

TABLE 1

Inputs Outputs 19 21 20 22 23 decimal binary decimal binary 0 0000 1 0 0000 0 0000 0 1 0001 1 0001 1 2 0010 1 0001 0 6 0110 2 0010 1 3 0011 2 0010 0 7 0111 3 0011 0 1 4 0100 3 0011 0 8 1000 4 0100 1 5 0101 5 0100 0 9 1001 5 0101 1 0 0000 5 0101 0 10 1010 6 0110 1 7 0111 6 0110 0 11 1011 7 0111 1 8 1000 7 0111 0 12 1100 8 1000 1 9 1001 8 1000 0 13 1101 9 1001 1 10 1010 9 1001 0 14 1110 10 1010 1 0 0000 10 1010 0 15 1111 11 1011 1 12 1100 11 1011 0 1 0001 12 1100 1 13 1101 12 1100 0 1 0001 13 1101 1 14 1110 13 1101 0 1 0001 14 1110 1 15 1111 14 1110 0 1 0001 15 1111 1 0 0000 15 1111 0 1 0001 From Fig. 4 it appears that in spite of possible errors a change in the series of received signalling code words is passed on, when in a series of seven successively received code words five code words are found which correspond with the reference code word recorded in the shift register 6 for the relevant channel.When in this series of seven code words more than two of them are received that differ from the code word recorded in the shift register 6, a fresh series is started.

This can also be deduced from the remaining situations represented by way of example in Fig. 4, which situations are self-evident after the above. When the output 14 is connected to a so-called bus bar, a common connecting channel for a number of pieces of apparatus, then a repetition of code q, as shown by column 17 row 14 (Fig. 4), is undesirable, for the equipment next in line does not receive any fresh information, while the time on the bus bar is occupied. According to the invention this difficulty can be removed by making use of the somewhat more elaborate device as shown in Fig. 5.

Fig. 6 shows in an identical way as done by Fig. 4 the working of the device according to Fig. 5. The parts of Fig. 5 that correspond with those of Fig. 2 are similarly numbered.

In addition Fig. 5 also comprises a comparator 24 with the inputs 25 and 26 and an output 27 as well as an output register 28 having the inputs 29, 30 and 31 and, moreover, a 16 X 2 bit shift register. On the analogy of the working store 6 the signal at the input 29 is passed on to the shift register 28, when the input 31 is on the cc "O"-level, whereas the signal at the input 30 is passed on to the shift register 28, when the input 31 is on the cc 1 "-level. The shift register has an output 32 and makes a step on receipt of every clock pulse Cs received from a clock signal generator, which is not shown. Morever, the device according to Fig. 5 comprises for each of the parts an AND-circuit 33 having an input 34, an inverted input 35 and an output 36. The step diagram according to Fig. 6 shows the working of the device according to Fig. 5.

Now the control of the logic circuit 12 ;s not effected directly by the output 23, but by the AND-circuit 33. In this case too the output 26 can serve again to announce a change in the signalling state to the equipment next in line. Now the Ist code word passed on by the circuit 14 is recorded in the output store 28, and only when a fresh code word that has to be passed on differs from the code word in the output store 28, which is found by the comparator 24, does the output 36 of the AND-circuit 33 cause the logic circuit 12 to open. From Fig. 6 column 17 it can be seen that the signalling code q is not passed on, because the output 27 of the comparator 24 is on the "l"-level, in consequencec of which the output 36 of the AND-circuit 33 maintains the "O"-level.

WHAT WE CLAIM IS: 1. A device in a pulse code modulation transmission system for recognizing as correct a code word out of at least (m - 1) and no more than (n - 1) consecutively received code words after a first occurrence of said code word, the device comprising: - an input store for storing the last of the received code words for one channel; - a working store for storing the first code word to be recognized as a reference code word for each of the channels; and - a comparator circuit for comparing the code word in the input store with the code word for the appropriate channel in the working store, characterized by - means for replacing the reference code word recorded in the working store bv a next received code word which differs from the reference code word and maintaining such stored code word during the reception of at least (n - m + 1) code words in the same channel; - means for replacing the reference code word recorded in the working store by next received code word which differs from the reference code word after the comparator circuit has found m code words corresponding with the reference code word out of no more than n successively received code words in the same channel; and - means to supply an output circuit with the code word that has been found m times within no more than n successively received code words in the same channel.

2. A device according to claim 1, which includes means for replacing the reference code word recorded in the working store by a next received code word which differs from the reference code word, after (n -- m) code words different from the reference code word out of at least (n - m + 1) and not more than (n - 1) successively received code words have been received.

3. A device according to claim 1 or 2, which includes a state register for recording, for each of the channels of the PCM transmission system one of the (m - 1) (n - m + 1) + 1 numerical values which indicate a combination of a) a number of received code words corresponding with the code word recorded in the working store, and b) a number of received code words not

**WARNING** end of DESC field may overlap start of CLMS **.

Claims

**WARNING** start of CLMS field may overlap end of DESC **. From Fig. 4 it appears that in spite of possible errors a change in the series of received signalling code words is passed on, when in a series of seven successively received code words five code words are found which correspond with the reference code word recorded in the shift register 6 for the relevant channel. When in this series of seven code words more than two of them are received that differ from the code word recorded in the shift register 6, a fresh series is started. This can also be deduced from the remaining situations represented by way of example in Fig. 4, which situations are self-evident after the above. When the output 14 is connected to a so-called bus bar, a common connecting channel for a number of pieces of apparatus, then a repetition of code q, as shown by column 17 row 14 (Fig. 4), is undesirable, for the equipment next in line does not receive any fresh information, while the time on the bus bar is occupied. According to the invention this difficulty can be removed by making use of the somewhat more elaborate device as shown in Fig. 5. Fig. 6 shows in an identical way as done by Fig. 4 the working of the device according to Fig. 5. The parts of Fig. 5 that correspond with those of Fig. 2 are similarly numbered. In addition Fig. 5 also comprises a comparator 24 with the inputs 25 and 26 and an output 27 as well as an output register 28 having the inputs 29, 30 and 31 and, moreover, a 16 X 2 bit shift register. On the analogy of the working store 6 the signal at the input 29 is passed on to the shift register 28, when the input 31 is on the cc "O"-level, whereas the signal at the input 30 is passed on to the shift register 28, when the input 31 is on the cc 1 "-level. The shift register has an output 32 and makes a step on receipt of every clock pulse Cs received from a clock signal generator, which is not shown. Morever, the device according to Fig. 5 comprises for each of the parts an AND-circuit 33 having an input 34, an inverted input 35 and an output 36. The step diagram according to Fig. 6 shows the working of the device according to Fig. 5. Now the control of the logic circuit 12 ;s not effected directly by the output 23, but by the AND-circuit 33. In this case too the output 26 can serve again to announce a change in the signalling state to the equipment next in line. Now the Ist code word passed on by the circuit 14 is recorded in the output store 28, and only when a fresh code word that has to be passed on differs from the code word in the output store 28, which is found by the comparator 24, does the output 36 of the AND-circuit 33 cause the logic circuit 12 to open. From Fig. 6 column 17 it can be seen that the signalling code q is not passed on, because the output 27 of the comparator 24 is on the "l"-level, in consequencec of which the output 36 of the AND-circuit 33 maintains the "O"-level. WHAT WE CLAIM IS:

1. A device in a pulse code modulation transmission system for recognizing as correct a code word out of at least (m - 1) and no more than (n - 1) consecutively received code words after a first occurrence of said code word, the device comprising: - an input store for storing the last of the received code words for one channel; - a working store for storing the first code word to be recognized as a reference code word for each of the channels; and - a comparator circuit for comparing the code word in the input store with the code word for the appropriate channel in the working store, characterized by - means for replacing the reference code word recorded in the working store bv a next received code word which differs from the reference code word and maintaining such stored code word during the reception of at least (n - m + 1) code words in the same channel; - means for replacing the reference code word recorded in the working store by next received code word which differs from the reference code word after the comparator circuit has found m code words corresponding with the reference code word out of no more than n successively received code words in the same channel; and - means to supply an output circuit with the code word that has been found m times within no more than n successively received code words in the same channel.

corresponding with the code word recorded in the working store; a controlling device capable of changing the numerical value in the state register on receipt of a fresh code word; and an output circuit.

4. A device according to claim 3, wherein the controlling device is arranged to a) indicate a first fixed numerical value which is maintained in the state register every time when, after not more than m equal code words have been successively received, a received code word is equal to the code word recorded in the working store; and b) change the first fixed numerical value in the state register into a second fixed numerical value under the control of the comparator, after this comparator has ascertained the reception of a code word that does not correspond with the code word recorded in the working store.

5. A device according to claim 4, wherein, under the control of the comparator and after the second fixed numerical value has been reached, the controlling device is arranged to increase the numerical value in the state register by one every time a received code word corresponds with a code word recorded in the working store, whereas it is arranged to increase the numerical value in the state register by (m - 1) every time a received code word does not correspond with the code word recorded in the working store.

6. A device according to claim 4 or 5, wherein, after the second fixed numerical value has been recorded in the state register, and out of the (n - 1) successive code words at least rm - 1) code words corresponding with the code word in the working store have been recognized, the controlling device is arranged to cause the first fixed numerical value to be recorded in the state register and ensure that the code word recorded in the working store is passed on to the output circuit.

7. A device according to claim 4, 5 or 6, wherein after the second fixed numerical value has been recorded in the state register and out of (n - 1) successive code words at least (n - m + 1) code words not corresponding with the code word in the working store have been recognized, the controlling device is arranged to cause a fixed numerical value, different from the first fixed numerical value, to be recorded in the state register.

8. A device according to any preceding claim, which includes an output circuit which comprises a second comparator, an output store in which the last code word supplied to the output is recorded, and a logic circuit which is also controlled by the second comparator and which only allows a code word to be supplied from the working store to the output when this code word does not correspond with the code word recorded in the output store.

9. A device substantially as hereinbefore described with reference to Figs. 1 to 4 or Figs. 5 and 6 of the accompanying drawings.