GB1559280A - Inverter arrangements - Google Patents

Description

(54) IMPROVEMENTS IN OR RELATING TO INVERTER ARRANGEMENTS (71) We, THE MARCONI COMPANY LIMITED, a British Company, of Marconi House, New Street, Chelmsford, Essex, CMi 1PL, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement:- This invention relates to inverter arrangement that is to say arrangements for producing alternating waveforms from direct current sources.

For many years inverter arrangements have generally taken the form of a square waveform generator followed by a LC (inductance/capacitance) filter. In the case of large inverter arrangements, correspondingly bulky and heavy filters have hitherto been used. Often the weight of the ,filter accounts for half of the weight of the total apparatus.

The present invention seeks to provide improved inverter arrangements in which the use of large and bulky LC filters is avoided.

According to this invention an inverter arrangement providing an output having a given number n of phases comprises generating means for generating a polyphase waveform having a number g of symmetrical phases connected to a static g to n phase converting transformer having a number of limbs equal to the number g of phases generated by said generating means and a number of secondary windings embracing each limb equal to the number n of phases required of the output waveform.

Static phase converting transformers are described by J. E. Parton in I.E.E.

Monograph Number 13, Published 15th November, 1951 (Proc. flEE. Volume 99, Part N, 1952, Pages 12 to 23).

The present invention makes use of the harmonic cancellation which is incidentally a feature of such static phase transformers to provide a satisfactorily low harmonic content in an inverter arrangement, whilst avoiding the hitherto customary bulky and weightly LC filters.

The number g should not equal the number n and normally g is greater than n.

Typically where a three phase output is required (i.e. where n equals 3) said means for generating said waveform is such that said waveform has five symmetrical phases.

Usually, but not essentially, g and n are odd numbers.

Recently inverter arrangements have been developed which comprise logic circuits which utilise multi-pulse waveforms to generate a required polyphase waveform and according to a preferred feature of this invention said generating means comprises logic means provided to utilise a multi-pulse waveform to generate said polyphase waveform, said multipulse waveform being controlled both as regards pulse width and pulse spacing. Said logic means may be digital or analogue logic means.

By controlling both pulse width and pulse spacing it has been found that certain harmonics can be substantially reduced in the polyphase waveform prior to its application to the phase converting transformer.

In the case of one example of inverter arrangement in accordance with the present invention, the waveform utilised by said logic means comprises a fourteen step waveform equivalent to a three pulse per half cycle waveform combined with a square wave of half amplitude.

The combined effect of logic generating means and a static g to N phase converting transformer as described above is to provide an inverter arrangement which is particularly compact and with inherently low harmonic content in its output waveform.

The invention is ilustrated in and further described with reference to Figures 1 to 9 of the accompanying drawings in which, Figure 1 is a schematic diagram of one three phase inverter arrangement in accordance with the present invention, Figures 2 and 3 illustrate the synthesis of two of the phases of the output waveform of the inverter arrangement of Figure 1, Figure 4 is an explanatory phasor diagram, Figures 5 and 6 are explanatory graphical diagrams, Figure 7 is an explanatory diagram, Figure 8 is a block schematic diagram illustrating a digital inverter in accordance with the present invention and Figure 9 is a block schematic diagram of an analogue inverter in accordance with the present invention.

J. E. Parton established that, with a static phase converting transformer as described in his monograph referred to earlier, balanced transformation takes place when the turns ratios form a matrix of values corresponding to the cosines of the phase angles involved.

From considerations of symmetry, in a three phase system the 3rd, 6th and 9th harmonics are of the same phasing from all three input phases, i.e. they have zero phase sequence. As a result any conection which cancels zero phase sequence components, such as a delta or interconnected star, will eliminate the triple harmonics. The elimination in the more general case applies when the phasors for the harmonic concerned form a closed polygon. In the particular case of a three phase system, the polygon is of zero area.

It may be shown that in a system of K phases, the polygon will always close, except for harmonics of number 2KS *1 where S is an integer or zero.

If there are K limbs on the transformer, each wound with the same number of turns and connected to a K phase balanced supply, one may obtain an in-phase system by winding turns in the proportion given by the matrix

The term on the pth. row and the qth. column will be

The primary voltage on the qth. column may be expressed as

where m is the harmonic.

The secondary voltage is therefore

on any one winding. The sum of the voltages for the pth. phase is therefore

q=K 2#m 2# 2# = V sin m wt # cos (q-1) cos (p-1) cos (q-1) q=1 K n K q=K 2#m 2# 2# - V sin m wt # cos (q-1) sin (p-1) sin (q-1) q=1 K n K q=K 2#m 2# 2# + V cos m wt # sin (q-1) cos (p-1) cos (q-1) q=1 K n K q=K 2#m 2# 2# - V cos m wt # sin (q-1) sin (p-1) sin (q-1) q=1 K n K 2# q=K 2#m 2# = V sin m wt cos (p-1) # cos (q-1) cos (q-1) n q=1 K K 2# q=K 2#m 2# - V sin m wt sin (p-1) # cos (q-1) sin (q-1) n q=1 K K 2# 2# q=K 2#m + V cos m wt cos (p-1) cos (q-1) # sin (q-1) n K K 2# q=K 2#m 2# - V cos m wt sin (p-1) # sin (q-1) sin (q-1) n q=1 K K V 2# q=K 2# 2# = sin m wt cos (p-1) # cos (q-1) (m+1) + cos (q-1) (m-1) 2 n q=1 K K V 2# q=K 2# 2# + sin m wt sin (p-1) # sin (q-1) (m+1) - sin (q-1) (m-1) 2 n q=1 K K V 2# q=K 2# 2# + -cosmwtcos (p-1) - 2 sin (q- 1) (m+1) - + sin (q-l) (m-1) @) 2 n q=l K K V 2# q=K 2# 2# + cos m wt sin (p-1) # cos (q-1) (m+1) - cos (q-1) (m-1) K K 2 n q=l R K q=K 2# # cos (q-1) (m+1) q=1 K represents the sum of the projections of the sides of a closed polygon and is zero, unles m + 1 is equal to a multiple of K, when the sum is simply equal to K.

The same applies to q=K 2# # cos (q-1) (m-1) q=1 K only this time the sum is zero unless m=l1.

Similarly the sine terms also total zero, but there are no exceptions given by choos ing m=1 or K-1.

The value of the output is therefore zero unless m=1 or K-1, or to be more exact. 2SK#1 where S is an integer or zero. It is then:

The output is therefore a balanced set of n phases, containing only the fundamental and harmonics adjacent to integral multiples of twice the number of phases.

In the case of a five phase system, the output is: Fundamental, 11th 21st 31st...harmonic, positive sequence 9th, 19th 29th... harmonic, negative sequence The closing of the polygon depends on whether the harmonics phase sequence appears in normal order, zero phase sequence, or interlaced. The sequences for the harmonics relative to the transformer input are:

Fundamental 11th etc 1 2 3 4 5 3rd, 13th....etc 1 42 5 3 5th, 15th....etc 1 1 1 11 Eliminated 7th, 17th.... etc 1 3 5 2 4 9th, 19th... .etc 1 5 4 3 2 If an input waveform consisting of a symmetrical polyphase system is applied to a phase converting transformer, the intermediate harmonics should be eliminated. This will apply irrespective of the harmonic spectrum of the input, provided that the symmetry is maintained. Even in the worst possible case, a square wave output, the first harmonics to be encountered in the output are the 9th and 11th, theoretically of amplitude 11.1% and 9.1% of the fundamental respectively.

It is this characteristic which is made use of in the present invention.

Referring to Figure 1, a five phase inverter is represented at 1. Inverter 1 provides a five phase output waveform which is unsmoothed, other than by natural harmonic cancellation if the inverter 1 is as described lated with reference to Figures 5 to 9. The five phases provided by inverter 1 are symmetrical. In order to provide symmetry of the phases, the inverter 1 includes five identical power stages driven from a Johnson type counter clocked at five times the output frequency. Two of the outputs are inverted in roder to produce the required symmetrical phase pattern.

A static phase converting transformer 2 consists of as many limbs as there are phases at the output of inverter 1, i.e. five, these being referenced 3. 4, 5, 6 and 7 respectively. Each limb contains a primary winding 8, 9, 10, 11 and 12 respectively. Each phase of the inverter 1 is connected to one of the primaries 8 to 12.

The three output phases, appearing at output terminals 13, 14 and 15 respectively, are generated by three secondary windings each extending between one of the output terminals 13, 14 or 15 and a common rail 16. As will be seen, each secondary winding has turns embracing each limb, 3, 4, 5, 6, and 7.

The winding turns are as follows where S indicates a start and F a finish:-

Limb 3 Limb 4 Limb 5 Limb 6 Limb 7 Primary S 100 F S 100 F S 100 F S 100 F S 100 F Secondary connected to S 200 F S 62 F F 162 S F 162 S S 62 F output terminal 13 Secondary connected to F 100 S F 196 S F 20 S S 182 F S 134 F output terminal 15 Secondary connected to F 100 S S 134 F S 182 F F 20 S F 196 S output terminal 14 The synthesis of the phase appearing at output terminals 12 and 13 are illustrated in Figures 2 and 3 respectively. In both Figures 2 and Figure 3 a is the voltage appearing at the output terminal in question and b, c, d, e, and f represent respectively the contributions from the windings on limbs 3, 4, 5, 6 and 7 respectively.

With such an arrangement percentages of harmonics (up to the 21st harmonic) present at the outputs were as follows:- Phase A - Symmetrical Phase B -- Asymmetrical Harmonic Number A B Harmonic Number A B Fundamental 100 100 2nd 0.4 0.2 both 0.5 OA 3rd 1.3 2.1 13th 0.3 0.1 4th 0.3 0.1 14th 0.25 0.2 5th 1.0 1.9 15th 0.2 0.3 6th 0.3 0.2 16th 0.1 0.2 7th 0.9 0.6 17th 0A 0.1 8th 0.5 OA 18th 0.45 0.35 9th 13.0 10.8 19th 6.5 5.25 10th OS 0.1 20th 0.55 0.5 I:lth 9.8 8.8 21st 5.3 4.4 It will be seen that only the 9th, 11th, 19th and 21st harmonics were present in significant amounts. Some other components are believed to be due to a slight asymmetry in the phases applied to the transformer or to residual magnetism in its core and a rounding off of the turns to whole numbers.

If the two phases at the output terminals 12 and 13 are displayed fr may be observed that, whilst good approximations to sine waves, they are not identical. The reason for this is that the principal harmonic components, the 9th and the 11th, have negative and positive phase sequences respectively and do not therefore lie in the same phase relationship to the fundamental in all three outputs. The outputs of the three phases at the nth harmonic are: 5 5 5 - . sin n wt, sin (n we + 120 ), | sin (n wt - 120 ) 2n 2n 2n 5 5 and not sin n (wt+120 ), sin n (wt-120 ) 2n 2n The primary neutral point (not shown) has a voltage relative to the mid-point of the supply rails (also not shown) which takes the form of a square wave at the 5th harmonic of amplitude equal to one fifth of the supply rail voltage. This point may be returned to the mid-point of the supply rails without changing the output waveform.

The start connection on the five phase side results in a crenellated waveform on an individual winding. In order to reduce the eddy current losses it would seem to be better to use a waveform with less discontinuities, which would be obtained by connecting across phases as far apart as possible. This results in a "pentacle" connection, where the windings form a closed loop with the following sequence: Finish 1 to start 3 Finish 3 to start 5 Finish 5 to start 2 Finish 2 to start 4 Finish 4 to start 1 Referring to Figure 4 the phasor diagram shows how the total output is built up from the five secondary windings. The ratio of the output voltage to the turns, relative to that for the in phase limb is 1+2 cos 72 + 2 cos 144 = 0.7725 1+2 cos 72 - 2 cos 1440 for a three limb winding it is: 1 + 2 cos 120 = 0.75 1-2 cos 1200 As the number of windings increases, the ratio approximates to Ir 4 Current waveforms in the windings, both primary and secondary, approximate to sinusoids, and would become sinusoidal with a small amount of filtering.

The preferred nature of inverter 1 will now be described with reference to Figures 5 to 9.

Referring to Figure 5, this shows at (a) a six pulse waveform (three pulses per half cycle) which may be utilised to generate a single phase alternating voltage by a logic circuit inverter. Both the pulse width and the pulse separation of the three pulses is controlled. In this particular case, the set of curves shown in Figure 5 illustrate the variation of the angles #1, #1, #2 and 0, (where 8, is half the width of one of the outer pulses, 18, is the distance between the centre of the middlepulses and the centre of either of the outer pulses and 0i is half the width of the centre pulse) for different values of Vmax Vdc Using this digital waveform, the output alternating waveform will appear substantially free from third and fifth harmonics.

For polyphase inverters, with which the present invention is concerned, a waveform is utilised which consists of the equivalent of the three pulses per half cycle waveform shown at (a) in Figure 5, combined with a square wave of half the amplitude of the aforementioned three pulse per half cycle waveform. This provides a fourteen step waveform as shown at (b) in Figure 6. Again the set of curves in Figure 6 show the variation of the angles # 2 e2 and #3 as shown at (b) for different values of Vmax Vdc Using this waveform, the polyphase alternating waveform generated will be substantially free from third and fifth harmonics.

Referring to Figure 7, here the output voltage of each phase is considered as a "phase" voltage to a star point S.P. which has a d.c. potential half-way between the d.c. potential of the supply rails R1 and R2. The point S.P. may be taken as a.c. earth and the output of the circuit as being taken between this point S.P. and point OY. As the semiconductors S.C. are switched, the half bridge output is connected alternately to the two supply rails R1 and R2. The switch pattern shown at (b) in Figure 6, is, as has already been mentioned, the equivalent of the switch pattern shown at (a) in Figure 5 superimposed on a half amplitude square wave of appropriate frequency. The single phase waveform shown at (a) in Figure 5 gives Fourier series co-efficients n-i 4Vdc bn = (-1) bn = (sin n#1 = 2 cos n#2 sin n#3) 2 where n is odd.

The presence of three variables allows selection of, say b1=.5, b3=0 and b5=0 to obtain #1, #2 and #3 for a particular output condition and solution are obtainable for a wide range of b1. The fourteen step waveform gives 4Vdc n-1 bn = ( - (-1) (sin n#1 + 2 cos n#2 sin n#3)) n 2 retaining the three variables and all the properties of the other waveform. In addition solutions exist for both positive and negative values of bl.

Referring to Figure 8, in this case the inverter is a five phase inverter. A master clock 1 provides timing signals to a divider chain 2 which provides five phased outputs 3, 4, 5, 6 and 7. Each of the phased outputs 3 to 7 are connected to control a different loadable counter 8, 9, 10, 11 and 12. Each leadable counter 8 to 12 derives an input number from a different section of a read-only memory arrangement 14. Each number relates to the angle interval between changes in the required waveform. Each loadable counter 8 to 12 is conected to provide input to a step counter 15, 16, 17, 18 and 19 respectively. Each counter 15 to 19 at the end of its count corresponding to a required change in the required waveform, instructs a step control circuit 20, 21, 22, 23 or 24 respectively to change from " high " to "low" or vice versa. At the same time a signal Is passed back via lead 25, 26, 27, 28 or 29 respectively to control the transfer of the next angle interval representative number from the appropriate section of the read-only memory arrangement 14 to the respective loadable counter 8 to 12.

Referring to Figure 9, two inputs corresponding to Vmax and Vdc are provided to a function generator 30 which in turn applies the function Vmax Vdc to three further function generators 31, 32 and 33. Function generator 31 generates the function (#2+#3). Function generator 32 generates the function (#2-#3) and function generator 33 generates the function (#1). The outpus of the function generators 31 to 33 are each applied to a comparator 34, 35 or 36. Each of the comparators 34, 35 and 36 also derives an input from the output of a triangular wave generator 37, the output waveform of which is represented at (c).

Comparators 34, 35 and 316 provide output waveforms as represented at (d), (e) and (f) respectively. The waveforms (d), (e) and (f) are then combined to provide the control waveform represented at (a) in Figure 5.

Claims (11)

WHAT WE CLAIM ES:-

1. An inverter arrangement providing an output having a given number n of phases comprising generating means for generating a polyphase waveform having a number g of symmetrical phases connected to a static g to n phase converting transformer having a number of limbs equal to the number g of phases generated by said generating means and a number of secondary windings embracing each limb equal to the number n of phases required of the output waveform.

2. An inverter arrangement as claimed in claim 1 and wherein g is greater than n.

3. An inverter as claimed in claim 1 or 2 and wherein g and n are odd numbers.

4. An inverter arrangement as claimed in any of the above claims and wherein a three phase output is required (i.e. n=3) and said means for generating said waveform is such that said waveform has five symmetrical phases (i.e. g =5).

5. An inverter arrangement providing an output having a given number n of phases substantially as herein described with reference to Figures 1 to 4 of the accompanying drawings.

6. An inverter arrangement as claimed in any of the above claims and wherein said generating means comprises logic means provided to utilise a multi-pulse waveform to generate said polyphase waveform, said multi-pulse waveform being controlled both as regards pulse width and pulse spacing.

7. An arrangement as claimed in claim 6 and wherein said logic means is digital logic means.

8. 8. An arrangement as claimed in claim 6 and wherein said logic means is analogue logic means.

9. An inverter arrangement as claimed in any of the above claims and wherein said generating means is substantially as herein described with reference to Figures 5 to 7 of the accompanying drawings.

10. An inverter arrangement as claimed in any of the above claims and wherein said generating means is substantially as herein described with reference to Figure 8 of the accompanying drawings.

11. An inverter arrangement as claimed in any of the above claims 1 to 9 and wherein said generating means is substantially as herein described with reference to Figure 9 of the accompanying drawings.