GB1558576A

GB1558576A - Circuit arrangement for displaying symbols

Info

Publication number: GB1558576A
Application number: GB4487177A
Authority: GB
Original assignee: Siemens AG
Current assignee: Siemens AG
Priority date: 1976-11-15
Filing date: 1977-10-27
Publication date: 1980-01-03
Also published as: IT1087493B; NL7711948A; DE2651973C2; DE2651973B1; FR2371021A1; AT360095B; JPS5362425A; ATA775777A; FR2371021B3

Description

(54) A CIRCUIT ARRANGEMENT FOR DISPLAYING SYMBOLS (71) We, SIEMENS AKTIENGESELLSCHAFT, a German company of Berlin and Munich, Germany (Fed. Rep.), do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement: This invention relates to a circuit arrangement for displaying symbols.

According to the present invention there is provided a circuit arrangement for displaying symbols, comprising a display unit and a data processing unit arranged to supply signals representing the symbols to be displayed, there being symbol storage connected between the data processing unit and the display unit and comprising a plurality of storage locations for storing what, in correct operation of the arrangement, will be the same symbol at any one time, the arrangement being such that in operation thereof a symbol display position of the display unit will receive contents from one after another of said storage locations.

- It is to be understood that in the above paragraph the term "symbol" is to include both the case of a symbol consisting of a single character or sign, and the case of a symbol consisting of a plurality of characters or signs.

Display units can be employed which have a wide range of possible designs. Inter alia, there are known: display panels having incandescent lamps arranged at raster points; visual devices for reproducing letters, numerals and optional symbols; glow lamp elements the electrodes of which have the form of the symbols to be shown and also 7-segment display elements with which numerals are assembled from seven lines, the full seven lines forming two squares disposed one above the other.

It is possible to design a circuit arrangement according to the invention such that it requires no separate fault detector which tests the stored symbol signals for correspondence and in the event of deviations transmits a fault signal. For indicating a fault, the display unit itself may be employed owing to the fact that the display unit receives signals from one storage location after another.

The new circuit arrangement is particularly suitable for application to redundant (i.e.

multi-channel) processes wherein the symbol signals are stored intermediately in duplicate. In the event of a fault on a symbol which ought to be constant, two different symbols will be displayed alternately. In the event of fault-freedom, always the same symbol is displayed. If the symbol signals are stored intermediately more than twice, and if the display unit is triggered by each stored symbol for the same amount of time, then in the event of a fault in one channel two symbols (one correct, one incorrect) will be displayed on the display unit and from the ratio of the display times it can be recognised which is the correct symbol, provided that the correct symbol remains constant.

For the display of numerals, there are most frequently employed display units which are built-up from display regions provided by 7-segment display elements, with which in each case a numeral can be shown. The individual segments may be provided by incandescent or glow lamps, liquid crystals or luminous diodes, and are therefore wear-free. Sometimes display units are to be capable of being operated within a wide ambient temperature range and under disadvantageous lighting conditions, for example in direct sunlight. Such conditions can be encountered for example with petrol dispensing pumps of street filling stations. In addition, it may be required of the display elements that on failure of the supply voltage they indicate the last value indicated before voltage failure. In order to meet all these conditions there are preferably employed mechanical 7-segment display elements. The segments are pivotal and can be put into two positions with the aid of an electromagnet. In one of the positions a line appears at the front side and in the other position a uniformly toned surface. If all seven segments are displayed or set, the seven lines represent the figure eight. For setting the segments, the segment coils must conduct a current in one direction; with a current in the opposite direction, the segments can be obscured or reset. As a rule, the current strength is so considerable that the coils are not triggered directly by commercially conventional integrated switching circuits, but via power amplifiers.

As a rule, these electromechanical 7segment display elements are triggered in such manner that all the segments are reset and then those segments are set which are necessary for showing the desired symbol.

Such a mode of operation would have the disadvantage that even when a constant value were indicated, on receipt of an instruction from the different storage locations the segments would always be switched and they would thus have only a comparatively short surface life. A development of the invention, whereby the segments perform in operation no more changes than are necessary means that in a first phase those segments which are to be visible are set one after the other. the segments which have already been set performing no switching process; and in a second phase those segments which are not to be visible are reset one after the other, again those segments which have already been reset performing no switching process. It is alternatively possible to reset the segments in the first phase and in the second phase to set the other segments. Thus, at each instruction from a different storage location only those segments are switched the position of which needs to be changed in order to show another symbol. On supplying signals for a single symbol no segments are changedover. If, however, a fault occurs in the triggering. switching or in the transfer of the symbol signals or in the data processing unit supplying the symbol signals, the segments are triggered by different signals in alternation, and there are therefore automatically displayed two different symbols. In this manner, even if no new symbols are issued, the functioning of the circuit arrangement is monitored.

For detecting faults or errors occurring in the data processing unit, the latter can be operated in such manner that the data to be processed are written several times into different data storage zones therein, and that the programmes for processing the data are also present several times in different programme storage zones. It is advantageous if the programmes are different in such manner that they vary in the individual programme steps but lead to the same results on identical data being processed. A data storage zone can be associated with each programme. In the case of two programmes and two data storage zones, there may be processed with the programme contained in the first programe storage zone the data stored in the first data storage zone, and with the programme contained in the second programme storage zone the data storage in the second data storage zone. If there is no fault, two identical results are obtained. In the event of a fault, the results are different. Additionally, the programme contained in the first programme storage zone may operate on the data in the second data storage zone; and the programme contained in the second programme storage zone may operate on the data in the first data storage zone. Thus four identical results will be obtained if there is freedom from error or fault. The results can be issued in parallel or in series in the case of symbol signals and addresses to symbol and address stores.

Where the electromechanical 7-segment display element is employed, the segment control coils could be triggered simultaneously. However, this would have the disadvantage that the source of voltage for the coils would be required to provide extremely high current for a short period of time. Thus, advantageously the segments are triggered one after the other so that a uniform current of uniform current strength flows out of the source of voltage. Of course this mode of triggering can be used with other types of display element also.

If the display unit has a plurality of display regions for the simultaneous display of a plurality of symbols, for for example multi-digit numerals, then the segments may expediently be triggered via line and column wires, the display regions being selected for example via the column wires and the segments via the line wires. The display regions and the segments are, in such an arrangement, triggered one after the other.

The lines via which the segments are selected are hereinafter designated segment lines and the lines via which the display regions are triggered, address lines. Correspondingly, the switches with which the signals derived from the symbol signals are supplied to the segment lines are called segment switches, and the switches which are switched as a function of the addresses determining the selected display regions are designated address switches. Where the display regions are provided by electromechanical display elements, the seg ment and address switches may expediently be semiconductor switches comprising a power stage for triggering the coils of the display elements.

Expediently the addresses, as also the symbol signals, may be intermediately stored a plurality of times, in order that also the correct addresses are provided. In the event of two identical addresses, during disturbance-free operation, with two address switches associated with the address display regiona, triggering may be so effected that one address switch applies one electrical side of the display region to one of the poles of a source of voltage. whereas a segment switch switches the other electrical side of a selected segment to be set to the other pole of the source of voltage. The other address switch then applies the one electrical side of the display element to the other pole of the source of voltage. whereas via a second segment switch the other electrical side of a selected segment to be reset is connected with the one pole of the source of voltage. In the event of a faulty transfer of an address. the segments of one display element are only set and none are reset, and those of another display elemnt are only reset, none being set. From this the error can be recognised.

The segment and address switches may be controlled by a control means so designed that in the case of n segments per display region it has 2n outputs. Connected to these outputs may be one set of inputs of segment and address coincidence elements to the outputs of which the control inputs of the segment and address switches are connected. The coincidence elements may be triggered in such manner that in a first phase one of the address switches of each display region is closed, whereas the outputs of one 6f a first symbol decoder are switchedthrough one after the other to the control inputs of the first segment switches. In a second phase the second address switch is closed and the first is opened of each display region, whereas the output signals of a second symbol decoder are applied via inverter elements one after the other to the control inputs of the second segment switch es. Another sequence of the segment and address switches is also possible.

After working through a triggering cycle.

during which the segments of a display region are put into their correct conditions.

the control means may supply to the data processing unit suppling the symbol signals and addresses a request for supply of a fresh symbol signal and a fresh address. These are made ready. via transfer sections in the symbol stores and the address stores for the next triggering cycle.

The next address and symbol signals transferred by the data processing unit and inserted into the address and symbol stores are preferably, in the case of the display of multi-digit numeral, not these for the digit having the next-higher or lower digit position. Thus when the multi-digit numeral varies, such as for example when indicating the quantity and price of fuel as it is delivered from a filling station petrol pump, preferably the symbol signals and addresses for the higher-value digits are introduced at lower frequency into the symbol and address stores than the symbol signals and addresses for the display regions representing the lower-order digits. This means that the more rapidly varying digits are more frequently transferred.

Low wear of the display regions can be achieved if the frequency at which the symbol signals and addresses are inserted into the symbol and address stores is limited to that frequency at which an observer can still discern the display. Therefore, for example when dispensing fuel with maximum through flow, the numerals which indicate the one hundredth parts of a litre are caried not after the supplying of each 1/100 litre. but in time intervals of for example 0.1 sec.

A current metering resistor may be connected between the two poles of the source of voltage supplying the current to the display regions. The resistor produces a voltage drop across it which is a measure of the current conducted by the display region in setting and resetting its segments. When the arrangement is operating correctly. this current will have a value within a pre determined range. By employing a voltage discriminator, it is possible to ascertain whether the current employed is impermiss ibly large or small. In addition, it has been stated hereinbefore that the individual seg ments in a triggering cycle can each be triggered once. independently of whether they have or have not already been set.

Thus in the case of n segments, n pulses must occur across the current measuring resistor. In a further advantageous embodi ment, these pulses are counted in a monitor ing counter. After completion of a trigger ing cycle. it is monitored whether the counter state is equal to the number of segments to be triggered during a triggering cycle.

For a better understanding of the inven tion and to show how it may be put into effect, reference will now be made, by way of example, to the accompanying drawings, in which: Figure 1 shows the circuit diagram of an embodiment of the invention; Figure 2 shows the principle of 7-segment display; and Figure 3 shows pulse diagrams occurring in the arrangement according to Figure 1.

Referring to Figure 1, DVE designates a data processing unit which takes up values of measurement value pick-up systems, numeral adjusters and the like, effects logic linkages and calculates results which are to be displayed by a display unit comprising displaying elements AE1 ... AEn. The data processing unit DVE may for example be a micro-processor, its word width being 8 bits.

Eight data lines can be connected to it. In the case of the illustrated embodiment, the eight data lines are sub-divided into four lines DL1 and four lines DL2, via each of which a code signal is supplied representing a symbol to be displayed.

Connected to the lines DL1 and DL2 are respective symbol stores ZSP1 and ZSP2 into which, in the case of correct operation, the same symbol signal is in each particular instance inserted. Duplicated transfer and storage of the same symbol signal is int tended to make it possible to recognise errors or faults during transfer and storage.

Expediently, the two symbol signals are calculated in the data processing unit DVE with the aid of different sub-programmes from the same output values, in order that also errors of the data processing unit DVE can be recognised.

The display unit AE1 ... AEn is to display multi-digit numerals, but the four wires of the lines DL1 and DL2 can transfer only one symbol signal for a numeral at a time, Therefore, the data processing unit DVE issues, together with each symbol signal, an address which determines by which one of the display elements AE1 ... AEn the numeral characterised by the symbol signal is to be displayed. These addresses are also transferred twice, via the data lines to address stores ASP1 and ASP2. In the event of correct operation, the same address values are contained. In the event of deviation of the contents of these stores ASP1 and ASP2, it can be deduced that there has been an error during address transfer or during computation of the addresses.

Connected to each of the two symbol stores ZSP1 and ZSP2 is a respective symbol decoder ZDC1 and ZDC2 which decodes the symbol signals of 4-bit width into signals suitable for triggering 7-segment display elements. The principle of the 7-segment display is shown clearly in Figure 2. Figure 2a shows the case where all 7-segments A, B ... G are displayed or set. The 7-segments are so arranged that they form two parallelograms positioned one above the other, therewith displaying the numeral 8 when all the segments have been displayed or set. If, as shown in Figure 2b. only the A. B and C are displayed or set, the numeral 7 is shown or, if additionally the segments G and D are displayed or set, the numeral 3 is shown. In the case of the example of embodiment, the segments are mechanically rotatable and have two faces which are visible in respective ones of two switching conditions of the segment. Marked on one of the faces is a line. The peripheral field of this face and also the whole of the other face have the same colpur tone as the visible nonrotatable portions of the front face of the display element. The segments are rotated or swivelled with the aid of electromagnets.

With a currant surge in one direction a segment ig set or displayed by showing the line on one face, and with a current surge in the opposite direction the segment is obscured or reset by showing the opposite face. In the currentless condition, the last previous switching position is maintained.

Thus, each display element comprises substantially a display portion with the segments, and a control portion with the segment coils.

The symbol decoders ZDC1 and ZDC2 do not simultaneously transmit their output signals, but do so in alternation in response to a clock pulse at an input T1 of approximately 1 c/s. the pulse being fed directly to a release input of the symbol store ZSP1 and via an inverter IV to the release input of the symbol store ZSP2.

The seven outputs al ... gl or a2 ... g2 of the symbol decoders ZDC1 and ZDC2 are each associated with a segment of the display elements AE1 ... AEn. This means that: for displaying the numeral 8, a "1" signal appears at all outputs; for showing a numeral 7, a "1" signal appears at outputs al, bl, c1 and a2, b2, c2: and for showing the numeral 3, a '1" signal appears additionally at the outputs gl, dl and g2, d2; and so on. The outputs corresponding to each other, i.e. al and a2; .., gl and g2, at which identical signals occur when operation is correct, are connected to inputs of the OR elements Qa ... Og the output signals of which are fed via lines a' ... g' to one set of inputs of first segment coincidence elements SUa ... SUg, and via inverters SIa ... SIg to the first inputs of second segment coincidence elements SUa ... SUg.

To the outputs of the first segmentcoincidence elements SUa ... SUg there are connected control inputs Sa ... Sg of first segment switches SSa ... SSg. one set of contacts Aa1 ... agl of the latter is connected with one of the poles +SQ of a source of voltage. The other contacts Aa2 ... AgS thereof are connected to first seg- menu lines a ... g to which, via decoupling diodes Dal ... Dan; Dgl ... Dgn; are connected the one set af connections aela ... aelg aena ... aeng of the control elements of the display element AE1 ...

AEn. Between the segment lines a ... g and the earthed negative pole -SQ of the source of voltage are connected quenching diodes LDa LDg.

Thus, with the segment switches SSa SSg closed, the segment coils Al ... G1, An ... Gn are connected to the positive pole +SQ of the source of voltage.

Connected to the second segment coincidence elements SUa ... SUg are the control inputs Sa ... Sg of second segment switches SSa ... SSg. One set of contacts Aal ... Agl of the latter are connected to the negative earthed pole -SQ of the source voltage whereas the other contacts Aa2 ... Ag2 thereof are connected via segment lines a g and decoupling diodes Dal ... Dan and Dgl ... Dgn to the one set of connections aela ... aelg and aena .. aeng of the segment coils Al ... G1 and An ... Gn.

Between the segment lines a ... g and the positive pole +SQ of the source of voltage are ~ arranged quenching diodes LDa LDg. The employment of two segment switches SSa, SSa per segment and the triggering of the second segment switches Spa via inverters SIa ... produces the effect that the segment coils of segments to be displayed can be applied to the positive pole +SQ of the voltage source, and the coils of the segments to be obscured can be applied to the negative pole -SQ of the source of voltage.

For displaying and obscuring the segments (i.e. setting and resetting) it is also necessary that the other connections of the coils Al ... G1; An ... Gn should be suitably connected to the source of voltage. For this purpose there serve address switch units ASE1 ... ASEn each comprising two address switches AS 1k. AS11 ... ASnk.

ASnl. These address switch units are controlled by address decoders ADC1 and ADC2 which decode the contents of the address stores ASP1 and ASP2 in such 'banner that a signal appears at each one of n outputs tk ... nk or 11 ... nl. Thus, an output is associated with each address: in the case of addresses of 4 bits each. 16 outputs may be present. Since. in the case of correct operation, identical addresses are contained in both address stores ASP1 and ASP2, there appear also at the outputs ilk ...

nk of the address decoder ADC1. the same signals as at the outputs 11 ... nl of the address decoder ADC2. Thus. there are in each case two outputs corresponding to each other of the address decoder ADC1 and ADC2. Associated with each display unit AE1 ... AEn is an address, inasmuch as the control inputs of the address switch units ASE1 ... ASEn are connected to outputs (corresponding to each other in each case) of the address decoders ADC1 and ADC2.

For example, the control inputs of the address switch unit ASE1 are connected to the output 1k of the address decoder ADC1 and to the output 11 of the address decoder ADC2. Correspondingly, the address switch unit ASEn is controlled by the outputs nk and nl. The output signals of the address decoder ADC1 are fed to the address switches ASlk ... ASnk, one set of contacts of which is connected to the negative pole -SQ of the source of voltage, whereas the other contacts thereof are connected to connections ael ... aen of the control elements of the display elements AE1 ...

AEn. The second address switches AS11 ...

ASnl, which in the closed condition apply the positive pole +SQ of the voltage source to the second control inputs of the display elements AE1 ... AEn, are controlled by the address decoder ADC2.

Connected between the address decoders ADC1 and ADC2 and the address switch units ASE1 ... ASEn are address coincidence elements Ulk, U11 ... Unk, Unl, of which the coincidence elements Ulk ... Unk are released if also the segment coincidence elements SUa ... SUg are released, and of which the address coincidence elements U11 ... Unl are released if one of the second segment coincidence elements SUa ... SUg receives a release signal. This means that the first segment switches SSa ... SSg can be closed only with the address switches ASlk ... ASnk and the second segment switches SSap ... SSg with the address switches AS11 ... ASnl. In the first case, a current can be sent from the positive pole +SQ of the source of voltage to one set of connections aela ... aeng of the segment coils Al ... G1; An ..Gn and through this to the negative pole -SQ of the voltage source and in the other case in the opposite direction through the segment coils. Due to suitable actuation of the switches, therefore, segnts can be displayed and obscured (set and reset). For this purpose. only one voltage source is necessary.

The segment coincidence elements SUHa .... SUa ... and the address coincidence elements Ulk ...; U11 ... are cyclically freed bv a function control system comprising substantially a clock generator TG, a counter Z and a decoder DEC. The output pulses of the clock generator TG are fed to the counter input ZE of the counter Z. The decoder DEC supplies a "1" signal to one of 16 outputs dcl ... dc16 as a function of the counter state. One set of inputs of the first gate circuits SUa ... SUg are connected to the outputs doc1 ... dc7, the first inputs of the second segment coincidence elements SUa ... SUg are connected to the outputs dc9 dc15 which furthermore are connected with the inputs of an OR element 04 with the output signals of which the address coincidence elements U11 ... Unl are released.

The release signals for the address coincidence element Ulk ... Unk are supplied by an OR element 03 to which the signals appearing at the outputs dcl ... dc8 of the detector DEC are fed.

The transfer pulses of the counter Z are fed to a control unit ST which may be a bistable trigger stage which in one switching condition blocks the decoder DEC and trans mits a request to the data processing unit DVE for transfer of a fresh symbol signal and of an address. and in the other switching condition releases the decoder DEC.

Between the two poles of the source of voltage, expediently at the earthed pole -SQ, there is switched a current measuring resistor RM to which a voltage discriminator DIS is connected. When operation is correct, the amplitudes of the current pulses extracted from the source of voltage are in a pre-determined zone. If the amplitude of a pulse is located outside this zone. the voltage drop thereby changed at the current measuring resistor RM is detected by the discriminator DIS and the latter supplies a signal via a line ML1. The discriminator DIS triggers furthermore a logic circuit LOG which at those times at which a pulse is to occur receives a clock pulse t'ia a line T2 and switches the discriminator signal through to a testing counter PZ. Due to the separate triggering of the display elements AEI ...

AEn, during a triggering cycle a predetermined number of pulses must be taken from the source of voltage. This number is stored in a store SP. After conclusion of a triggering cycle. there is fed to a comparator VGL, which compares the state of the testing counter PZ with the content of the store SP, a signal z-ia a line T3. for example from the control unit ST. If the two values do not correspond, the comparator VGL supplies a disturbance signal i'ia a line ML2.

Hereinafter, with reference to the pulse diagrams of Figure 3, the operation of the arrangement according to Figure 1 is discussed. It is assumed that the display element AE1 is to show the numeral 3. The function control is in that condition in which the state of the counter Z (line z in Figure 3) is l and the control unit ST (line st in Figure 3) supplies a request pulse to the data processing unit DVE and a clock pulse Isia the line T3 to the comparator VGL. Thereupon. the data processing unit DVE (line dvc in Figure 3) makes ready a symbol signal and an address which are read into the symbol stores ZSP1 and ZSP2 and also the address stores ASP1 and ASP2. During this. the counter Z counts the pulses of the pulse generator TG fed to its input ZE. After reaching the counter state 16. it transmits an overrun pulse in response to which the control unit ST frees the decoder DEC.

Therewith, a first phase I of the triggering cycle is concluded and a second phase ll, in which the segments are displayed and obscured (set and reset) is initiated.

The lines as, bs .. gs of Figure 3 show the current flow in the segment coils of the selected display element AEl. In a "1" signal at the output dc7 the segment switch SSg is closed, since the symbol decoder ZDC1 and ZDC2 supply "1" signals to the lines gl and g2; the current flow gs is positive. In a phase IIa of the triggering cycle, therefore, the segments A, B, C, D and G are set, these being required to be set for showing the numeral 3.

The segments E and F, which must not be set for showing the numeral 3, are still in the position in which they were at the commencement of the triggering cycle. They are reset in a second component phase llb. The output dc8 of the decoder DEC is connected with no segment coincidence element SUa ... or SUa ... If a "1" signal appears at it, none of the segment elements is released, the segment switches are open. If, however, a "1" signal appears at output dc9, this is fed via the OR element 04 to the address coincidence element U11 ... Unl. of which the coincidence element Ull furthermore receives a "1" signal via the line 11 from the address decoder ADC2, and therefore closes the address switch AS11 which, during the entire phase Ila, (cf. diagram asl in Figure 3) remains closed. Furthermore, the segment coincidence element SUa receives a "1" signal. The output signal thereof is.

however, zero, since the symbol decoders ZDC1 and ZDC2 supply to the line a' a "I" signal which is inverted by the segment inverter SIa and therefore blocks the segment coincidence element SUa. Thus. the segment switch SSa controlled thereby remains open; the current flow as through the segment coil Al is zero at count 9.

Correspondingly, also in the case of the counts 10, 11 and 12 the current flows bs, cs and ds through the segment coils B1. Cl and D1 are zero. The segments A. B. C and D set in the first phase IIa therefore remain set.

The "0" signals present at the lines e' and f' (not shown) free, after the invertion, segment coincidence elements which corres pond to the coincidence elements SUa and SUg; therewith, switches corresponding to the switches SSa and SSg are closed and there flow one after the other during the times at which a "1" signal is present at the outputs dc12 and dc13 of the decoder DEC, currents from the positive pole +SQ via the address switch AS11, the segment coils El and F1 (not shown), decoupling diodes and segment switches, and also the current measuring resistor RM to the negative pole -SQ of the source of voltage. The currents es and fs (see Figure 3) through the segment coils El and F1 are directed oppositely to those currents which previously in phase Ila flowed through the other segment coils.

Thus, the segments E and F are or remain reset.

If the counter Z reaches the count 16 then, as in the case of the count 8, none of the segment coincidence elements is triggered and all the segment switches are open.

On shutting off the currents through the segment coils Al, B1, C1. D1 and Gl, the quenching diodes LDa ... LDg become effective. and on shutting-off the currents through the segment coils El and F1 and the quenching diodes LDe and LDf (not shown) become effective.

In the case of the example of embodiment, there are connected to the outputs doc1 ... dc8 and to dc9 ... dc16 or element 03 and 04 respectively. These can be dispensed with. if the counter Z is a binary counter and the address coincidence elements U l k . . .

Unk and Ull ... Unl are directly connected to the two inverse outputs of the fourth stage of the counter Z.

On reaching the count 16, the triggering cycle is concluded. The control unit ST is set and thereupon the blocks the decoder DEC and supplies a testing signal to lines T2 and T3. From the diagrams as. bs ... gs of Figure 3 it is apparent that the testing counter connected to the current measuring resistor RM must receive seven pulses per triggering cycle. In the case of the showing of numeral 3. five pulses were produced during the phase lla, in which the segments A, B, C, D and G were triggered with setting pulses, and two pulses during phase llb in which the segments E and F received reset pulses. In the showing of each numeral, a total of seven pulses must be summed-up, independently of how many segments have been changed-over. With the pulse on the line T3. it is tested whether the numeral 7 is in the testing counter. If this is not the case, an error signal is supplied to the line ML2. If no error is detected, the control unit ST supplies to the data processing unit DVE a request signal to issue the next symbol signal and the address of the display element with which the next numeral is to be shown.

The numerals may be issued by the data processing unit DVE cyclically one after the other, to correspond to their values. In this case. the display units AEl ... AEn would be continuously triggered one after the other in order. If varying multi-digit numerals are to be displayed, for example at petrol stations during the supply of petrol, the quantity dispensed in each particular instance and the associated price, then expediently the display elements at the higher order positions in the multi-digit numeral are triggered with a lower frequency than are the display elements at the lower order positions. In this manner the frequency of variation of the display is adapted to the frequency with which the multi-digit numeral to be indicated varies in the individual locations. Clearly the lower the order of the numeral position, the higher the frequency at which it will change. Moreover, it is senseless to trigger the display elements with a frequency so high that an observer is no longer able to follow the changes. In this case, the display elements would be unnecessarily worn. Triggering of the individual display elements is therefore restricted to a frequency at which an observer can still detect the individual values indicated.

The arrangement according to Figure 1 is intended to serve for triggering display elements in a secure manner, i.e. errors of the arrangement and also of pre-connected units, such as transfer sections, are to be detected. An error may occur in one of the two symbol signals which are recorded by the data processing unit DVE in the two symbol stores ZSP1 and ZSP2, whether during transfer, on storage or on decoding or in switching elements connected sequentially of the decoders ZDC1 and ZDC2. In this case the segment switches SSa. SSa are during the two phases of the pulse signal supplied to the line T1 varying opened or closed, so that the addressed display element during the two phases shows two different numerals whereof one is the correct numeral and the other a false or meaningless symbol. Since the two numerals are alternatingly shown with a frequency of for example 1 c/s. the error is readily recognisable. A separate fault signal, for example lighting up of a lamp or the like, need not be observed.

Errors during dispensing, transfer or during storage of the addresses have the result that in the address stores ASP1 and ASP2 there are differing addresses and that output lines 1k ... nk, 11 ... nl which do not correspond to each other are provided with a "1" signal. For example if the display element AE1 is to be triggered. the output line 1k and the output line nl mayh carry "1" signals, so that two address coincidence elements not belonging to a display element, in the example the coincidence elements Ulk and Unl are released. During the component phase IIa. the address switch ASlk and during the component phase IIb the address switch ASnl is closed, so that in display element AE1 segments are only set and in display element AEn reset. The element AEn is addressed once again at each control cycle, so that it shows cyclically two numerals or one numeral and a mean ingless symbol, from which the error can be recognised. Correspondingly, also errors of one of the decoders, for exaple the con tinuous issue of "0" signals, are detected by the comparator VGL in that the test counter PZ does not in a triggering cycle of a display element reach the number contained in the store SP. The simultaneous issue of two "1" signals causes the discriminator DIS to respond, since in such a case two segment coils are connected in parallel and current pulses of approximately double amplitude are extracted from the source of voltage.

For changing over the segments, relatively strong currents are necessary such as cannot be supplied by commercially conventional integrated semiconductor circuits. the output circuits of the segment switches SSa, SSa ... and ASEI ..., which are semiconductors, are therefore formed as power stages.

From the diagrams as, bs ... of Figure 3, it is clear that the power stages are triggered one after the other, so that a uniform, low, current is extracted from the source of voltage.

From the data processing unit, also in times in which no fresh numbers are to be issued, code signals are continuously transferred and shown as symbols. In this manner, the functioning of the arrangement is always tested, the segments not being switched when there is a lack of error and therefore not being worn.

The illustrated and described embodiment provides a circuit arrangement for the controlled triggering of display units, which is distinguished by slight expenditure, reliable fault detection, high operational reliability, and conspicuous fault reporting.

WHAT WE CLAIM IS: 1. Circuit arrangement for displaying symbols, comprising a display unit and a data processing unit arranged to supply signals representing the symbols to be displayed, there being symbol storage connected between the data processing unit and the display unit and comprising a plurality of storage locations for storing what, in correct operation of the arrangement, will be the same symbol at any one time, the arrangement being such that in operation thereof a symbol display position of the display unit will receive contents from one after another of said storage locations.

2. Circuit arrangement according to claim 1. which is such that the frequency at which the display unit will receive contents from one after another of said storage locations is a low frequency.

3. Circuit arrangement according to claim 2, wherein said frequency is of the order of 1 c/s.

4. Circuit arrangement according to claim 1. 2 or 3, wherein the data processing unit is arranged to supply coded signals to the symbol storage, and decoder means are connected between the symbol storage and the display unit.

5. Circuit arrangement according to any one of the preceding claims, wherein the display unit comprises at least one display region comprising a plurality of segments adapted to be set and reset, the segments being arranged such that the display region

**WARNING** end of DESC field may overlap start of CLMS **.

Claims

**WARNING** start of CLMS field may overlap end of DESC **. at which it will change. Moreover, it is senseless to trigger the display elements with a frequency so high that an observer is no longer able to follow the changes. In this case, the display elements would be unnecessarily worn. Triggering of the individual display elements is therefore restricted to a frequency at which an observer can still detect the individual values indicated. The arrangement according to Figure 1 is intended to serve for triggering display elements in a secure manner, i.e. errors of the arrangement and also of pre-connected units, such as transfer sections, are to be detected. An error may occur in one of the two symbol signals which are recorded by the data processing unit DVE in the two symbol stores ZSP1 and ZSP2, whether during transfer, on storage or on decoding or in switching elements connected sequentially of the decoders ZDC1 and ZDC2. In this case the segment switches SSa. SSa are during the two phases of the pulse signal supplied to the line T1 varying opened or closed, so that the addressed display element during the two phases shows two different numerals whereof one is the correct numeral and the other a false or meaningless symbol. Since the two numerals are alternatingly shown with a frequency of for example 1 c/s. the error is readily recognisable. A separate fault signal, for example lighting up of a lamp or the like, need not be observed. Errors during dispensing, transfer or during storage of the addresses have the result that in the address stores ASP1 and ASP2 there are differing addresses and that output lines 1k ... nk, 11 ... nl which do not correspond to each other are provided with a "1" signal. For example if the display element AE1 is to be triggered. the output line 1k and the output line nl mayh carry "1" signals, so that two address coincidence elements not belonging to a display element, in the example the coincidence elements Ulk and Unl are released. During the component phase IIa. the address switch ASlk and during the component phase IIb the address switch ASnl is closed, so that in display element AE1 segments are only set and in display element AEn reset. The element AEn is addressed once again at each control cycle, so that it shows cyclically two numerals or one numeral and a mean ingless symbol, from which the error can be recognised. Correspondingly, also errors of one of the decoders, for exaple the con tinuous issue of "0" signals, are detected by the comparator VGL in that the test counter PZ does not in a triggering cycle of a display element reach the number contained in the store SP. The simultaneous issue of two "1" signals causes the discriminator DIS to respond, since in such a case two segment coils are connected in parallel and current pulses of approximately double amplitude are extracted from the source of voltage. For changing over the segments, relatively strong currents are necessary such as cannot be supplied by commercially conventional integrated semiconductor circuits. the output circuits of the segment switches SSa, SSa ... and ASEI ..., which are semiconductors, are therefore formed as power stages. From the diagrams as, bs ... of Figure 3, it is clear that the power stages are triggered one after the other, so that a uniform, low, current is extracted from the source of voltage. From the data processing unit, also in times in which no fresh numbers are to be issued, code signals are continuously transferred and shown as symbols. In this manner, the functioning of the arrangement is always tested, the segments not being switched when there is a lack of error and therefore not being worn. The illustrated and described embodiment provides a circuit arrangement for the controlled triggering of display units, which is distinguished by slight expenditure, reliable fault detection, high operational reliability, and conspicuous fault reporting. WHAT WE CLAIM IS:

1. Circuit arrangement for displaying symbols, comprising a display unit and a data processing unit arranged to supply signals representing the symbols to be displayed, there being symbol storage connected between the data processing unit and the display unit and comprising a plurality of storage locations for storing what, in correct operation of the arrangement, will be the same symbol at any one time, the arrangement being such that in operation thereof a symbol display position of the display unit will receive contents from one after another of said storage locations.

can display any one of a plurality of symbols in dependence upon how the segments are set and reset.

6. Circuit arrangement according to claim 5, and comprising logic circuitry between said symbol storage locations and the display unit and control means for said logic circuitry operable such that in said display region and the segments will be set or reset one after another in dependence upon the symbol to be displayed.

7. Circuit arrangement according to claim 6, wherein corresponding outputs of the respective storage locations are logically associated in each. case by an OR element coupled to a first segment coincidence ele event, and via an inverter to a second segment coincidence element associated with the same segment, the segment coincidence element for all the segments being arranged to be released one after the other by said control means, there being connected to the first segment coincidence elements the control inputs of first segment switches the first contacts of which are for connection to one pole of a source of voltage; and to the second segment coincidence elements there are connected the control inputs of second segment switches the first contacts of which are for connection to the other pole of the source of voltage, there being connected to the second contacts of the segment switches in each case a connection associated with a segment of the display region.

8. Circuit arrangement according to claim 5, or claim 6 or 7 when appended to claim 5, wherein the display unit comprises a plurality of display regions each of which comprises a plurality of segments and each of which is associated with addressing means operable in dependence upon the data processing unit.

9. Circuit arrangement according to claim 8 when appended to claim 7, wherein the addressing means of each display region comprises two address switches for connecting an opposite connection associated with the segments of the display region to the opposite pole of said source of voltage when one of the first segment coincidence elements is released, and to said one pole of said source of voltage when one of the second segment coincidence elements is released, thereby to provide two phases in the operation of the or each display region: a phase in which only setting signals are supplied, and a phase in which only resetting signals are supplied.

10. Circuit arrangement according to claim 8, or claim 8 or 9 when appended to claim 7, wherein inductive resistance is associated with the display regions and there are quenching elements connected to the second contacts of the segment switches.

11. Circuit arrangement according to claim 7, or claim 8, 9 or 10 when appended to claim 7, wherein the connections associated with a segment of the display region are coupled to said second contacts of the segment switches via decoupling diodes.

12. Circuit arrangement according to claim 8, or any one of claims 9 to 11 when appended to claim 8, wherein said addressing means comprises two address stores in common for the display regions, the arrangement being such that in correct operation each of said address stores at any one instant in time contains the address of the display region in which the setting or resetting or segments is being carried out, each display region is associated with a particular output of each of the two address stores, and the output signals from each such pair of outputs of the two address stores are fed in alternation to the display unit.

13. Circuit arrangement according to claim 12 when appended to claim 9, wherein in said each such pair of outputs one of the outputs is associated with one of the two address switches of the associated display region. and the other of the outputs is associated with the other of these two address switches.

14. Circuit arrangement according to claim 7, or any one of claims 8 to 13 when appended to claim 7, wherein the or each display region comprises n segments and said control means comprises 2n outputs to which it is arranged to apply release signals cyclically, one half of the 2n outputs being connected to respective ones of said first segment coincidence elements and the other half of the 2n outputs being connected to respective ones of said second segment coincidence elements.

15. Circuit arrangement according to claim 13. or claim 14 when appended to claim 13, wherein in said each such pair of outputs the one output is associated with said one address switch by means of a first address coincidence element controlled in dependence upon said control means, and the other output is associated with said other address switch by means of a second address coincidence element controlled in dependence upon said control means.

16. Circuit arrangement according to claims 14 and 15. wherein said one half of the 2n outputs of the control means are coupled to an OR gate which controls the first address coincidence elements, and said other half of the 2n outputs of the control means are coupled to a further OR gate which controls the second address coincidence elements, these OR gates providing that said output signals from said each such pair of outputs of the two address stores are fed in alternation to the display unit.

17. Circuit arrangement according to claim 15, wherein the first and second address coincidence elements are controlled by an output stage of a counter comprised in said control means.

18. Circuit arrangement according to claim 6, or any one of claims 7 to 17 when appended to claim 6, wherein said control means is arranged to supply, after each triggering cycle of a display region, a request to the data processing unit for transfer of a symbol signal and, where applicable, an address.

19. Circuit arrangement according to claim 7, or any one of claims 8 to 18 when appended to claim 7, and comprising for connection between the two poles of the source of voltage a current measuring resistor which is connected to detect the current employed in setting or resetting the segments.

20. Circuit arrangement according to claim 19, and comprising a voltage discriminator connected to the current measuring resistor for supplying an error signal if the strength of the current supplied by the voltage source is outside a predetermined range.

21. Circuit arrangement according to claim 19 or 20, and comprising a testing counter arranged to count the pulses occurring during predetermined phases of the triggering of a display region at the current measuring resistor, and a comparator to compare the counter result with a desired value.

22. Circuit arrangement according to claim 8, or any one of claims 9 to 21 when appended to claim 8, which is arranged such that the display regions are to display respective digits of multi-digit number, and such that the symbols and addresses from the data processing unit for the higher order display regions are to be entered into the symbol storage at a lower frequency than are the symbols and addresses for the lower order display regions.

23. Circuit arrangement according to any one of the preceding claims, which is arranged such that no symbol at the display unit will change at a frequency which is so great that the individual symbols cannot be discerned bv a human observer.

24. Circuit arrangement according to claim 23, which is arranged such that no symbol at the display unit will change at a frequency higher than 10 times per second.

25. Circuit arrangement according to any one of the preceding claims, wherein the data processing unit has a plurality of data storage zones in which, in each case, the same data are to be stored, and a plurality of programme storage zones in which there are contained programmes which, on processing identical data. will lead to the same results, and in that for producing the symbol signals and, where applicable, the addresses, each programme is executed with the data associated with it.

26. Circuit arrangement according to claim 25, wherein the programmes which, on processing identical data, will lead to the same result, one different from one another.

27. Circuit arrangement according to any one of the preceding claims, wherein the data processing unit is a micro-processor having a word width of 8 bits which, in the case of correct operation, supplies in each case two identical symbol signals each of 4 bits to two symbols stores each of 4 bit capacity.

28. Circuit arrangement according to claim 27 when appended either directly or indirectly to claim 12, wherein in the case of correct operation the micro-processor supplies in each case two identical address signals each of 4 bits to the two address stores each of 4 bit capacity.

29. Circuit arrangement for displaying symbols, substantially as hereinbefore described with reference to Figure 1 of accompanying drawings.