GB1526105A - Pneumatic logic unit - Google Patents

Abstract

1526105 Pneumatic logic unit FOXBORO CO 28 Jan 1976 [14 Feb 1975] 3270/76 Heading G4P A pneumatic logic unit is formed of several parts assembled in a stack. The parts include a flexible diaphragm 32 and two spacer elements 26, 28 retaining the diaphragm and forming two chambers 74, 76 one on either side of the diaphragm. Two further diaphragms are situated between a respective spacer and a body 22, 24 and one end of the unit is closed by a sealing jacket 40 and a top plate 38. The bottom end of the unit has two gaskets 44, 46 and a restrictor plate 42 and is secured to a two-layer circuit board 52 providing conduits supplying the unit and interconnecting units. The parts of the stack have aligned openings through which bolts pass to secure the parts to each other and to the board and have aligned openings forming conduits 60, 62, 64, 66. Conduits 60, 62 form control lines b, a. Conduit 60 is connected via slot 70 in spacer 26 to chamber 74. Conduit 62 is connected via slot 72 in spacer 28 to chamber 76. Conduit 64 connected to line 2 is coupled via channels 116, 120 in body 24 to a chamber 112. Conduit 66 is connected via channels 118, 115 in body 22 to a chamber 110. Bodies 22, 24 contain nozzles 94, 96 which can be selectively closed by valve stems 86, 88 coupled to diaphragm 32. Nozzle 92 is coupled to line 1. Nozzle 94 is coupled either to an outlet 99 or by channel 102 in gasket 40 to conduit 64. To perform logic functions, e.g. as an AND gate, Fig. 3H, the input signals X, Y are fed to lines a, 1 and line 3 is vented. The diaphragm is biased so that nozzle 92 is closed and nozzle 94 is open and thus line 4 conduit 66 is connected to line 3 and outlet 99 via chamber 110. If an X signal is applied via line a conduit 62 pressure is supplied to chamber 76 and the diaphragm moves to open nozzle 92 and close nozzle 94. Lines 1 and 2 are then coupled. If a Y signal is applied a "1" exists on the output. If the Y signal is applied to line 3 and a "1" signal to line 1 an OR gate is formed (Fig. 31, not shown). A bistable circuit, a one shot circuit, a NOT circuit and a compare circuit are described.