GB1525009A - Lsi semiconductor devices - Google Patents

Lsi semiconductor devices

Info

Publication number
GB1525009A
GB1525009A GB4696875A GB4696875A GB1525009A GB 1525009 A GB1525009 A GB 1525009A GB 4696875 A GB4696875 A GB 4696875A GB 4696875 A GB4696875 A GB 4696875A GB 1525009 A GB1525009 A GB 1525009A
Authority
GB
United Kingdom
Prior art keywords
data
array
inputs
output
terminals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB4696875A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US05/534,608 external-priority patent/US3961254A/en
Priority claimed from US05/534,605 external-priority patent/US3961251A/en
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of GB1525009A publication Critical patent/GB1525009A/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/48—Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)

Abstract

1525009 Memory system INTERNATIONAL BUSINESS MACHINES CORP 14 Nov 1975 [20 Dec 1974 (2)] 46968/75 Heading G4A A large scale integrated circuit device, e.g. a memory, includes a main circuit unit (the memory array) normally accessed from terminals on the device through auxiliary circuitry (associated logic circuits, decoders, &c.) and a by-pass mechanism operative so that the main circuit unit can be assessed directly from terminals on the device for test purposes. Two embodiments are described. In the first the integrated circuit includes a main memory array 15 incorporating switchable gates 19, 20, 21 responsive to control signals ATL, ITL, OTL fed in via device inputs selectively to connect address and data inputs to the array and data outputs from the array directly to terminals on the device and to associated logic units, decoders, &c. 12, 13, 14 which receive their inputs from terminals on the device. In normal operation the logic circuits are used to transfer inputs to the memory array in accordance with the design of the device. However for test purposes the array may be tested in isolation by feeding it data direct. Subsequently the various logic circuits may be tested by the appropriate choice of direct and normal input/output routes. In the second embodiment the array includes address, data input, and data output registers which may be clocked to receive data via the associated logic circuits. The data and address registers are formed as master/slave shift registers and may be clocked to receive data serially direct from and send data serially direct to external inputs and outputs of the device. The data output register may be connected to feed data directly to a comparator where it is compared with the expected output and to a shift register which is arranged to receive complementary output signals. The arrangement allows operation of the address and data input registers to be checked individually and the memory array itself to be checked by comparing the output with that exepcted.
GB4696875A 1974-12-20 1975-11-14 Lsi semiconductor devices Expired GB1525009A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US05/534,608 US3961254A (en) 1974-12-20 1974-12-20 Testing embedded arrays
US05/534,605 US3961251A (en) 1974-12-20 1974-12-20 Testing embedded arrays

Publications (1)

Publication Number Publication Date
GB1525009A true GB1525009A (en) 1978-09-20

Family

ID=27064528

Family Applications (1)

Application Number Title Priority Date Filing Date
GB4696875A Expired GB1525009A (en) 1974-12-20 1975-11-14 Lsi semiconductor devices

Country Status (2)

Country Link
JP (1) JPS5184530A (en)
GB (1) GB1525009A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2137785A (en) * 1983-04-04 1984-10-10 Oki Electric Ind Co Ltd Semiconductor memory device

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5525109A (en) * 1978-08-09 1980-02-22 Fujitsu Ltd Logic circuit
JPS5614357A (en) * 1979-07-16 1981-02-12 Matsushita Electric Ind Co Ltd Diagnostic control unit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2137785A (en) * 1983-04-04 1984-10-10 Oki Electric Ind Co Ltd Semiconductor memory device

Also Published As

Publication number Publication date
JPS5184530A (en) 1976-07-23
JPS5415650B2 (en) 1979-06-16

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Legal Events

Date Code Title Description
PS Patent sealed
PCNP Patent ceased through non-payment of renewal fee