GB1513960A - Apparatus for reading coded information - Google Patents

Abstract

1513960 Card sensors WESTERN ELECTRIC CO INC 31 July 1975 [2 Aug 1974 (2) 27 Feb 1975] 31988/75 Heading G4M A reader for self clocking binary signals has two spaced read heads feeding circuitry deriving clock and data pulses from the signals. The data may be bar codes or magnetic signals on credit cards with the data arranged in cells having a transition at cell boundaries and a transition in the cell for e.g. a '1' and no transition for e.g. a '0'. In one embodiment (Fig. 8) the heads are spaced by ¢ cell width, and the data is magnetically recorded. The heads feed separate amplifiers 66, 67 the outputs of which feed OR gate 68 and AND gate 70. Each transition at a cell boundary and in the centre of a '1' cell produces a pulse to form train 530 from the leadin7 head and 531 from the trailing head. The pulses from OR gate 68 alternately set and reset flip-flop 71 to produce clock signals V81 at its output. AND gate 70 passes a pulse only when pulses coincide in trains 530, 531 and V81 and this only happens at each '1' pulse in train 31. The read head contains a plurality of magneto resistive elements 30a, 30b, 31a, 31b joined by conducting elements 40a, 40b, 41a, 41b. The length of the series of elements 30, 31 is arranged to correspond to the width of the track to be read. If the card carries two or more parallel tracks then further sensors 30<SP>1</SP>, 31<SP>3</SP> are provided offset from the first sensors to correspond to the track position. The spacing between the further sensors may be changed if the cells in the second or further tracks have different widths C1, C2. If the card has visible marks (Fig. 18C) spaced optical read heads produce signals (Figs. 18A, Figs. 18D) as shown spaced by one cell. The cells feed an Exclusive NOR gate 52 producing a signal (Fig. 18E) only when the two inserts differ and the trailing head feeds a transition detector 57 produces pulses (Fig. 18G) at each black/white or white/black transition. The pulses are fed to AND gate 58 receiving the Q output of flip-flop 53 to remove the pulses corresponding to the '1' transitions. The clock signals are inverted and used to clock the flip-flop to produce an output signal (Fig. 18F). The spacing of the read heads may be n non- integral or an integral multiple of the cell width. A shift register storing the values of cells occurring between the read heads is required (Figs. 20, 22, not shown) and a logic circuit determining how many '1's are stored in the cells is used to determine the values of succeeding cells.