GB1510588A - Sequential computing system - Google Patents
Sequential computing systemInfo
- Publication number
- GB1510588A GB1510588A GB22419/76A GB2241976A GB1510588A GB 1510588 A GB1510588 A GB 1510588A GB 22419/76 A GB22419/76 A GB 22419/76A GB 2241976 A GB2241976 A GB 2241976A GB 1510588 A GB1510588 A GB 1510588A
- Authority
- GB
- United Kingdom
- Prior art keywords
- register
- computer
- output
- gate
- matrix
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/3001—Arithmetic instructions
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/10—Program control for peripheral devices
- G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
- G06F13/124—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/22—Microcontrol or microprogram arrangements
- G06F9/226—Microinstruction function, e.g. input/output microinstruction; diagnostic microinstruction; microinstruction format
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/22—Microcontrol or microprogram arrangements
- G06F9/26—Address formation of the next micro-instruction ; Microprogram storage or retrieval arrangements
- G06F9/262—Arrangements for next microinstruction selection
- G06F9/264—Microinstruction selection based on results of processing
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/448—Execution paradigms, e.g. implementations of programming paradigms
- G06F9/4482—Procedural
- G06F9/4484—Executing subprograms
Abstract
1510588 Data processing J M POLSKY V P ZAKHAROV N T GOLETS J V TAYAKIN G P LIPOVETSKY V V PROTSENKO A D KHOMENKO V P SIDORENKO A Y SIROTA J V PROKOFIEV and A M KOPYTOV 28 May 1976 [2 June 1975 28 July 1975 15 March 1976 (10)] 22419/76 Heading G4A Data circulating in serially-connected registers 2 1 -2 n is processed by an adder 6 and gates controlled by a microinstruction matrix 10, timing signals being provided by three counters 33, 34, 35 acting as frequency dividers. To replace a digit by zero gate 24 temporarily disconnects register 2 1 from register 2 n . To move a digit one place to the right gate 26 temporarily connects the input of register 2 1 to the output of register 2 m . To move a digit to the left it is transferred from register 2 n via gate 4, adder 6, and gate 12 to an accumulator register 11 in which it is circulated via gate 13 until it is replaced in the data circulating in registers 2 1 -2 n via gate 25 and register 2 1 . The carry output of the adder 6 is stored in a register 19 the contents of which are circulated via a gate 20 and indicate whether a program jump is to take place. The result of the processing is provided via a matrix 80 to outputs 81. An address counter 38, receiving the output of an address register 74 and control signals from a control unit 42, provides an address to a program matrix 27 the output of which contains an address in a matrix 32 which provides addresses to the microinstruction matrix 10, a code which, via a circuit 70, modifies the addresses supplied from matrix 32 to matrix 10, a rear instruction address code, a code which causes a signal at output 87 of a circuit 29 to modify the operations of certain of the gates, and a jump condition code. External information is received from an input 69 and supplied to registers 66 1 -66 p whose output is selectively connectible via a gate 68 to adder 6 or via gate 67 to an output 65, a flip-flop 89 producing a control signal when external information is received. For operation with binary-coded decimal numbers constants 0110 and 1010 are formed by circuits 53 and 55 respectively. A plurality of such computers may be connected together (Fig. 2, not shown) the output 48 connected to counter 35 of the first computer being connected to the inputs 46 connected to counters 33 of the other computers, the output 65 of all but the first computer being connected to the input 69 of the preceding computer and the output 65 of the first computer being connected via external register to the input 69 of the last computer so that all the registers 66 1 -66 p1 the gates 67 and the external registers are connected in a closed loop. The code of the computer which is to continue calculations and the initial program address in that computer are inserted into this loop by a computer completing a calculation. All the computers are interrupted to determine the computer code in the closed loop. The computer whose code is in the closed loop passes the initial program address to registers 2 1 -2 n and then from register 2 k via control unit 42 to address counter 38. One of the computers may control all the other computers.
Applications Claiming Priority (12)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
SU752135163A SU532295A1 (en) | 1975-06-02 | 1975-06-02 | Consecutive digital computer |
SU752157301A SU547970A1 (en) | 1975-07-28 | 1975-07-28 | Output device at TIR transistors |
SU762327006A SU678485A2 (en) | 1976-03-15 | 1976-03-15 | Series-action digital electronic computer |
SU762327011A SU654948A2 (en) | 1976-03-15 | 1976-03-15 | Digital electronic series-acting computer |
SU2327010 | 1976-03-15 | ||
SU2327009 | 1976-03-15 | ||
SU762327005A SU658564A2 (en) | 1976-03-15 | 1976-03-15 | Series-action digital electronic computer |
SU762327008A SU591076A1 (en) | 1976-03-15 | 1976-03-15 | Electronic digital serial computer |
SU762327007A SU678486A2 (en) | 1976-03-15 | 1976-03-15 | Series-action digital electronic computer |
SU762327014A SU602950A1 (en) | 1976-03-15 | 1976-03-15 | Serial-action computing system |
SU2327012 | 1976-03-15 | ||
SU762327013A SU591960A1 (en) | 1976-03-15 | 1976-03-15 | Sampling device for metal-insulator-semiconductor transistor storages |
Publications (1)
Publication Number | Publication Date |
---|---|
GB1510588A true GB1510588A (en) | 1978-05-10 |
Family
ID=27583578
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB22419/76A Expired GB1510588A (en) | 1975-06-02 | 1976-05-28 | Sequential computing system |
Country Status (6)
Country | Link |
---|---|
CA (1) | CA1067620A (en) |
DE (1) | DE2624764A1 (en) |
FR (1) | FR2313711A1 (en) |
GB (1) | GB1510588A (en) |
IT (1) | IT1063000B (en) |
NL (1) | NL7605919A (en) |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
BE759025A (en) * | 1969-11-18 | 1971-04-30 | Traitement De L Information Et | |
JPS5036542B1 (en) * | 1969-12-15 | 1975-11-26 |
-
1976
- 1976-05-28 GB GB22419/76A patent/GB1510588A/en not_active Expired
- 1976-06-01 CA CA253,791A patent/CA1067620A/en not_active Expired
- 1976-06-02 NL NL7605919A patent/NL7605919A/en not_active Application Discontinuation
- 1976-06-02 FR FR7616672A patent/FR2313711A1/en active Granted
- 1976-06-02 DE DE19762624764 patent/DE2624764A1/en not_active Withdrawn
- 1976-06-03 IT IT23909A/76A patent/IT1063000B/en active
Also Published As
Publication number | Publication date |
---|---|
FR2313711B1 (en) | 1979-06-01 |
CA1067620A (en) | 1979-12-04 |
IT1063000B (en) | 1985-02-11 |
DE2624764A1 (en) | 1976-12-16 |
FR2313711A1 (en) | 1976-12-31 |
NL7605919A (en) | 1976-12-06 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PS | Patent sealed | ||
PCNP | Patent ceased through non-payment of renewal fee |