GB1504116A - Television display apparatus circuit arrangements - Google Patents

Abstract

1504116 Line deflection circuit MULLARD Ltd 25 Feb 1975 [1 April 1974] 43720/77 Divided out of 1503666 Heading H3T [Also in Division H2] A circuit arrangement for television display includes a switched mode power supply and a line deflection circuit, the power supply comprising a capacitor C3 and the series arrangement of a first switch T1 and a first inductor L1 and the deflection circuit comprising a line deflection coil L3 and the series arrangement of a second switch T2 and a second inductor L2, both series arrangements being connected in series between terminals 1, 2 for connection to a source of direct voltage. The first switch T1 is switched at line frequency or an integral multiple or submultiple thereof to produce a charge on the capacitor C3 which then acts as a source of direct voltage for the line deflection circuit. The first inductor L1 is timed so that during each period when the first switch is off the voltage at the junction of the first switch and first inductor performs a half sinewave at a first frequency which occupies the non-conducting period, the second switch is operated at line frequency to provide current to the deflection coil L3 in scan periods and to be off during the flyback periods. The line deflection circuit is tuned so that during the flyback period, when the second switch is off, the voltage at the junction between the switch and the second inductor performs a half sinewave at a second frequency which occupies the flyback period. The first and second inductors are not tightly coupled so allowing the two switches to be switched asynchronously. The inductors may be loosely coupled inductively, and part of the current flowing in part of the scan period in the deflection coil is provided by current flowing in the second inductor, induced there by current in the first inductor. The first inductor may be tuned by the reflected impedance of the tuned circuit associated with the second inductor. A transductor TR1 may be connected in parallel with the first inductor L1, and controlled by a voltage present in, or derived from, the arrangement to stabilize a second voltage in the arrangement which may have the same value as the first. Alternatively stabilization may be obtained by varying the time at which the first switch T 1 is turned off relative to the time that the second switch T2 is turned off, this may be obtained by turning them off by alternate edges of a pulse train whose mark-space ratio is varied. The second inductor may be connected as shown between the two switches. Preferably the first switch is turned off at the start of the flyback period. The inductors may be wound on the opposite limbs of a line transformer. The switches may be transistors, thyristors or gate turn-off switches, but since the currents must flow in each direction through the switches diodes (not shown) may be needed in parallel with these devices. The deflection circuitry T2, C2, C4, L3 may be conventional in design. As shown, a square wave switching waveform is generated 20 and applied via a transistor T3 to a transformer whose secondaries drive the transistors T1, T2 by suitably connecting the windings, the transistors are operated on the same or on opposite edges of the waveforms. To equalize switching delays in turning the transistors T1, T2 off, due to hole storage, inductors L4, L5 are provided; a common core may vary their inductance in opposite senses. The position of a mark-space modulator 21 is shown by the dotted lines.