GB1494750A - Data processing system with hash instruction - Google Patents
Data processing system with hash instructionInfo
- Publication number
- GB1494750A GB1494750A GB53774/74A GB5377474A GB1494750A GB 1494750 A GB1494750 A GB 1494750A GB 53774/74 A GB53774/74 A GB 53774/74A GB 5377474 A GB5377474 A GB 5377474A GB 1494750 A GB1494750 A GB 1494750A
- Authority
- GB
- United Kingdom
- Prior art keywords
- register
- instruction
- address
- operand
- bits
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000000034 method Methods 0.000 abstract 3
- 238000006073 displacement reaction Methods 0.000 abstract 2
- 238000013523 data management Methods 0.000 abstract 1
- 239000004065 semiconductor Substances 0.000 abstract 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F16/00—Information retrieval; Database structures therefor; File system structures therefor
- G06F16/90—Details of database functions independent of the retrieved data types
- G06F16/901—Indexing; Data structures therefor; Storage structures
- G06F16/9024—Graphs; Linked lists
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/30018—Bit or string instructions
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
- G06F9/3016—Decoding the operand specifier, e.g. specifier format
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30181—Instruction operation extension or modification
- G06F9/30192—Instruction operation extension or modification according to data descriptor, e.g. dynamic data typing
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Software Systems (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Databases & Information Systems (AREA)
- Data Mining & Analysis (AREA)
- Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
- Memory System Of A Hierarchy Structure (AREA)
- Executing Machine-Instructions (AREA)
Abstract
1494750 Data processing HONEYWELL INFORMATION SYSTEMS Inc 12 Dec 1974 [13 Dec 1973] 53774/74 Heading G4A In a data processing system a hash instruction results in a data descriptor specified by the instruction being accessed, the descriptor including the address of an operand and a characteristic of it (e.g. its length), the operand being fetched and used in conjunction with the characteristic to compute a hash address. As described the contents of a circulating register are shifted left before a four byte unit of the operand is added to it, the result being one's complemented and shifted left again before the same four byte unit is added, this process being repeated until all the four byte units specified by the length characteristic have been operated on. Data processing system.-The system comprises four semi-conductor memory modules (201, Fig. 2, not shown) interfaced via a sequencer (202) to an input/output controller (220) controlling, e.g. tape or disc stores and a CPU (200) the latter including a read only microprogram store (210), a data management unit (206), an address control unit (207) and an ALU (212). A buffer (204) stores the most recently or most frequently used data in the form of pages, a directory (205) keeping an index of pages in the store (204), address control unit (207) including an associative store with the base addresses of the most recently used memory segments and their segment number. Operation.-A hash instruction comprising an 8 bit op code (bits 0-7), 4 bit general register code (8-11) and a 20 bit address syllable (bits 12-31) is stored in an instruction register 400 (Fig. 4) of instruction set unit 208. The op code results in control store units 210 performing tests to determine (1) that bit 11 of the instruction is zero (since two registers are required for hash instruction), (2) whether bit 12 indicates direct or indirect addressing. The address syllable is used to fetch a data descriptor having a tag field of 01 indicating that a second (extended) descriptor is also to be fetched. The first descriptor contains the segment (STN, STE) and displacement (DISP) within the segment of the operand and the second which describes characteristics of the operand (e.g. type of coding, length) is transferred to register 408, bits 40-47 being fed to register 412 for comparison with predetermined constants loaded by the control store unit into register 414 to determine whether the data type is correct for "hashing", an illegal data type exception or a termination routine occurring otherwise. Hash operation.-If the data type is correct the hash operation is performed (flow drawing of Fig. 5). First bits 56-63 of the descriptor (representing the number of bytes of the operands) are accessed. The hash instruction operates on groups of 4 bytes, the number of groups of 4 bytes being stored in a register N of store 406 with the remainder in a register R. The absolute address of the operand is then developed and entered into a register S. The first 4 bytes of the operand are fetched and stored in register 422, the valve N is decremented by 1 and the address incremented by 4. The contents of circulation register 420 are rotated left 19 bits and the content of register 422 added to it, the result being replaced after one's complementing in register 420 (any carry being added to the lowermost bit). The register is then rotated left 18 bits and the contents of register 422 added to it. This process is repeated until N=0. The remainder bytes are then processed by first adding zeroes to make the remainder up to 4 bytes and then repeating the above process. Finally the contents of register 420 are rotated left 17 bits, added to the contents of register 422 with any overflow being added to the lowest bit, the result being. stored in a register specified by the instruction. This register now holds the random key address identifying the storage location for the left record in secondary storage, e.g. disc. A multiplication or division operation is executed to specify the page in which the record is to be stored.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US42439173A | 1973-12-13 | 1973-12-13 |
Publications (1)
Publication Number | Publication Date |
---|---|
GB1494750A true GB1494750A (en) | 1977-12-14 |
Family
ID=23682467
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB53774/74A Expired GB1494750A (en) | 1973-12-13 | 1974-12-12 | Data processing system with hash instruction |
Country Status (5)
Country | Link |
---|---|
JP (1) | JPS5093054A (en) |
CA (1) | CA1023476A (en) |
DE (1) | DE2458331A1 (en) |
FR (1) | FR2287724A1 (en) |
GB (1) | GB1494750A (en) |
Cited By (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2004099975A2 (en) * | 2003-05-12 | 2004-11-18 | International Business Machines Corporation | Processing message digest instructions |
EP1596281A2 (en) | 2004-05-14 | 2005-11-16 | Via Technologies, Inc. | Hash instruction |
FR2917197A1 (en) * | 2007-06-07 | 2008-12-12 | Thales Sa | METHOD OF MASKING THE RESULT OF A MODULAR MULTIPLICATION OPERATION AND ASSOCIATED DEVICE |
US7720220B2 (en) | 2003-05-12 | 2010-05-18 | International Business Machines Corporation | Cipher message assist instruction |
US7770024B2 (en) | 2003-05-12 | 2010-08-03 | International Business Machines Corporation | Security message authentication instruction |
US8924741B2 (en) | 2012-12-29 | 2014-12-30 | Intel Corporation | Instruction and logic to provide SIMD secure hashing round slice functionality |
US9027104B2 (en) | 2012-12-28 | 2015-05-05 | Intel Corporation | Instructions processors, methods, and systems to process secure hash algorithms |
US9912481B2 (en) | 2014-03-27 | 2018-03-06 | Intel Corporation | Method and apparatus for efficiently executing hash operations |
US10038550B2 (en) | 2013-08-08 | 2018-07-31 | Intel Corporation | Instruction and logic to provide a secure cipher hash round functionality |
US10503510B2 (en) | 2013-12-27 | 2019-12-10 | Intel Corporation | SM3 hash function message expansion processors, methods, systems, and instructions |
US10592245B2 (en) | 2014-09-26 | 2020-03-17 | Intel Corporation | Instructions and logic to provide SIMD SM3 cryptographic hashing functionality |
US10623175B2 (en) | 2014-09-04 | 2020-04-14 | Intel Corporation | SM3 hash algorithm acceleration processors, methods, systems, and instructions |
-
1974
- 1974-12-10 DE DE19742458331 patent/DE2458331A1/en not_active Withdrawn
- 1974-12-12 CA CA215,903A patent/CA1023476A/en not_active Expired
- 1974-12-12 GB GB53774/74A patent/GB1494750A/en not_active Expired
- 1974-12-12 FR FR7441024A patent/FR2287724A1/en active Granted
- 1974-12-13 JP JP49142629A patent/JPS5093054A/ja active Pending
Cited By (35)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8103860B2 (en) | 2003-05-12 | 2012-01-24 | International Business Machines Corporation | Optional function multi-function instruction |
US9424055B2 (en) | 2003-05-12 | 2016-08-23 | International Business Machines Corporation | Multi-function instruction that determines whether functions are installed on a system |
WO2004099975A3 (en) * | 2003-05-12 | 2006-01-05 | Ibm | Processing message digest instructions |
GB2416609A (en) * | 2003-05-12 | 2006-02-01 | Ibm | Processing message digest instructions |
GB2416609B (en) * | 2003-05-12 | 2006-03-22 | Ibm | Processing message digest instructions |
US7159122B2 (en) | 2003-05-12 | 2007-01-02 | International Business Machines Corporation | Message digest instructions |
US8661231B2 (en) | 2003-05-12 | 2014-02-25 | International Business Machines Corporation | Multi-function instruction that determines whether functions are installed on a system |
WO2004099975A2 (en) * | 2003-05-12 | 2004-11-18 | International Business Machines Corporation | Processing message digest instructions |
CN1799024B (en) * | 2003-05-12 | 2010-04-28 | 国际商业机器公司 | Method and system for processing message digest instructions |
US7720220B2 (en) | 2003-05-12 | 2010-05-18 | International Business Machines Corporation | Cipher message assist instruction |
US7725736B2 (en) | 2003-05-12 | 2010-05-25 | International Business Machines Corporation | Message digest instruction |
US7770024B2 (en) | 2003-05-12 | 2010-08-03 | International Business Machines Corporation | Security message authentication instruction |
US8255703B2 (en) | 2003-10-10 | 2012-08-28 | Via Technologies, Inc. | Atomic hash instruction |
US8132022B2 (en) | 2003-10-10 | 2012-03-06 | Via Technologies, Inc. | Apparatus and method for employing configurable hash algorithms |
US8132023B2 (en) | 2003-10-10 | 2012-03-06 | Via Technologies, Inc. | Apparatus and method for performing transparent hash functions |
US7921300B2 (en) | 2003-10-10 | 2011-04-05 | Via Technologies, Inc. | Apparatus and method for secure hash algorithm |
EP1596281A3 (en) * | 2004-05-14 | 2008-01-02 | Via Technologies, Inc. | Hash instruction |
EP1596281A2 (en) | 2004-05-14 | 2005-11-16 | Via Technologies, Inc. | Hash instruction |
FR2917197A1 (en) * | 2007-06-07 | 2008-12-12 | Thales Sa | METHOD OF MASKING THE RESULT OF A MODULAR MULTIPLICATION OPERATION AND ASSOCIATED DEVICE |
US10581594B2 (en) | 2012-12-28 | 2020-03-03 | Intel Corporation | Instructions processors, methods, and systems to process secure hash algorithms |
US9027104B2 (en) | 2012-12-28 | 2015-05-05 | Intel Corporation | Instructions processors, methods, and systems to process secure hash algorithms |
US9251377B2 (en) | 2012-12-28 | 2016-02-02 | Intel Corporation | Instructions processors, methods, and systems to process secure hash algorithms |
US9542561B2 (en) | 2012-12-28 | 2017-01-10 | Intel Corporation | Instructions processors, methods, and systems to process secure hash algorithms |
US10911222B2 (en) | 2012-12-28 | 2021-02-02 | Intel Corporation | Instructions processors, methods, and systems to process secure hash algorithms |
US10009172B2 (en) | 2012-12-28 | 2018-06-26 | Intel Corporation | Instructions processors, methods, and systems to process secure hash algorithms |
US8924741B2 (en) | 2012-12-29 | 2014-12-30 | Intel Corporation | Instruction and logic to provide SIMD secure hashing round slice functionality |
US10148428B2 (en) | 2012-12-29 | 2018-12-04 | Intel Corporation | Instruction and logic to provide SIMD secure hashing round slice functionality |
US10686591B2 (en) | 2012-12-29 | 2020-06-16 | Intel Corporation | Instruction and logic to provide SIMD secure hashing round slice functionality |
US10038550B2 (en) | 2013-08-08 | 2018-07-31 | Intel Corporation | Instruction and logic to provide a secure cipher hash round functionality |
US10503510B2 (en) | 2013-12-27 | 2019-12-10 | Intel Corporation | SM3 hash function message expansion processors, methods, systems, and instructions |
US9912481B2 (en) | 2014-03-27 | 2018-03-06 | Intel Corporation | Method and apparatus for efficiently executing hash operations |
US10623175B2 (en) | 2014-09-04 | 2020-04-14 | Intel Corporation | SM3 hash algorithm acceleration processors, methods, systems, and instructions |
US11075746B2 (en) | 2014-09-04 | 2021-07-27 | Intel Corporation | SM3 hash algorithm acceleration processors, methods, systems, and instructions |
US11128443B2 (en) | 2014-09-04 | 2021-09-21 | Intel Corporation | SM3 hash algorithm acceleration processors, methods, systems, and instructions |
US10592245B2 (en) | 2014-09-26 | 2020-03-17 | Intel Corporation | Instructions and logic to provide SIMD SM3 cryptographic hashing functionality |
Also Published As
Publication number | Publication date |
---|---|
DE2458331A1 (en) | 1975-06-19 |
CA1023476A (en) | 1977-12-27 |
JPS5093054A (en) | 1975-07-24 |
FR2287724B1 (en) | 1977-11-10 |
AU7590974A (en) | 1976-06-03 |
FR2287724A1 (en) | 1976-05-07 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PS | Patent sealed | ||
PCNP | Patent ceased through non-payment of renewal fee |