GB1466272A - Phased array radar antenna systems - Google Patents

Abstract

1466272 Aerial arrays SIEMENS AG 25 June 1974 [28 June 1973] 28012/74 Heading H4A A phased array radar antenna system incorporates a phase computing circuit which electronically controls the beam sweep, the antenna consisting of radiator elements arranged in rows and columns, each individual element current phase being adjusted by the phase computing circuit, which controls a respective phase shift device via associated stores for each element. A single pulse controlled computer digitally generates the common vertical phases within the individual rows, the output of the vertical computer being fed, via a shift register which has the same number of stages as there are horizontal rows, to respective horizontal phase computers which are connected to respective element rows, so that one horizontal computer may control several or all of the rows, the output of the or each horizontal computer being connected to each respective row of element stores, selectively, and in response to a specific count produced by a counter connected to the radar pulse control system, in time-division multiplex fashion. In the Fig. 6 embodiment, which may apply to either a radiation-fed antenna array comprising elemental radiators R, phase shift devices P and stores ESP, in which case a precomputer VOR is provided which computes from the focusing parameters A x , A y and B and the horizontal and vertical sweep movements H, V from radar control generator the inputs to vertical computer VRW<SP>1</SP>, which computes the combined phase, or, a line fed antenna array in which computer VOR is absent, the complexity of known systems is reduced by dispensing with a horizontal computer for each individual row, by taking into account the computing time available between radar pulses. A reduced number of horizontal computers HRW are provided to be sequentially switched through a plurality of rows of elements, each row being activated sequentially by a signal from gating device G controlled by counter Z1. In another embodiment, the horizontal computers are switched by switches (U, Fig. 5, not shown) controlled by a counter (Z).