GB1460788A - Electronic counter - Google Patents

Abstract

1460788 Electronic counters INTERNATIONAL BUSINESS MACHINES CORP 10 May 1974 [11 June 1973] 20661/74 Heading G4A [Also in Division H3] Each stage of a counter includes a dynamic logic recirculating memory 11 and a dynamic logic shift circuit 21, the latter having an input for an advance signal and being arranged to propagate the signal to later stages in synchronism with the recirculation of the memory, the shift circuit having an inhibit input connected to the output of the preceding memory stage 33 to inhibit propagation of the advance signal to later stages if the preceding stage contains a logical zero. The circuit comprises field effect transistor gates (Fig. 4, not shown), controlled by a four phase clock (figures within the logic symbols denote clock phases). The true output of the memory from inverter 47 or the inverted output from inverter 49 are fed back to OR-gate 41 once per clock cycle depending on whether AND gate 43 or 45 is enabled by inverter 57 and OR gate 51 respectively. When an advance input is received at 23 and no inhibit signal at 31, gate 45 is enabled and the memory changes its condition; otherwise gate 43 is enabled and the memory is recharged to its previous condition. In another embodiment, Fig. 5, there are five octal stages 501-509 (Fig. 7, not shown), each comprising three binary memory circuits and the shift circuit (Fig. 6, not shown), has a plurality of propagating paths to increase the speed of operation.