GB1460431A - Memory systems - Google Patents

Abstract

1460431 Memory system NATIONAL RESEARCH DEVELOPMENT CORP 3 Jan 1974 [8 Jan 1973] 968/73 Headings G4A and G4C An associative memory includes a plurality of memory devices storing multi-bit words and each having an associated match bistable, means comparing successive bits in each memory device with successive bits of a required identifier and, when a mismatch is detected in respect of any memory device, resetting the associated match bistable, means inhibiting the comparison in respect of each memory device whose match bistable is reset, and means reading out the contents of a selected one of the memory devices whose match bistables are set. As described each data word consists of a name field, a key field indicating the priority of the data word, and a multiple match bit which is always 1, followed by a data field. The name and key fields may be used together or alone, in each case with or without the multiple match bit except that when this bit is not used no two data words may have the same name or key fields, or, where both are used, the same name and key fields. Each data item normally recirculates, via gate 23, in a respective shift register S 0 -S 511 which may be an integrated circuit device. When a new data item is to be loaded the transfer flipflops 17 down to that associated with the first empty shift register working from right to left (indicated by free bistables 25) are set and the remainder reset so that the contents of all full registers are transferred left one register via gates 22 and the rightmost register is loaded with the new data. Other procedures, e.g. loading data into the first free register or maintaining data items in the leftmost registers are mentioned. To perform a search the match bistables 13 are set to pass via gates 11 data from each shift register for comparison with a required name field stored in register 28 at exclusive-OR gates 33. Any mismatch resets the corresponding match bistable and inhibits the corresponding gate 11 preventing any further comparison in the register for which the mismatch occurred. The comparison may be made while a new item is being entered although the new item does not participate in the search. When the name fields have been compared, and assuming more than one match bistable remains set, the key fields are compared, at gates 33, with the output, via AND 39, of OR/DECODE network 38 which consists of the OR combination of like bits from the key fields of all registers still participating, thereby to select the highest key field and therefore the highest priority data word. If at the end of the key field more than one match bistable still remains set DECODE network 38 operates on the multiple match bits of all registers still participating. These bits are fed via the corresponding gates 11 to respective inputs Zi and the network 38 produces outputs Yj such that all Y j = 1 where j indicates a register to the right of the leftmost register still participating (i.e. where Z = 1) and Yj = 0 for all other. The signals Yj = 1 reset their associated match bistables via gates 40 and 34 so that only one set match bistable, corresponding to the leftmost, i.e. oldest, entry whose name and key fields produced a match, remains. The following data field of the selected register is then loaded into the output register 36 via the OR network 38, and gates 39 and 32, the name field, key field, and multiple match bit having been loaded from name register 28 via gates 31, 32 and from OR network 38 via gates 39 and 32. The multiple match bit in register 36 indicates via line 42 whether a match was obtained for the name and key fields since otherwise all gates 11 would have been blocked and OR network 38 and gates 39 and 32 would have produced a zero in the appropriate bit. To set the transfer bistables 17 to permit a new entry the outputs of the "free" bistables 25 are gated, via 47, to the decode network 38 which operates as in the case of a multiple match to produce signals Yi which are used to set the transfer bistables. During loading, which involves the shifting leftwards by one register, the states of each free bistable 25 are transferred to the free bistable next to the left and the first free bistable is reset to indicate that the first register is occupied. The registers may be cleared by setting all free bistables 25 to indicate that all registers are empty so that any data subsequently entered overwrites that in the system. Figs. 2, 3, and 4 (not shown) illustrate the details of OR/DECODE network 38 which is formed of OR gates. It is stated that the shift register stores could be replaced by a core matrix. The data searched may relate to interrupt requests in a data processing system, the name field identifying the interrupt and the key field giving its priority.